SG10201802435TA - Gallium nitride semiconductor structure and process for fabricating thereof - Google Patents

Gallium nitride semiconductor structure and process for fabricating thereof

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Publication number
SG10201802435TA
SG10201802435TA SG10201802435TA SG10201802435TA SG10201802435TA SG 10201802435T A SG10201802435T A SG 10201802435TA SG 10201802435T A SG10201802435T A SG 10201802435TA SG 10201802435T A SG10201802435T A SG 10201802435TA SG 10201802435T A SG10201802435T A SG 10201802435TA
Authority
SG
Singapore
Prior art keywords
gallium nitride
layer
fabricating
nitride semiconductor
semiconductor structure
Prior art date
Application number
SG10201802435TA
Inventor
Kaplun Joseph
Houli Arbiv Bilha
Original Assignee
Elta Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elta Systems Ltd filed Critical Elta Systems Ltd
Publication of SG10201802435TA publication Critical patent/SG10201802435TA/en

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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    • H01L33/005—Processes
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    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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    • H01L33/0093—Wafer bonding; Removal of the growth substrate
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

02542256\1-01 GALLIUM NITRIDE SEMICONDUCTOR STRUCTURE AND PROCESS FOR FABRICATING THEREOF A semiconductor substrate structure and process for fabrication of the semiconductor substrate structure are described. The semiconductor substrate structure 5 includes a silicon carbide (SiC) wafer substrate, an active gallium nitride (GaN) layer and a layer of microcrystalline diamond (MCD) layer disposed between the SiC wafer substrate and the GaN active layer. The MCD) layer is bonded to the SiC wafer substrate and to the GaN active layer. 10 Fig 2
SG10201802435TA 2017-06-20 2018-03-23 Gallium nitride semiconductor structure and process for fabricating thereof SG10201802435TA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IL253085A IL253085B (en) 2017-06-20 2017-06-20 Gallium nitride semiconductor structure and process for fabricating thereof

Publications (1)

Publication Number Publication Date
SG10201802435TA true SG10201802435TA (en) 2019-02-27

Family

ID=60942723

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SG10201802435TA SG10201802435TA (en) 2017-06-20 2018-03-23 Gallium nitride semiconductor structure and process for fabricating thereof

Country Status (5)

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US (1) US10388752B2 (en)
EP (1) EP3419061B1 (en)
KR (1) KR102549134B1 (en)
IL (1) IL253085B (en)
SG (1) SG10201802435TA (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11652146B2 (en) * 2020-02-07 2023-05-16 Rfhic Corporation Method of forming a semiconductor wafer containing a gallium-nitride layer and two diamond layers
CN115020205A (en) * 2022-05-05 2022-09-06 广东奔朗新材料股份有限公司 Low-interface-thermal-resistance diamond-based wafer and low-temperature bonding method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2835096B1 (en) 2002-01-22 2005-02-18 PROCESS FOR MANUFACTURING SELF-CARRIER SUBSTRATE OF SINGLE-CRYSTALLINE SEMICONDUCTOR MATERIAL
US7033912B2 (en) 2004-01-22 2006-04-25 Cree, Inc. Silicon carbide on diamond substrates and related devices and methods
WO2006113539A2 (en) 2005-04-13 2006-10-26 Group4 Labs, Llc Semiconductor devices having gallium nitride epilayers on diamond substrates
US8309967B2 (en) * 2007-05-31 2012-11-13 Chien-Min Sung Diamond LED devices and associated methods
JP2009076694A (en) * 2007-09-20 2009-04-09 Panasonic Corp Nitride semiconductor device and method for manufacturing the same
WO2010015878A2 (en) * 2008-08-06 2010-02-11 S.O.I. Tec Silicon On Insulator Technologies Process for modifying a substrate
US8921239B2 (en) * 2009-12-15 2014-12-30 Soitec Process for recycling a substrate
GB201121659D0 (en) 2011-12-16 2012-01-25 Element Six Ltd Substrates for semiconductor devices
GB201121666D0 (en) 2011-12-16 2012-01-25 Element Six Ltd Synthetic diamond coated compound semiconductor substrates
CN104285001A (en) 2012-02-29 2015-01-14 六号元素技术美国公司 Gallium-nitride-on-diamond wafers and manufacturing equipment and methods of manufacture
US9259818B2 (en) * 2012-11-06 2016-02-16 Sinmat, Inc. Smooth diamond surfaces and CMP method for forming
US9111750B2 (en) 2013-06-28 2015-08-18 General Electric Company Over-voltage protection of gallium nitride semiconductor devices
US9601327B2 (en) 2014-08-15 2017-03-21 The Board Of Regents Of The University Of Oklahoma High-power electronic device packages and methods

Also Published As

Publication number Publication date
IL253085B (en) 2021-06-30
KR102549134B1 (en) 2023-06-28
EP3419061B1 (en) 2021-09-29
KR20180138138A (en) 2018-12-28
EP3419061A1 (en) 2018-12-26
US20180366558A1 (en) 2018-12-20
US10388752B2 (en) 2019-08-20
IL253085A0 (en) 2017-12-31

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