CN115020205A - Low-interface-thermal-resistance diamond-based wafer and low-temperature bonding method thereof - Google Patents
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Abstract
The invention provides a diamond-based wafer with low interface thermal resistance and a low-temperature bonding method thereof, belonging to the technical field of diamond and gallium nitride bonding; the method comprises the following steps: s1, respectively carrying out surface activation on the diamond and the semiconductor wafer through plasma etching treatment; s2, respectively depositing nanometer-sized gradient layers; s3, inverting one of the wafers obtained in the step S2 to enable the gradient layers on the two wafers to be mutually contacted; s4, then bonding is carried out under the bonding condition; the gradient layer is sequentially provided with an initial layer, a transition layer and an end layer, wherein the initial layer is selected from at least one of Ti, Ta, Cr, Ni, W and Mo, and the end layer is Ag; the thickness of the initial layer is not more than 5nm, the thickness of the transition layer is not more than 10nm, and the thickness of the finish layer is not more than 15 nm. The invention has the advantages of lower interface thermal resistance, high bonding strength and lower requirement on bonding environment.
Description
Technical Field
The invention relates to the technical field of diamond and gallium nitride bonding, in particular to a diamond-based wafer with low interface thermal resistance and a low-temperature bonding method thereof.
Background
Due to the self-heating effect of the GaN-based power device and the low thermal conductivity of the original substrate, the power output capability is reduced, the stability and the reliability of the device are affected, and the performance of the device is seriously degraded. Diamond, however, has an ultra-high thermal conductivity and a very small coefficient of thermal expansion, and thus is the preferred substrate material. However, the large lattice mismatch and difference in thermal expansion coefficient between materials make high quality integration of GaN with diamond quite difficult. Diamond and GaN bonding is a feasible method, and the principle is to combine two or more materials into a whole through van der waals force, molecular force and even atomic force, so as to improve the integration level of wafers, which is an indispensable important link in the field of semiconductor manufacturing. The bonding of GaN and diamond is a parallel process, a GaN layer and a diamond substrate can be respectively prepared, the low-temperature bonding technology can avoid the lattice mismatch and the difference of thermal expansion coefficients generated by high-temperature growth of GaN, and simultaneously, the problem of low thermal conductivity of the nucleation layer is avoided. Metal bonding is a promising technology, and metal bonds are formed between metal atoms at a bonding interface by depositing a nanocrystalline metal film on two wafers to be bonded, then contacting the surfaces of the wafers with each other, and applying a certain temperature and pressure to promote metal atom diffusion and grain growth. The metal bonding can ensure that the bonding interface has high bonding strength, and the metal material has high thermal conductivity, thereby being beneficial to reducing the interface thermal resistance. The metal bonding can realize low-temperature bonding, and avoids damage to devices under high-temperature conditions.
In general, bonding diamond and GaN through a metal intermediate layer is required to satisfy requirements of high bonding strength, low interface thermal resistance, low bonding temperature, and the like. For example, in a method for heterogeneously integrating a diamond-based gallium nitride high-electron-mobility transistor reported in patent CN 109860049 a, W and Au are used as an intermediate layer, so that the method has the advantages of high bonding strength, good heat dissipation effect, simple process, no need of harsh conditions such as ultrahigh vacuum, high flatness and high-temperature annealing, and is successfully applied to the preparation of a diamond-based GaN HEMT.
However, in the conventional metal bonding method, the bonding intermediate layer has a multi-layer structure, which may generate more interface thermal resistance; in addition, the bonding strength is difficult to ensure by adopting normal-temperature Au bonding, and the wafer bonding success rate is obviously influenced by the processing state of the substrate. Therefore, developing a bonding system which reduces bonding interfaces as much as possible and has lower requirements on bonding environment has important significance for the semiconductor material integration process applicable to a heat dissipation system.
Disclosure of Invention
The invention aims to solve the technical problem of providing a diamond-based wafer with low interface thermal resistance and a low-temperature bonding method thereof, which have the advantages of low interface thermal resistance, high bonding strength and low requirement on bonding environment. The method is particularly suitable for the application requirements of the semiconductor material integration field for some temperature sensitive devices. The method has low bonding temperature and high bonding interface thermal conductivity, and is suitable for integrating semiconductor materials with large difference of thermal expansion coefficients.
In order to solve the technical problems, the invention provides the following technical scheme:
in a first aspect, a low interface thermal resistance diamond-based wafer low-temperature bonding method is provided, which includes the following steps:
s1, respectively carrying out surface activation on the diamond and the semiconductor wafer through plasma etching treatment;
s2, respectively depositing nanometer-sized gradient layers on the surfaces of the diamond and the semiconductor wafer which are activated on the surface in the step S1;
s3, inverting one of the wafers obtained in the step S2 to enable the gradient layers on the two wafers to be mutually contacted;
s4, and then bonding under the bonding condition.
The diamond is a material with ultrahigh heat conductivity, and the diamond is used as a heat dissipation substrate of power devices such as GaN and the like, so that the heat dissipation capability of a near-junction region of the device can be effectively improved, the peak temperature is reduced, and the maximum output power and the reliability of the device are greatly improved.
Wherein, preferably, the thickness of the diamond is 400-600 μm, and the thickness of the semiconductor wafer is 1-3 μm. This preferred embodiment is more advantageous for adaptation to a specific gradient layer.
The semiconductor wafer may or may not include a substrate, and may be, for example, a semiconductor wafer or a silicon-based semiconductor wafer.
The gradient layer is sequentially provided with an initial layer, a transition layer and an end layer, wherein the initial layer is at least one of Ti, Ta, Cr, Ni, W and Mo, and the end layer is Ag. It is understood that the transition layer is a compositionally graded layer of the initial layer elements and the end layer Ag.
The thickness of the gradient layer is below 30 nm.
Preferably, the thickness of the initial layer is not more than 5nm, the thickness of the transition layer is not more than 10nm, and the thickness of the end layer is not more than 15 nm. With this preferred embodiment, the influence of the intermediate layer on the properties of the semiconductor materials after bonding can be reduced to the maximum.
Wherein, preferably, the diamond and the semiconductor wafer in the step S1 both satisfy: the surface evenness is less than 3 mu m, and the roughness Rq is less than or equal to 2 nm. Under the preferred scheme, the semiconductor substrate material is more adaptive to the deposition of a specific gradient layer, so that the interface bonding strength is more favorably improved.
Preferably, the semiconductor wafer is selected from one or more semiconductor materials of GaN, Si, Ge, GaAs, InP, GaO, SiC and AlN.
The plasma etching process in step S1 may be ICP, RIE or other low temperature plasma processing methods. Preferably, the plasma etching process in step S1 is specifically to bombard the surface of the bonded wafer with ICP Ar plasma.
Wherein, preferably, the conditions of the surface activation in step S1 include: at a vacuum degree of 3X 10 -3 Below Pa, RF power of 40-60W, and processing atmosphere of oxygen-free protective atmosphere for 40-80 s. The optimal scheme is more beneficial to removing adsorbed gas and natural oxide layers, removing oxygen atom adsorption of the bonding surface, not obviously changing the surface roughness of the bonding surface, increasing the bonding strength and the bonding success rate, cleaning the surface of the wafer, increasing the activation energy, and simultaneously enabling the surface of the wafer to have proper flatness and roughness, thereby being beneficial to bonding of a specific gradient layer. The plasma treatment time should not be too long and the energy should not be too high, otherwise the surface roughness will be increased.
The protective atmosphere without oxygen can be selected from Ar, N 2 And H and 2 and the like non-O atmosphere.
Preferably, the low-temperature bonding method further includes a wafer surface cleaning step before performing step S1: ultrasonically cleaning with acetone or isopropanol for 10-30min, ultrasonically cleaning with anhydrous ethanol for 10-20min, ultrasonically cleaning with deionized water for 10-20min, taking out, and blow-drying with protective gas.
The protective gas includes, but is not limited to, nitrogen, inert gas, and the like.
In some embodiments, the washing step specifically comprises: ultrasonically cleaning the glass substrate by using acetone or isopropanol for 15 minutes, ultrasonically cleaning the glass substrate by using absolute ethyl alcohol for 10 minutes, ultrasonically cleaning the glass substrate by using deionized water for 10 minutes, taking out the glass substrate after cleaning, and blow-drying the glass substrate by using nitrogen for later use.
Here, the deposition in step S2 may be sputtering or evaporation. Preferably, the deposition in step S2 is physical vapor deposition.
The deposition is preferably carried out by means of multi-target reactive magnetron sputtering to produce a gradient layer.
The gradient layer containing the transition layer is arranged, so that the transition layer has no obvious interface, and the stress is gradually released, the bonding force can be obviously improved, and the stress mismatch between the film layer and the substrate is reduced.
The conditions of low temperature, low power and short time are required to be met during deposition so as to ensure that the deposited gradient layer is in a proper nanometer size. Wherein, preferably, the process of depositing in step S2 includes:
at vacuum degree of 5X 10 -4 Below Pa, firstly carrying out pre-sputtering, wherein the sputtering power is 90-110W, the Ar gas flow is 40-60sccm, and the pre-sputtering time is 10-20 min;
then, beginning to deposit an initial layer, adjusting the flow of argon gas to 20-30sccm, adjusting the sputtering power to 90-110W, adjusting the cavity pressure to 0.2-0.4Pa, and adjusting the deposition time to 30-50s, thereby completing the process of plating the initial layer;
then opening an Ag target to start co-sputtering, gradually increasing the power of the Ag target from 9-12W to 90-110W, gradually decreasing the power of the initial layer target from 90-110W to 0W, and finishing the deposition of the transition layer with the co-sputtering time of 50-70 s;
and depositing an end layer Ag after the co-sputtering is finished, keeping the cavity pressure and the argon flow unchanged, and continuing sputtering for 80-200s at 90-110W to finish the deposition of the end layer. Under the preferred scheme, each layer is uniformly deposited on the whole wafer surface, and a deposition layer with proper grain size and proper thickness can be obtained, so that low-temperature bonding is realized.
In the deposition method, the grain size of the precipitated nano Ag layer is less than 10nm, so that low-temperature bonding is facilitated.
Step S3 of the present invention is to perform lamination, and the specific operation may be: and attaching the surfaces of the side surfaces of the wafers plated with the metal layers together, putting the wafer into a template with the size corresponding to that of the wafers, putting the template into bonding equipment for fixing, and aligning the upper wafer and the lower wafer by using the template.
Wherein, preferably, the bonding conditions in step S4 include: the ambient vacuum degree is 1 × 10 -3 Gradually applying pressure to a wafer on the top part under Pa to enable the pressure to reach 0.1-0.3MPa within 30 s; then the upper and the lower are alignedThe wafer is heated at the same time, the heating temperature is 200 ℃ and 250 ℃, and the wafer is kept for 10-20 min.
After the bonding is finished, the interface of the middle layer is reduced, gradient transition is formed, the element concentration of the initial layer is higher when the initial layer is closer to the wafer, and the Ag element concentration is higher when the initial layer is closer to the middle.
The specific operation of the bonding may be: and after the wafer is placed into bonding equipment, designing parameters such as pressure, temperature and time according to the thickness of the gradient layer. And applying pressure on the top of the wafer, keeping the inside of the equipment in a vacuum state during bonding, simultaneously heating the upper wafer and the lower wafer, naturally cooling the sample along with the equipment after bonding is finished, taking out the sample, and then completing bonding to form the low-temperature metal bonding of the semiconductor material.
Preferably, the low-temperature bonding method further includes, before the bonding in step S4, performing pre-bonding:
and under the atmospheric condition at room temperature, applying the pressure of 0.1-0.2MPa to a wafer at the top, keeping for 8-12min, gradually reducing the pressure to 0, and finishing prebonding.
The method can be popularized to the bonding of various semiconductor materials, such as Si/Si bonding, Si/diamond bonding, Si/GaN bonding and the like, and condition optimization is carried out according to specific materials. The period and the thickness of the gradient layer can be adjusted according to the stress and the lattice mismatch degree, so that the gradient transition of the structure and the stress is formed.
In a second aspect, a diamond-based wafer with low interface thermal resistance prepared by the low-temperature bonding method of the first aspect is provided.
The bonding strength of the diamond-based wafer is more than 5MPa, and the interface bonding rate is more than 95%.
The technical scheme of the invention has the following beneficial effects:
1. the gradient layer with the specific thickness is used as the middle layer, the heat conductivity is good, the gradient layer can play a role of a heat conduction layer, the heat conductivity of Ag in metal is very high (429W/m.K), and the integration process of Si/diamond, GaN/diamond and the like suitable for a heat dissipation system can be realized.
2. The gradient layer with the transition layer and the proper thickness is adopted between the surface layer and the bottom layer metal for transition, so that introduction of multiple interfaces is reduced, interface scattering in a phonon/electron coupling transmission process is prevented, stress gradient change is realized, and bonding strength and interface thermal conductivity are obviously improved.
3. The gradient layer for bonding contains nano Ag, the deposited nano Ag with proper thickness has low melting point, and the low-temperature bonding from normal temperature to 250 ℃ can be realized. The low-temperature bonding method can reduce the mismatching of the thermal expansion coefficients of different materials to the maximum extent, and avoid the problems of wafer warping and the like caused by the defects generated by a high-temperature process and stress increase.
4. The process is simple, the conditions are easy to obtain, and subsequent high-temperature annealing or ultrahigh vacuum environment is not needed. The requirement on the surface roughness of the bonded wafer is low, and the surface does not need complex treatment.
5. Compared with Au-Au bonding, the method has lower cost and higher interface thermal conductivity.
Drawings
FIG. 1 illustrates a raw semiconductor substrate material with a smooth surface;
FIG. 2 illustrates Ti plating on a smooth original substrate surface;
FIG. 3 shows the plating of a gradient layer on the Ti surface;
FIG. 4 shows Ag plating on the surface of the gradient layer;
fig. 5 shows the semiconductor material after bonding is completed.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
Example 1
1) The silicon-based gallium nitride and the single crystal diamond are used as original substrate wafers, the size of the original substrate is 5 multiplied by 5mm, the thickness of the diamond is 500 mu m, the surface flatness is less than 3 mu m, and the surface roughness Rq is 0.4nm, the silicon-based gallium nitride is prepared on a silicon substrate by adopting the Metal Organic Chemical Vapor Deposition (MOCVD) technology, wherein the thickness of a gallium nitride layer is 2 mu m, the surface flatness is less than 3 mu m, and the surface roughness Rq is 0.8 nm. Firstly, cleaning the surface of a wafer, ultrasonically cleaning the surface of the wafer by using isopropanol for 15min, then transferring the wafer into absolute ethyl alcohol for ultrasonic cleaning for 10min, finally transferring the wafer into deionized water for ultrasonic cleaning for 10min, and drying the wafer by using nitrogen for standby, wherein the method is shown in figure 1;
2) ICP argon plasma treatment. Putting the cleaned wafer into ICP equipment, and vacuumizing the equipment to 3 multiplied by 10 -3 Pa below, the RF power is 50W, the processing atmosphere is argon, and the processing time is 50 s;
3) respectively depositing Ti (5nm), Ti/Ag (10nm) and Ag (10nm) films on the surfaces of the diamond and the GaN by a magnetron sputtering method. Putting two wafers into equipment for sputtering; the apparatus was evacuated to 5X 10 -4 Pa below; firstly, pre-sputtering a target, setting the sputtering power to be 100W, the Ar gas flow to be 50sccm, and the pre-sputtering time to be 15 min; firstly, depositing Ti, adjusting the flow of argon to 23.5sccm, sputtering power of 100W, cavity pressure of 0.3Pa and deposition time of 40s, and finishing the Ti plating process, as shown in FIG. 2; at the moment, opening the Ag target to start co-sputtering, gradually increasing the power of the Ag target from 10W to 100W, gradually decreasing the power of the Ti target from 100W to 0W, and finishing the deposition of the transition film with the co-sputtering time of 60s, as shown in FIG. 3; depositing Ag after the co-sputtering is finished, keeping the parameters unchanged, and sputtering for 100s at 100W to finish the deposition of the Ag film, as shown in FIG. 4;
4) pre-bonding, namely, attaching the surfaces of one side of a wafer deposition film together, placing diamond below and GaN above into bonding equipment, fixing the wafer through a mold, aligning the upper wafer and the lower wafer, and fixing the mold in the equipment; applying 0.1MPa pressure to the top of the wafer under the atmospheric condition at room temperature, keeping for 10 minutes, gradually reducing the pressure to 0, and finishing prebonding;
5) and (4) bonding. After the prebonding is completed, the equipment is vacuumed to 1 × 10 -3 Pa below; gradually applying pressure to the top wafer to reach 0.15MPa within 30 s; heating an upper wafer and a lower wafer at the same time, wherein the temperature is 250 ℃; holding at the above temperature and pressure conditions for 15 minutes;
6) after bonding, heating is stopped, the pressure is gradually reduced, the sample is taken out after being cooled to 80 ℃ along with the equipment, and gradient transition is formed in the middle layer, as shown in fig. 5.
The obtained diamond-based semiconductor wafer had a bonding strength of 6MPa and a bonding rate of 97%.
Example 2
1) Silicon and polycrystalline diamond are used as original substrate wafers, the original substrate size is 10 multiplied by 10mm, the diamond thickness is 500 mu m, the surface flatness is less than 3 mu m, the surface roughness Rq is 0.8nm, the silicon wafer thickness is 625 mu m, the surface flatness is less than 3 mu m, and the surface roughness Rq is 0.9 nm. Firstly, cleaning the surface of a wafer, ultrasonically cleaning the surface of the wafer by using isopropanol for 15min, then transferring the wafer into absolute ethyl alcohol for ultrasonic cleaning for 10min, finally transferring the wafer into deionized water for ultrasonic cleaning for 10min, and drying the wafer by using nitrogen for later use;
2) ICP argon plasma treatment. Putting the cleaned wafer into ICP equipment, and vacuumizing the equipment to 3 multiplied by 10 -3 Pa below, the RF power is 50W, the processing atmosphere is argon, and the processing time is 50 s;
3) respectively depositing Ti (5nm), Ti/Ag (10nm) and Ag (15nm) films on the surfaces of the diamond and the silicon wafer by adopting a magnetron sputtering method. Putting two wafers into equipment for sputtering; the apparatus was evacuated to 5X 10 -4 Pa below; firstly, pre-sputtering a target material, setting the sputtering power to be 100W, the Ar gas flow to be 50sccm, and the pre-sputtering time to be 15 min; firstly, depositing Ti, adjusting the flow of argon to 23.5sccm, sputtering power of 100W, cavity pressure of 0.3Pa and deposition time of 40s to finish the Ti plating process; opening an Ag target to start co-sputtering, gradually increasing the power of the Ag target from 10W to 100W, gradually decreasing the power of the Ti target from 100W to 0W, and finishing the deposition of the transition film with the co-sputtering time of 60 s; depositing Ag after the co-sputtering is finished, keeping the parameters unchanged, and sputtering for 140s at 100W to finish the deposition of the Ag film;
4) pre-bonding, namely, attaching the surfaces of one side of a wafer deposition film together and putting the wafer deposition film into bonding equipment, fixing the wafer through a die, aligning an upper wafer and a lower wafer, and fixing the die in the equipment; applying 0.15MPa pressure to the top of the wafer under the atmospheric condition at room temperature, keeping for 10 minutes, gradually reducing the pressure to 0, and finishing prebonding;
5) and (6) bonding. After the prebonding is completed, the equipment is vacuumed to 1 × 10 -3 Pa below; gradually applying pressure to the top wafer to reach 0.2MPa within 30 s; heating an upper wafer and a lower wafer at the same time, wherein the temperature is 250 ℃; maintaining the temperature and pressure for 15minA clock;
6) and after bonding is finished, stopping heating, gradually reducing the pressure, cooling the sample to 80 ℃ along with the equipment, and taking out the sample, wherein the gradient transition is formed in the middle layer.
The bonding strength of the prepared composite wafer is 5.2MPa, and the bonding rate is 97%.
Comparative example 1
The procedure is as in example 1, except that the deposition conditions are adjusted so that Ti/Ag (50nm) is deposited, the other layers being unchanged; wherein the codeposition conditions are: the Ag target power is gradually increased from 10W to 100W, the Ti target power is gradually decreased from 100W to 0W, and the co-sputtering time is 540 s.
The bonding strength of the prepared composite wafer is 4.7MPa, and the bonding rate is 93%.
Comparative example 2
The procedure is as in example 1, except that Ni is used as initial layer, the thickness is 5nm, the transition layer is Ni/Ag (50nm), and the other layers are unchanged; the deposition conditions were the same as in comparative example 1.
The bonding strength of the prepared composite wafer is 2.8MPa, and the bonding rate is 88%.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A low-interface thermal resistance diamond-based wafer low-temperature bonding method is characterized by comprising the following steps:
s1, respectively carrying out surface activation on the diamond and the semiconductor wafer through plasma etching treatment;
s2, respectively depositing nanometer-sized gradient layers on the surfaces of the diamond and the semiconductor wafer which are activated on the surface in the step S1;
s3, inverting one of the wafers obtained in the step S2 to enable the gradient layers on the two wafers to be mutually contacted;
s4, then bonding is carried out under the bonding condition;
the gradient layer is sequentially provided with an initial layer, a transition layer and an end layer, wherein the initial layer is selected from at least one of Ti, Ta, Cr, Ni, W and Mo, and the end layer is Ag; the thickness of the initial layer is not more than 5nm, the thickness of the transition layer is not more than 10nm, and the thickness of the finish layer is not more than 15 nm.
2. The low temperature bonding method of claim 1, wherein the diamond and the semiconductor wafer in step S1 both satisfy: the surface evenness is less than 3 mu m, and the roughness Rq is less than or equal to 2 nm.
3. The low temperature bonding method according to claim 1,
in the step S1, the plasma etching treatment is specifically to bombard the surface of the bonded wafer by ICPAr plasma;
and/or, the conditions of the surface activation in the step S1 include: at a vacuum degree of 3X 10 -3 Below Pa, RF power of 40-60W, and treating atmosphere of oxygen-free protective atmosphere for 40-80 s.
4. The low temperature bonding method of claim 1, further comprising a wafer surface cleaning step before performing step S1:
ultrasonically cleaning with acetone or isopropanol for 10-30min, ultrasonically cleaning with anhydrous ethanol for 10-20min, ultrasonically cleaning with deionized water for 10-20min, taking out, and blow-drying with protective gas.
5. The low temperature bonding method of claim 1, wherein the semiconductor wafer is selected from one or more semiconductor materials of GaN, Si, Ge, GaAs, InP, GaO, SiC, AlN.
6. The low-temperature bonding method according to claim 1, wherein the deposition process in step S2 includes:
at vacuum degree of 5X 10 -4 Under Pa, pre-sputtering and sputteringThe jet power is 90-110W, the Ar gas flow is 40-60sccm, and the pre-sputtering time is 10-20 min;
then starting to deposit an initial layer, adjusting the flow of argon gas to 20-30sccm, adjusting the sputtering power to 90-110W, the cavity pressure to 0.2-0.4Pa and the deposition time to 30-50s, and finishing the working procedure of plating the initial layer;
then opening an Ag target to start co-sputtering, gradually increasing the power of the Ag target from 9-12W to 90-110W, gradually decreasing the power of the initial layer target from 90-110W to 0W, and finishing the deposition of the transition layer with the co-sputtering time of 50-70 s;
and depositing an end layer Ag after the co-sputtering is finished, keeping the cavity pressure and the argon flow unchanged, and continuing sputtering for 80-200s under 90-110W to finish the deposition of the end layer.
7. The low-temperature bonding method according to claim 1, wherein the bonding conditions in step S4 include: the ambient vacuum degree is 1 × 10 -3 Gradually applying pressure to a wafer on the top part under Pa to enable the pressure to reach 0.1-0.3MPa within 30 s; then, the upper and lower wafers are heated at the same time, the heating temperature is 200 ℃ and 250 ℃, and the heating time is kept for 10-20 min.
8. The low temperature bonding method of claim 1, further comprising, prior to the bonding in step S4, further performing pre-bonding:
and under the atmospheric condition at room temperature, applying the pressure of 0.1-0.2MPa to a wafer at the top, keeping for 8-12min, gradually reducing the pressure to 0, and finishing prebonding.
9. A diamond-based wafer with low interfacial thermal resistance prepared by the low temperature bonding method of any one of claims 1 to 8.
10. The diamond-based wafer according to claim 1, wherein the diamond-based wafer has a bonding strength of 5MPa or more and an interfacial bonding rate of more than 95%.
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