WO2022237080A1 - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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Publication number
WO2022237080A1
WO2022237080A1 PCT/CN2021/125943 CN2021125943W WO2022237080A1 WO 2022237080 A1 WO2022237080 A1 WO 2022237080A1 CN 2021125943 W CN2021125943 W CN 2021125943W WO 2022237080 A1 WO2022237080 A1 WO 2022237080A1
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Prior art keywords
region
layer
mask layer
shallow trench
trench isolation
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PCT/CN2021/125943
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English (en)
French (fr)
Inventor
张权
姚兰
周璐
Original Assignee
长江存储科技有限责任公司
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Publication date
Priority claimed from PCT/CN2021/103677 external-priority patent/WO2022236944A1/en
Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to CN202180003702.3A priority Critical patent/CN114175232A/zh
Publication of WO2022237080A1 publication Critical patent/WO2022237080A1/zh
Priority to US18/089,451 priority patent/US20230126267A1/en

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Definitions

  • the invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
  • CMOS Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor
  • the planar transistor structure will have a serious short-channel effect, which seriously affects the device performance.
  • the invention provides a method for manufacturing a semiconductor device, which includes:
  • a substrate is provided, the substrate includes a first region and a second region; a first shallow trench isolation structure located in the first region and at least two first shallow trench isolation structures located in the second region are formed in the substrate Two shallow trench isolation structures; forming a second mask layer on the substrate, the first shallow trench isolation structure and the at least two second shallow trench isolation structures; The second mask layer in the second region and the at least two second shallow trench isolation structures are used to form a semiconductor protrusion between two adjacent second shallow trench isolation structures.
  • a first mask layer is formed on the substrate; the sequential etching of the second mask layer located in the second region and the at least two second shallow trench isolation structures includes: Forming a second photoresist layer on the second mask layer; sequentially etching the second photoresist layer and the second mask layer in the second region until the first mask in the second region is exposed layer and at least two second shallow trench isolation structures; removing the second photoresist layer located in the first region; taking the exposed first mask layer and the remaining second mask layer located in the second region as mask to etch the at least two second shallow trench isolation structures.
  • forming the second photoresist layer on the second mask layer includes: forming a protective layer on the second mask layer; forming the second photoresist layer on the protective layer .
  • a first device oxide layer located in the first region and a second device oxide layer in the second region are also formed between the substrate and the first mask layer; the etching at least After the two second shallow trench isolation structures, further comprising: removing the first mask layer and the remaining second mask layer; forming a supplementary oxide layer on both sides of the semiconductor protrusion to extend the The second device oxide layer.
  • the second mask layer is silicon nitride or polysilicon; when the second mask layer is polysilicon, the removal of the first mask layer and the remaining second mask layer includes : Doping carbon or germanium on both sides of the semiconductor protrusion; removing the remaining second mask layer and the first mask layer in sequence.
  • the carbon doping on both sides of the semiconductor protrusion includes: forming a third mask layer on the remaining second mask layer; using the third mask layer and the The first mask layer is a mask, and the two sides of the semiconductor protrusion are doped with carbon or germanium.
  • a supplementary oxide layer on both sides of the semiconductor protrusion to extend the second device oxide layer it further includes: forming a first gate layer on the first device oxide layer; A second gate layer is formed on the second device oxide layer.
  • the thickness of the first device oxide layer in the first direction is greater than the thickness of the second device oxide layer in the first direction.
  • forming a first shallow trench isolation structure located in the first region and at least two second shallow trench isolation structures located in the second region in the substrate includes: An isolation groove is formed in the isolation groove, and the isolation groove includes a first sub-isolation groove located in the first region and at least two second sub-isolation grooves located in the second region; The first region and the second region form the first shallow trench isolation structure and the at least two second shallow trench isolation structures.
  • filling the isolation trenches with an isolation material includes: depositing the isolation material in the isolation trenches and on the first mask layer to fill up the isolation trenches; planarizing the isolation trenches. material, so that the isolation material in the isolation groove is flush with the first mask layer.
  • the material of the first mask layer is silicon nitride.
  • the second mask layer is silicon nitride or polysilicon; when the second mask layer is polysilicon, the substrate, the first shallow trench isolation structure and at least two Forming a second mask layer on the second shallow trench isolation structure includes: forming a buffer on the first mask layer, the first shallow trench isolation structure, and the second shallow trench isolation structure layer; forming the second mask layer on the buffer layer.
  • the buffer layer has a thickness ranging from 8 nm to 9 nm.
  • the first region is used to form a planar transistor
  • the second region is used to form a fin transistor
  • the first shallow trench isolation structure is higher than the substrate, and the substrate is higher than the trench isolation structure.
  • the present invention also provides a semiconductor device, which includes: a substrate, the substrate includes a first region and a second region; first shallow trenches respectively located in the first region and the second region A trench isolation structure and at least two second shallow trench isolation structures, with a semiconductor protrusion between two adjacent second shallow trench isolation structures; the first device oxide layer located in the first region, and the first device oxide layer located in the first region a second device oxide layer covering the second region and covering the semiconductor protrusion; a first gate layer located on the first device oxide layer, and a second gate layer located on the second device oxide layer .
  • the first region is used to form a planar transistor
  • the second region is used to form a fin transistor
  • the first shallow trench isolation structure is higher than the substrate, and the substrate is higher than the second shallow trench isolation structure.
  • the thickness of the first device oxide layer in the first direction is greater than the thickness of the second device oxide layer in the first direction.
  • Fig. 1 is a flow chart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention
  • Fig. 2 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention.
  • FIG. 3 is a flowchart of another manufacturing method of a semiconductor device provided by an embodiment of the present invention.
  • 4A to 4P are schematic cross-sectional structure diagrams of semiconductor devices at various stages according to embodiments of the present invention.
  • 5A-5B are schematic cross-sectional structural views of a semiconductor device when a buffer layer is formed when the second mask layer is polysilicon provided by an embodiment of the present invention.
  • FIGS. 6A-6B are schematic cross-sectional structure diagrams of a semiconductor device in a doping stage when the second mask layer is polysilicon provided by an embodiment of the present invention.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected, or electrically connected, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction of two components relation.
  • installation connection
  • connection connection
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected, or electrically connected, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction of two components relation.
  • a first feature being “on” or “under” a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them.
  • “above”, “above” and “above” the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.
  • “Below”, “beneath” and “under” the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.
  • CMOS Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor
  • the existing low-voltage device area generally uses FinFET (Fin Field-Effect Transistor, Fin Field-Effect Transistor), and it becomes very difficult to form a FinFET process that meets its performance requirements in the high-voltage device area, so that The high-voltage device area still uses planar transistors.
  • FinFET Fin Field-Effect Transistor, Fin Field-Effect Transistor
  • the shallow trench isolation structures of the high-voltage device region and the low-voltage device region are formed simultaneously in the existing semiconductor device, the shallow trench isolation structures of the high-voltage device region and the low-voltage device region are the same.
  • the existing formation methods cannot meet the actual needs because planar transistors and FinFETs have different requirements for shallow trench isolation structures. .
  • the invention provides a semiconductor structure and a manufacturing method thereof, which effectively solves the problem that the existing shallow trench isolation structure cannot meet the structural requirements of different regions in the semiconductor device at the same time.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.
  • the specific flow of the method can be as follows:
  • Step S101 providing a substrate, the substrate includes a first region and a second region.
  • FIG. 4A a schematic cross-sectional structure diagram after step S101 is completed is shown in FIG. 4A .
  • the material of the substrate 10 may be semiconductor materials such as silicon, germanium, or silicon-on-insulator (Silicon-On-Insulator, SOI).
  • the substrate 10 may include a first region (A region) and a second region (B region), wherein the A region includes a high-voltage device region, and the A region can be used to form the plane in the embodiment of the present invention.
  • B region includes a low-voltage device region (the operating voltage of the device in the low-voltage device region is lower than the operating voltage of the device in the high-voltage device region), and further, the low-voltage device region can also include the first low-voltage region b1 and the second low-voltage region b2 , wherein, the relationship between the operating voltages of the devices (such as transistors or CMOS tubes) in the high-voltage device region, the first low-voltage region, and the second low-voltage region can be successively decreasing.
  • the devices such as transistors or CMOS tubes
  • area B is used to give a general illustration of b1 and b2; specifically, area B can be a low-voltage device area, or it can contain b1 and b2 at the same time.
  • Figure 4B-4O uses area B to include a low-voltage device area Take this as an example.
  • the B region is used to form the fin transistor (FinFET) in the embodiment of the present invention.
  • FinFET the fin transistor
  • the gate can surround the channel from three sides, which increases the control area of the gate to the channel, so that the gate control capability is greatly improved. Enhanced, so that the short channel effect can be effectively suppressed and the subthreshold leakage current can be reduced.
  • the performance of different device regions can be adjusted by changing the channel width of one or more transistors inside the device, and the channel width of FinFET is proportional to the height of the fin structure. Since the high-voltage device region requires a higher driving voltage, therefore The height of the "Fin" (fin structure) of the corresponding FinFET is also relatively high, and it is difficult to form a gate structure surrounded by three sides on the higher Fin, so the A region still uses a planar transistor.
  • a first device oxide layer 11A located in the first region and a second device oxide layer 11B located in the second region are also formed on the substrate 10 , and the first device oxide layer 11A is located in the second region.
  • the thickness H 1 in the first direction (the y direction in the figure) is greater than the thickness H 2 of the second device oxide layer 11B in the first direction.
  • the formation process of the first device oxide layer 11A and the second device oxide layer 11B includes a thermal oxidation process (Thermal Oxidation), a light plasma oxidation process (Soft Plasma Oxidation) or an ultraviolet assisted oxidation process (UV Photo Assistant Oxidation), and in this example, when the substrate 10 is selected to be a silicon or germanium substrate, the second device oxide layer 11B can be formed at the same time as the first device oxide layer 11A is formed. At this time, the first device oxide layer The components of 11A and the second device oxide layer 11B are both silicon oxide or germanium oxide.
  • the composition of the first device oxide layer 11A and the second device oxide layer 11B may also be different according to whether the A region or the B region of the substrate 10 is doped in advance, for example, the second device oxide layer 11B may not contain silicon oxide containing chlorine, and the first device oxide layer 11A is silicon oxide containing chlorine.
  • the first device oxide layer 11A and the second device oxide layer 11B are respectively used as the gate oxide layer of the high-voltage device and the low-voltage device.
  • the leakage current of the first device oxide layer 11A in the first direction (y direction in the figure), that is, the thickness H1 in the thickness direction of the substrate 10 is greater than that of the second device oxide layer 11B in the first direction.
  • the thickness H 2 in one direction in order to achieve a corresponding thickness relationship, the first device oxide layer 11A and the second device oxide layer 11B may be formed step by step or simultaneously.
  • chlorine ions can be doped in the A region in advance. Since the A region is doped with chlorine ions, the oxidation speed of the substrate 10 in the A region is accelerated.
  • the formed first device The oxide layer 11A is thicker than the second device oxide layer 11B.
  • the first step under the same time and process conditions, form the device oxide layer with the same thickness in the first region and the second region; the second step, selectively etch the device oxide layer in the second region , so that the thickness of the second device oxide layer located in the second region is smaller than the thickness of the first device oxide layer located in the first region.
  • a first mask layer 12 located on the first device oxide layer 11A and the second device oxide layer 11B is formed on the substrate 10 .
  • the first mask layer 12 is a hard mask layer, wherein the function of the hard mask layer is to transfer the specific pattern on the photoresist to the substrate, that is, first transfer the specific pattern from the photoresist to the substrate. Transferred to the hard mask layer, because the hard mask layer has hard and dense characteristics, it has better shape retention ability, and a relatively complete pattern can be obtained when the pattern is etched and transferred to the substrate 10 through the hard mask layer. picture of.
  • the specific material of the first mask layer 12 can be silicon nitride or titanium nitride.
  • first device oxide layer 11A and the second device oxide layer 11B are beneficial to relieve the stress on the substrate 10 caused by the formation of the silicon nitride layer (that is, the first mask layer 12).
  • the silicon nitride layer may be formed through an LPCVD process.
  • Step S102 forming a first STI structure located in the first region and at least two second STI structures located in the second region in the substrate.
  • FIG. 2 is a flowchart of another semiconductor device manufacturing method provided by an embodiment of the present invention.
  • Step S102 may specifically include:
  • Step S1021 forming isolation trenches in the substrate, the isolation trenches include a first sub-isolation trench located in the first region and at least two second sub-isolation trenches located in the second region;
  • FIG. 4D a schematic cross-sectional structure diagram after step S1021 is completed is shown in FIG. 4D .
  • the function of the isolation trench 101 is to be filled with a dielectric material to prevent electrical coupling between the transistor structures.
  • a photoresist pattern defining the position of the isolation groove 101 and having openings can be formed by coating a first photoresist layer (not shown in the figure) on the surface of the first mask layer 12 and performing photolithography processes such as exposure and development, Then, the first mask layer 12, the first device oxide layer 11A, and the second device oxide layer 11B are etched through the openings of the first photoresist layer by reactive ion etching or plasma etching to expose the surface of the substrate 10, Then, the substrate 10 is etched with fluorine-containing etching gas, and the first mask layer 12 is used as a mask, so that an isolation groove 101 is formed in the substrate 10, and the isolation groove 101 includes a first sub-isolation groove 101A and a sub-isolation groove 101A.
  • At least two second sub-isolation trenches 101B the first sub-isolation trench 101A is located in area A, the second sub-isolation trench 101B is located in area B, the first sub-isolation trench 101A and at least two second sub-isolation trenches 101B can be selected in the same Formed in one step in the etching process, that is, the two can have the same height in the first direction; the first sub-isolation trench 101A and the second sub-isolation trench 101B can also be formed in different etching processes, that is, the two There may also be different heights in the first direction, and corresponding heights may be set according to different degrees of electrical insulation requirements.
  • S1022 Fill the isolation trench with an isolation material to form the first shallow trench isolation structure and the at least two second shallow trench isolation structures in the first region and the second region, respectively.
  • step S1022 may specifically include: depositing the isolation material in the isolation trench and on the first mask layer to fill up the isolation trench; planarizing the isolation material so that the isolation material in the isolation trench and The first mask layer is even.
  • the isolation material 13 can be deposited in the isolation trench 101 and on the first mask layer 12 by a high-density plasma chemical vapor deposition process to fill the isolation trench 101, and then planarization process, such as a chemical mechanical polishing process, to planarize the isolation material 13, so that the isolation material 13 in the isolation trench 101 is flush with the first mask layer 12.
  • planarization process such as a chemical mechanical polishing process
  • the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B may be formed in the same process step or in different process steps, because the first sub-isolation trench 101A and the The heights of the second sub-isolation trenches 101B may be the same or different, therefore, the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B may be of equal height or different heights, and may be based on different degrees of electrical insulation Set the corresponding height for isolation requirements.
  • Step S103 forming a second mask layer on the substrate, the first STI structure and the at least two second STI structures.
  • FIG. 4G a schematic cross-sectional structure after step S103 is completed is shown in FIG. 4G .
  • the second mask layer 14 is a hard mask layer, and the specific material may also be silicon nitride or polysilicon.
  • the silicon nitride layer can be formed specifically by the LPCVD process. .
  • the material of the second mask layer 14 can be selected to be polysilicon, which can avoid this phenomenon.
  • the materials selected for the second mask layer are different, there are also differences in the formation process of the second mask layer 14 and the subsequent process of removing the second mask layer 14 .
  • the material of the second mask layer 14 is polysilicon, please refer to FIGS.
  • step S103 may specifically include: A buffer layer 17 is formed on the second shallow trench isolation structure, and the structure after this step is completed is shown in FIG. 5A ; the second mask layer 14 is formed on the buffer layer, and the structure after this step is completed is shown in FIG. 5B .
  • the function of the buffer layer 17 is to better combine the second mask layer 14 made of polysilicon with the first mask layer 12 .
  • the material of the buffer layer 17 can be selected as silicon oxide or other materials that help to bond the second mask layer 14 made of polysilicon to the first mask layer 12.
  • the corresponding thickness range of the buffer layer 17 is preferably 8nm ⁇ 9nm.
  • Step S104 sequentially etching the second mask layer located in the second region and the at least two second STI structures to form a semiconductor protrusion between two adjacent second STI structures.
  • FIG. 2 is a flow chart of another semiconductor device manufacturing method provided by an embodiment of the present invention.
  • Step S104 may specifically include:
  • Step S1041 forming a second photoresist layer on the second mask layer.
  • FIG. 4H a schematic cross-sectional structure diagram after step S1041 is completed is shown in FIG. 4H .
  • the material of the second mask layer 14 is selected as silicon nitride
  • the material of the protective layer 19 is preferably silicon oxide, which is used to avoid the second photoresist layer from being exposed to nitrogen.
  • the step S1061 may specifically include: forming a protection layer on the second mask layer; forming the second photoresist layer on the protection layer.
  • Step S1042 sequentially etching the second photoresist layer and the second mask layer in the second region until the first mask layer and at least two second shallow trench isolation structures in the second region are exposed.
  • step S1042 is completed is shown in FIG. 4J .
  • the second photoresist layer 15A having a pattern defining the B area can be formed by performing photolithography processes such as exposure and development on the second photoresist layer 15, and the second mask is etched according to the pattern. mold layer 14. Specifically, reactive ion etching or plasma etching can be used to etch the second mask layer 14 according to the pattern until as shown in FIG. Two shallow trench isolation structures 13B.
  • Step S1043 removing the second photoresist layer located in the first region.
  • step S1043 the schematic cross-sectional structure is shown in FIG. 4K , and the second photoresist layer 15A located in area A is removed by exposure and development.
  • Step S1044 Using the exposed first mask layer and the remaining second mask layer located in the second region as a mask, etch the at least two second shallow trench isolation structures.
  • FIG. 4L a schematic cross-sectional structure diagram after step S1044 is completed is shown in FIG. 4L .
  • step S1042 After the etching of the second mask layer 14 in the B area is completed, there is still a remaining second mask layer 14A in the A area, so the remaining second mask layer 14A is used to etch the at least two second shallow trenches.
  • the trench isolation structure 13B serves to protect the first shallow trench isolation structure 13A, and the exposed first mask layer 12 can prevent other structures in the B region from being etched except the second shallow trench isolation structure 13B .
  • the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B are set at the same height, after the second shallow trench isolation structure 13B is etched, the resulting trench isolation structure 13B ' is less than the height of the first shallow trench isolation structure 13A.
  • the second shallow trench isolation structure 13B is selected to be etched to be lower than the substrate 10. Therefore, the first shallow trench isolation structure A shallow trench isolation structure 13A is higher than the substrate 10, and the substrate 10 is higher than the trench isolation structure 13B', so that the substrate 10 protrudes from two adjacent trench isolation structures 13B' As the "Fin" of the FinFET in the B area, that is, the semiconductor protrusion 10B in the B area serves as the fin structure in the FinFET.
  • step S104 also include:
  • Step S105 removing the first mask layer and the remaining second mask layer.
  • FIG. 4M a schematic cross-sectional structure diagram after step S105 is completed is shown in FIG. 4M .
  • the top of the semiconductor protrusion 10B is covered with a part of the second device oxide layer 11B'.
  • hot phosphoric acid can be used to remove the remaining second mask layer 14A and the remaining second mask layer 14A by wet etching.
  • the first mask layer 12 can be used to remove the remaining second mask layer 14A and the remaining second mask layer 14A by wet etching.
  • the second mask layer 14 when the second mask layer 14 is made of polysilicon material and the first mask layer 12 is made of silicon nitride, the tetramethylammonium hydroxide (TMAH) solution can be used to remove the The second mask layer 14A in the first region is then removed with hot phosphoric acid to remove the remaining first mask layer 12. Since TMAH has a strong corrosion effect on polysilicon and single crystal silicon, in order to avoid When the second mask layer 14A is removed by the process, the semiconductor protrusion 10B in the B area is greatly damaged. In this embodiment, as shown in FIG. impurity; sequentially remove the remaining second mask layer and the first mask layer.
  • TMAH tetramethylammonium hydroxide
  • the step of carbon doping can protect the Fin structure, similarly to germanium.
  • the step of doping the two sides of the semiconductor protrusion with carbon or germanium includes: forming a third mask layer on the remaining second mask layer; using the third mask layer and The first mask layer located in the second region is a mask, and the two sides of the semiconductor protrusion are doped with carbon or germanium.
  • the third mask layer 18 is a photoresist material, and through the mask function of the third mask layer 18, carbon or germanium doping on the second mask layer 14A made of polysilicon is avoided. Therefore, when the second mask layer 14A is removed by TMAH solution, since the second mask layer 14A is not doped with carbon or germanium, the etching speed of the second mask layer 14A is much faster than that of etching the part of the isolation Therefore, the carbon or germanium doping step can protect the Fin structure corresponding to the part of the isolation trench sidewall 1011B, while other structures such as the second shallow trench located in the B region The insulation performance of the trench isolation structure 13B' will not be affected by the doping of carbon or germanium.
  • Step S106 forming a supplementary oxide layer on both sides of the semiconductor protrusion to extend the second device oxide layer.
  • FIG. 4N the schematic diagram of the structure after step 106 is completed is shown in FIG. 4N .
  • the semiconductor protrusion 10B may be oxidized by a direct thermal oxidation process to form a supplementary oxide layer on both sides of the semiconductor protrusion 10B, and the corresponding supplementary oxide layer is the same as that shown in FIG.
  • the second device oxide layer 11B′ constitutes an extended second device oxide layer 11B that surrounds the fin structure on three sides from the top and two sides 1011B.
  • the extended second device oxide layer 11B is used for the gate oxide layer of the FinFET structure.
  • FIG. 3 is a flowchart of another manufacturing method of a semiconductor device provided by an embodiment of the present invention. After step S106, it also includes:
  • Step S107 forming a first gate layer on the first device oxide layer.
  • Step S108 forming a second gate layer on the extended second device oxide layer.
  • FIG. 4O A schematic diagram of the structure after step 108 is completed is shown in FIG. 4O.
  • the first gate layer 16A is patterned and etched to form the gate of a planar transistor, and the second gate layer 16B is used as a FinFET.
  • the second gate layer 16B can surround the channel from three sides, increasing the control area of the gate to the channel, so that the gate control ability is greatly enhanced, so that the short channel effect can be effectively suppressed, and the sub-threshold value can be reduced. leakage current.
  • both the first gate layer 16A and the second gate layer 16B are metal, they are formed on different regions by Low Pressure Chemical Vapor Deposition.
  • the low-voltage device region also includes the first low-voltage region b1 and the second low-voltage region b2
  • the device oxide layer thicknesses of the first low-voltage region b1 and the second low-voltage region b2 can be the same or different. Set according to the breakdown voltage requirements of different low-voltage areas.
  • the method for forming devices in the first low-voltage region and the second low-voltage region is similar to the method for forming devices in a low-voltage device region.
  • the devices in the first low-voltage region and the devices in the second low-voltage region can be formed simultaneously or separately.
  • the first shallow trench isolation structure and the second shallow trench isolation structure are respectively formed in the first region and the second region, and then two adjacent second shallow trench isolation structures are formed.
  • the trench isolation structure is etched to obtain semiconductor protrusions, so that a shallow trench isolation structure meeting different regional structure requirements is formed on the semiconductor device, and it is also beneficial to form a FinFET on the semiconductor device based on the semiconductor protrusions, and slow down the short channel effect.
  • the present invention also provides a semiconductor device, which can be formed according to the above-mentioned manufacturing method.
  • the semiconductor device can be specifically used for peripheral circuits in a storage device.
  • the storage device can be a NAND chip .
  • the semiconductor device includes a substrate 10, a first shallow trench isolation structure 13A, a trench isolation structure 13B', a semiconductor protrusion 10B, a first device oxide layer 11A, a second device oxide layer 11B, a first gate layer 16A and The second gate layer 16B.
  • the material of the substrate 10 may be semiconductor materials such as silicon, germanium, or silicon-on-insulator (Silicon-On-Insulator, SOI).
  • the substrate 10 may include a first region (A region) and a second region (B region), wherein the A region includes a high-voltage device region, and the A region can be used to form the plane in the embodiment of the present invention.
  • B region includes a low-voltage device region (the operating voltage of the device in the low-voltage device region is lower than the operating voltage of the device in the high-voltage device region), and further, the low-voltage device region can also include the first low-voltage region b1 and the second low-voltage region b2 , wherein, the relationship between the operating voltages of the devices (such as transistors or CMOS tubes) in the high-voltage device region, the first low-voltage region, and the second low-voltage region can be successively decreasing.
  • the devices such as transistors or CMOS tubes
  • area B is used to give a general illustration of b1 and b2; specifically, area B can be a low-voltage device area, or it can contain b1 and b2 at the same time.
  • Figure 4B-4O uses area B to include a low-voltage device area Take this as an example.
  • the B region is used to form the fin transistor (FinFET) in the embodiment of the present invention.
  • FinFET the fin transistor
  • the gate can surround the channel from three sides, which increases the control area of the gate to the channel, so that the gate control capability is greatly improved. Enhanced, so that the short channel effect can be effectively suppressed and the subthreshold leakage current can be reduced.
  • the performance of different device regions can be adjusted by changing the channel width of one or more transistors inside the device, and the channel width of FinFET is proportional to the height of the fin structure. Since the high-voltage device region requires a higher driving voltage, therefore The height of the "Fin" (fin structure) of the corresponding FinFET is also relatively high, and it is difficult to form a gate structure surrounded by three sides on the higher Fin, so the A region still uses a planar transistor.
  • a first device oxide layer 11A located in the first region and a second device oxide layer 11B located in the second region are also formed on the substrate 10 , and the first device oxide layer 11A is located in the second region.
  • the thickness H 1 in the first direction (the y direction in the figure) is greater than the thickness H 2 of the second device oxide layer 11B in the first direction.
  • the formation process of the first device oxide layer 11A and the second device oxide layer 11B includes a thermal oxidation process (ThermalOxidation), a light plasma oxidation process (SoftPlasmaOxidation) or an ultraviolet-assisted oxidation process (UVPhotoAssistantOxidation), and
  • the substrate 10 is selected as a silicon substrate
  • the second device oxide layer 11B may be formed at the same time as the first device oxide layer 11A is formed.
  • the first device oxide layer 11A and the second device oxide layer 11B The ingredients are silicon oxide.
  • the first device oxide layer 11A and the second device oxide layer 11B are respectively used as the gate oxide layer of the high-voltage device and the low-voltage device. Since the breakdown voltage requirements of the low-voltage device and the high-voltage device are different, in order to avoid excessive
  • the leakage current of the first device oxide layer 11A in the first direction (y direction in the figure), that is, the thickness H1 in the thickness direction of the substrate 10 is greater than that of the second device oxide layer 11B in the first direction.
  • the thickness H 2 in one direction in order to achieve a corresponding thickness relationship, the first device oxide layer 11A and the second device oxide layer 11B may be formed step by step or simultaneously. When using synchronous formation, chlorine ions can be doped in the A region in advance.
  • the first step under the same time and process conditions, form the device oxide layer with the same thickness in the first region and the second region; the second step, selectively etch the device oxide layer in the second region , so that the thickness of the second device oxide layer located in the second region is smaller than the thickness of the first device oxide layer located in the first region.
  • the first step under the same time and process conditions, form the device oxide layer with the same thickness in the first region and the second region; the second step, selectively etch the device oxide layer in the second region , so that the thickness of the second device oxide layer located in the second region is smaller than the thickness of the first device oxide layer located in the first region.
  • the second device oxide layer 11B surrounds the semiconductor protrusion 10B from both sides and the top of the semiconductor protrusion 10B, that is, the second device oxide layer 11B covers the FinFET from three sides.
  • the fin structure of the structure, the second device oxide layer 11B is used for the gate oxide layer of the FinFET structure.
  • the first STI structure 13A and the second STI structure 13B' are respectively located in the first region and the second region. Since the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B can have the same height, after the second shallow trench isolation structure 13B is etched, the height of the trench isolation structure 13B′ obtained is less than the height of the first shallow trench isolation structure 13A, further, in this embodiment, the second shallow trench isolation structure 13B is selected to be etched to be lower than the substrate 10, therefore, the first shallow trench The trench isolation structure 13A is higher than the substrate 10, and the substrate 10 is higher than the second shallow trench isolation structure 13B' after etching, so that the substrate 10 protrudes from two adjacent second shallow trenches Part of the isolation structure 13B' serves as the "Fin" of the FinFET in the B region, that is, the semiconductor protrusion 10B in the B region serves as the fin structure in the FinFET.
  • the semiconductor device further includes a first gate layer 16A on the first device oxide layer 11A and a second gate layer 16B on the second device oxide layer 12A.
  • the first gate layer 16A is patterned and etched to form the gate of a planar transistor
  • the second gate layer 16B is used as the gate of a FinFET
  • the second gate layer 16B can be viewed from three sides.
  • the control area of the gate to the channel is increased, so that the gate control ability is greatly enhanced, so that the short channel effect can be effectively suppressed, and the subthreshold leakage current can be reduced.
  • both the first gate layer 16A and the second gate layer 16B are metal, they are formed on different regions by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition).
  • the low-voltage device region also includes the first low-voltage region b1 and the second low-voltage region b2
  • the device oxide layer thicknesses of the first low-voltage region b1 and the second low-voltage region b2 can be the same or different, and the Set according to the requirements of the wear voltage.
  • the method for forming devices in the first low-voltage region and the second low-voltage region is similar to the method for forming devices in a low-voltage device region.
  • the devices in the first low-voltage region and the devices in the second low-voltage region can be formed simultaneously or separately.
  • the beneficial effects of the present invention are: different from the prior art, in the semiconductor device and its manufacturing method provided by the present invention, by forming the first shallow trench isolation structure and the second shallow trench in the first region and the second region respectively isolation structure, and then etched two adjacent second shallow trench isolation structures to obtain semiconductor protrusions, thereby forming shallow trench isolation structures that meet the structural requirements of different regions on the semiconductor device, and it is also beneficial to use the semiconductor protrusions in accordance with the FinFETs are formed on semiconductor devices to mitigate short channel effects.
  • the present invention can also have other implementations. All technical solutions formed by equivalent replacement or equivalent replacement fall within the scope of protection required by the present invention.

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Abstract

本发明提供一种半导体器件的制作方法，包括：提供衬底；在衬底中形成位于第一区域的第一浅沟槽隔离结构以及位于第二区域的至少两个第二浅沟槽隔离结构；形成第二掩膜层；依次刻蚀位于第二区域的第二掩膜层以及至少两个第二浅沟槽隔离结构，以于相邻两个第二浅沟槽隔离结构之间形成半导体突起。

Description

半导体器件及其制作方法
本申请要求于2021年5月12日提交的国际申请号为PCT/CN2021/093323的优先权以及于2021年6月30日提交的国际申请号为PCT/CN2021/103677的优先权，案件名称均为“MEMORY PERIPHERAL CIRCUIT HAVING THREE-DIMENSIONAL TRANSISTORS AND METHOD FOR FORMING THE SAME”，其全部内容通过引用并入本文。
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件及其制作方法。
背景技术
在现有集成电路的半导体器件中，通常包括高压器件区和低压器件区，二者都采用平面型晶体管。随着CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)工艺的快速发展，人们对于集成电路的集成度和性能要求越来越高，对应地，要求将半导体器件的特征尺寸进一步缩小，当特征尺寸按比例缩小到22nm时，平面型晶体管结构会出现严重的短沟道效应，严重地影响到器件性能。
技术解决方案
本发明提供一种半导体器件的制作方法，其包括：
提供衬底，所述衬底包括第一区域和第二区域；在所述衬底中形成位于所述第一区域的第一浅沟槽隔离结构以及位于所述第二区域的至少两个第二浅沟槽隔离结构；在所述衬底、所述第一浅沟槽隔离结构以及所述至少两个第二浅沟槽隔离结构上形成第二掩膜层；依次刻蚀位于所述第二区域的第二掩膜层以及所述至少两个第二浅沟槽隔离结构，以于相邻两个所述第二浅沟槽隔离结构之间形成半导体突起。
优选的，所述衬底上形成有第一掩膜层；所述依次刻蚀位于所述第二区域的第二掩膜层以及所述至少两个第二浅沟槽隔离结构，包括：在所述第二掩模 层上形成第二光阻层；依次刻蚀位于所述第二区域的第二光阻层以及第二掩膜层，直至暴露位于所述第二区域的第一掩膜层以及至少两个第二浅沟槽隔离结构；去除位于所述第一区域的第二光阻层；以暴露的第一掩模层和位于所述第二区域的剩余第二掩膜层为掩模，刻蚀所述至少两个第二浅沟槽隔离结构。
优选的，所述在所述第二掩模层上形成第二光阻层，包括：在所述第二掩膜层上形成保护层；在所述保护层上形成所述第二光阻层。
优选的，所述衬底与所述第一掩膜层之间还形成有位于所述第一区域的第一器件氧化层和所述第二区域的第二器件氧化层；所述刻蚀至少两个所述第二浅沟槽隔离结构之后，还包括：去除所述第一掩模层以及所述剩余第二掩模层；在所述半导体突起的两侧形成补充氧化层，以延展所述第二器件氧化层。
优选的，所述第二掩膜层为氮化硅或多晶硅；当所述第二掩膜层为多晶硅时，所述去除所述第一掩模层以及所述剩余第二掩模层，包括：对所述半导体突起的两侧进行碳或锗掺杂；依次去除所述剩余第二掩膜层以及所述第一掩膜层。
优选的，所述对半导体突起的两侧进行碳掺杂，包括：在所述剩余第二掩膜层上形成第三掩膜层；以所述第三掩膜层以及位于所述第二区域的第一掩膜层为掩膜，对所述半导体突起的两侧进行碳或锗掺杂。
优选的，所述在所述半导体突起的两侧形成补充氧化层，以延展所述第二器件氧化层之后，还包括：在所述第一器件氧化层上形成第一栅极层；在延展的所述第二器件氧化层上形成第二栅极层。
优选的，所述第一器件氧化层在第一方向上的厚度大于所述第二器件氧化层在所述第一方向上的厚度。
优选的，在所述衬底中形成位于所述第一区域的第一浅沟槽隔离结构以及位于所述第二区域的至少两个第二浅沟槽隔离结构，包括：在所述衬底中形成隔离槽，所述隔离槽包括位于第一区域的第一子隔离槽以及位于第二区域的至少两个第二子隔离槽；在所述隔离槽中填充隔离材料，以分别在所述第一区域和第二区域形成所述第一浅沟槽隔离结构和所述至少两个第二浅沟槽隔离结构。
优选的，所述在所述隔离槽中填充隔离材料包括：在所述隔离槽中及所述 第一掩膜层上沉积所述隔离材料，以填满所述隔离槽；平坦化所述隔离材料，以使所述隔离槽中的所述隔离材料与所述第一掩膜层平齐。
优选的，所述第一掩模层材料为氮化硅。
优选的，所述第二掩膜层为氮化硅或多晶硅；当所述第二掩膜层为多晶硅时，所述在所述衬底、所述第一浅沟槽隔离结构以及至少两个所述第二浅沟槽隔离结构上形成第二掩膜层，包括：在所述第一掩膜层、所述第一浅沟槽隔离结构以及所述第二浅沟槽隔离结构上形成缓冲层；在所述缓冲层上形成所述第二掩膜层。
优选的，所述缓冲层的厚度范围为8nm～9nm。
优选的，所述第一区域用于形成平面型晶体管，所述第二区域用于形成鳍式晶体管。
优选的，所述第一浅沟槽隔离结构高出所述衬底，且所述衬底高出所述沟槽隔离结构。
第二方面，本发明还提供一种半导体器件，其包括：衬底，所述衬底包括第一区域和第二区域；分别位于所述第一区域和所述第二区域的第一浅沟槽隔离结构和至少两个第二浅沟槽隔离结构，相邻两个所述第二浅沟槽隔离结构之间具有半导体突起；位于所述第一区域的第一器件氧化层，以及位于所述第二区域且包覆所述半导体突起的第二器件氧化层；位于所述第一器件氧化层上的第一栅极层，以及位于所述第二器件氧化层上的第二栅极层。
优选的，所述第一区域用于形成平面型晶体管，所述第二区域用于形成鳍式晶体管。
优选的，所述第一浅沟槽隔离结构高出所述衬底，且所述衬底高出所述第二浅沟槽隔离结构。
优选的，所述第一器件氧化层在第一方向上的厚度大于所述第二器件氧化层在所述第一方向上的厚度。
附图说明
图1是本发明实施例提供的一种半导体器件的制作方法流程图；
图2是本发明实施例提供的另一种半导体器件的制作方法流程图；
图3是本发明实施例提供的又一种半导体器件的制作方法流程图；
图4A～图4P是本发明实施例的半导体器件在各阶段时的剖面结构示意图；
图5A～图5B是本发明实施例提供的当第二掩膜层为多晶硅时，半导体器件在形成缓冲层时的剖面结构示意图。
图6A～图6B本发明实施例提供的当第二掩膜层为多晶硅时，半导体器件在掺杂阶段的剖面结构示意图。
本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上” 或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
在现有集成电路的半导体器件中，通常包括高压器件区和低压器件区，二者都采用平面型晶体管。随着CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)工艺的快速发展，人们对于集成电路的集成度和性能要求越来越高，对应地，要求将半导体器件的特征尺寸进一步缩小，当特征尺寸按比例缩小到22nm时，平面型晶体管结构会出现严重的短沟道效应，严重的影响到器件性能。为了解决这一问题，现有低压器件区一般改用FinFET(Fin Field-Effect Transistor，鳍式场效应晶体管)，而在高压器件区形成满足其性能需求FinFET的工艺就变得十分困难，以致于高压器件区仍然采用平面型晶体管。
由于现有半导体器件中高压器件区与低压器件区的浅沟槽隔离结构是同时形成的，故高压器件区与低压器件区的浅沟槽隔离结构相同。然而，当低压器件区改用FinFET，而高压器件区仍采用平面型晶体管时，由于平面型晶体管和FinFET对于浅沟槽隔离结构的要求各不相同，因此采用现有形成方法并不能满足实际需求。
本发明提供了一种半导体结构及其制作方法，有效地解决了现有浅沟槽隔离结构不能同时满足半导体器件中不同区域结构要求的问题。
请参阅图1，图1是本发明实施例所提供的一种半导体器件的制作方法的流程图，该制作方法的具体流程可以如下：
步骤S101:提供衬底，该衬底包括第一区域和第二区域。
其中，步骤S101完成后的剖面结构示意图如图4A所示。
具体的，该衬底10的材料可以为硅、锗或绝缘体上硅(Silicon-On-Insulator，SOI)等半导体材料。在本实施例中，该衬底10可以包括第一区域(A区)和第二区域(B区)，其中，A区包含高压器件区，该A区可用于形成本发明实施例中的平面型晶体管；B区包含低压器件区(低压器件区中的器件的工作电压小于高压器件区的器件的工作电压)，进一步的，低压器件区还可以包括第一低压区b1和第二低压区b2，其中，高压器件区、第一低压区以及第二低压区的器件(例如晶体管或CMOS管)的工作电压的大小关系可以是依次递减，在本实施例中，为了精简示图，在图4A后的附图中，用B区对b1及b2进行概括示意；具体的可以B区可以为一个低压器件区，也可以同时包含b1和b2，图4B-4O是以B区包含一个低压器件区为例进行说明。该B区用于形成本发明实施例中的鳍式晶体管(FinFET)，在FinFET中，栅极可从三面包围着沟道，增大了栅极对沟道的控制面积，使得栅控能力大大增强，从而可以有效抑制短沟道效应，减小亚阈值泄露电流。不同器件区的性能可以通过改变在器件内部的一个或多个晶体管的沟道宽度来调整，而FinFET的沟道宽度与鳍结构的高度成正比，由于高压器件区需要较高的驱动电压，因此对应的FinFET的“Fin”(鳍结构)的高度也较高，很难在较高的Fin上形成三面包围的栅极结构，故A区仍采用平面型晶体管。
其中，如图4B所示，该衬底10上还形成有位于该第一区域的第一器件氧化层11A与位于该第二区域的第二器件氧化层11B，该第一器件氧化层11A在第一方向(图中的y方向)上的厚度H 1大于该第二器件氧化层11B在该第一方向上的厚度H 2。
具体地，在本实施例中第一器件氧化层11A和第二器件氧化层11B的形成工艺包括热氧化工艺(Thermal Oxidation)、轻等离子体氧化工艺(Soft Plasma Oxidation)或者紫外辅助氧化工艺(UV Photo Assistant Oxidation)，且在本实例中选择衬底10为硅或锗衬底时，可选择在形成第一器件氧化层11A的同时，形 成第二器件氧化层11B，此时第一器件氧化层11A和第二器件氧化层11B的成分均为氧化硅或者氧化锗。其中，第一器件氧化层11A和第二器件氧化层11B的成分还可以根据是否预先在衬底10的A区或B区进行掺杂而存在差异，例如第二器件氧化层11B可以是不含氯的氧化硅，而第一器件氧化层11A是含氯的氧化硅。该第一器件氧化层11A和第二器件氧化层11B分别用作高压器件和低压器件的栅氧化层，由于低压器件和高压器件对于击穿电压的要求不同，为了避免在高压器件区出现过大的漏电流，该第一器件氧化层11A在第一方向上(图中的y方向)，也即在该衬底10的厚度方向上的厚度H 1大于该第二器件氧化层11B在该第一方向上的厚度H 2，为了实现对应的厚度关系，该第一器件氧化层11A和第二器件氧化层11B可在分步或者同步形成。当采用同步形成时，可预先在A区掺杂氯离子，由于A区掺杂了氯离子，A区中衬底10被氧化的速度加快，因此，在相同时间内，形成的该第一器件氧化层11A比第二器件氧化层11B更厚。当采用分步形成时，第一步：在相同时间和工艺条件下，在第一区域和第二区域形成相同厚度的器件氧化层；第二步，选择性刻蚀第二区域的器件氧化层，使得位于第二区域的第二器件氧化层的厚度小于位于第一区域的第一器件氧化层厚度。
其中，如图4C所示，该衬底10上还有形成有位于该第一器件氧化层11A与该第二器件氧化层11B上的第一掩膜层12。
具体的，该第一掩膜层12为硬掩膜层，其中，硬掩膜层的作用在于将光刻胶上的特定图形转移到衬底上，也即首先将特定图形从光刻胶上转移到硬掩膜层上，由于硬掩膜层具有坚硬以及致密的特性，因此具有较好的保形能力，通过硬掩模层最终将图形刻蚀转移到衬底10上时可以得到较为完整的图案。该第一掩膜层12具体材料可选择氮化硅或者氮化钛。另外，需要说明的是，第一器件氧化层11A和第二器件氧化层11B有利于减缓形成氮化硅层(也即第一掩膜层12)对衬底10的应力，在本实例中，可通过LPCVD工艺形成氮化硅层。
步骤S102:在该衬底中形成位于该第一区域的第一浅沟槽隔离结构以及位于该第二区域的至少两个第二浅沟槽隔离结构。
具体的，请参阅图2，图2是本发明实施例所提供的另一种半导体器件的制作方法的流程图，步骤S102具体可以包括：
步骤S1021:在该衬底中形成隔离槽，该隔离槽包括位于第一区域的第一子隔离槽以及位于第二区域的至少两个第二子隔离槽；
其中，步骤S1021完成后的剖面结构示意图如图4D所示。
该隔离槽101的作用在于被介电材料填满以防止晶体管结构之间的电性耦合。可通过在第一掩膜层12的表面涂布第一光阻层(图中未示出)并进行曝光、显影等光刻工艺以形成定义隔离槽101位置且具有开口的光刻胶图形，之后利用反应离子刻蚀或等离子刻蚀工艺经第一光阻层的开口刻蚀第一掩膜层12、第一器件氧化层11A、第二器件氧化层11B，以露出衬底10的表面，然后利用含氟刻蚀气体，再以第一掩膜层12为掩膜对衬底10进行刻蚀，从而在衬底10中形成隔离槽101，该隔离槽101包括第一子隔离槽101A和至少两个第二子隔离槽101B，第一子隔离槽101A位于A区，第二子隔离槽101B位于B区，第一子隔离槽101A和至少两个第二子隔离槽101B可选择在同一刻蚀工艺中步成形，即二者在第一方向上可具有相同的高度；第一子隔离槽101A和第二子隔离槽101B也可选择在不同的刻蚀工艺中形成，也即二者在第一方向上也可具有不同的高度，可根据不同程度的电绝缘隔离需求设置对应的高度。
S1022:在该隔离槽中填充隔离材料，以分别在该第一区域和第二区域形成该第一浅沟槽隔离结构和该至少两个第二浅沟槽隔离结构。
其中，步骤S1022具体可以包括：在该隔离槽中及该第一掩膜层上沉积该隔离材料，以填满该隔离槽；平坦化该隔离材料，以使该隔离槽中的该隔离材料与该第一掩膜层平齐。
具体的，如图4E，可通过高密度等离子体化学气相沉积工艺在该隔离槽101中及该第一掩膜层12上沉积该隔离材料13，以填满该隔离槽101，之后采用平坦化工艺，如化学机械抛光工艺，平坦化该隔离材料13，以使该隔离槽101中的隔离材料13与该第一掩膜层12平齐，此时，该第一浅沟槽隔离结构13A和第二浅沟槽隔离结构13B平齐，第一掩膜层12的作用还在于用作平坦化工艺中的停止层。步骤S1022完成后的剖面结构示意图如图4F所示。在本实施例中，该第一浅沟槽隔离结构13A和第二浅沟槽隔离结构13B可选择在同一工艺步骤中形成或者在不同的工艺步骤中形成，由于该第一子隔离槽101A和该第二子隔离槽101B的高度可以相同或者不同，因此，该第一浅沟槽隔离结构13A和第二 浅沟槽隔离结构13B可以为等高或不等高，可根据不同程度的电绝缘隔离需求设置对应的高度。
步骤S103:在该衬底、该第一浅沟槽隔离结构以及该至少两个第二浅沟槽隔离结构上形成第二掩膜层。
其中，步骤S103完成之后的剖面结构示意图如图4G所示。
具体的，该第二掩膜层14为硬掩膜层，具体材料也可为氮化硅或多晶硅。当第二掩膜层14选择为氮化硅层时，可避免在刻蚀中出现硬掩膜层脱皮翘起的问题(peeling defect)，本实施例中具体可通过LPCVD工艺形成氮化硅层。另外，当第二掩膜层14选择为氮化硅层时，采用惰性气体对氮化硅层进行刻蚀时，气体与氮化硅反应的副产物会在氮化硅层上形成针孔并对第一器件氧化层和/或第二器件氧化层损害，因此，本实施例中，可选择第二掩膜层14的材料为多晶硅，可避免出现这种现象。当第二掩膜层选择的材料不同时，第二掩膜层14的形成工艺和后续去除第二掩膜层14的工艺也存在差异。例如，当第二掩膜层14的材料为多晶硅时，请参阅图5A～图5B，步骤S103具体可以包括：在该第一掩膜层、该第一浅沟槽隔离结构以及该至少两个第二浅沟槽隔离结构上形成缓冲层17，该步骤完成后的结构如图5A所示；在该缓冲层上形成该第二掩膜层14，该步骤完成后的结构如图5B所示。其中，该缓冲层17的作用在于使以多晶硅为材料的第二掩膜层14与第一掩膜层12更好地结合。该缓冲层17的材料可以选择为氧化硅或其他有助于结合以多晶硅为材料的第二掩膜层14附着在第一掩膜层12上的材料，该缓冲层17对应的厚度范围优选为8nm～9nm。
步骤S104:依次刻蚀位于该第二区域的第二掩膜层以及该至少两个第二浅沟槽隔离结构，以于相邻两个该第二浅沟槽隔离结构之间形成半导体突起。
请参阅图2，图2是本发明实施例提供的另一种半导体器件的制作方法的流程图，步骤S104具体可以包括：
步骤S1041:在该第二掩模层上形成第二光阻层。
其中，步骤S1041完成后剖面结构示意图如图4H所示。在本实施例中，当第二掩膜层14的材料选择为氮化硅时，为了避免氮化硅材料对第二光阻层15造成的“中毒现象”，即为了避免氮化硅材料影响到第二光阻层15的形貌，在 形成第二光阻层15之前，可以预先形成保护层19，该保护层19的材料优选为氧化硅，用于避免第二光阻层的受到氮化硅材料的影响；该第二光阻层15为光刻胶，包括正性光刻胶或者负性光刻胶。因此，该步骤S1061具体可以包括：在该第二掩膜层上形成保护层；在该保护层上形成该第二光阻层。
步骤S1042:依次刻蚀位于该第二区域的第二光阻层以及第二掩膜层，直至暴露位于该第二区域的第一掩膜层以及至少两个第二浅沟槽隔离结构。
其中，步骤S1042完成后剖面结构示意图如图4J所示。
具体的，如图4I所示，可通过对第二光阻层15进行曝光、显影等光刻工艺以形成具有定义B区图案的第二光阻层15A，根据该图案刻蚀该第二掩模层14。具体的，可利用反应离子刻蚀或等离子刻蚀工艺根据该图案刻蚀该第二掩膜层14，直至如图4J所示，暴露位于B区的第一掩膜层12以及至少两个第二浅沟槽隔离结构13B。
步骤S1043:去除位于该第一区域的该第二光阻层。
其中，步骤S1043完成后剖面结构示意图如图4K所示，通过曝光及显影的方式去除位于A区的该第二光阻层15A。
步骤S1044:以暴露的第一掩模层和位于该第二区域的剩余第二掩膜层为掩模，刻蚀该至少两个第二浅沟槽隔离结构。
其中，步骤S1044完成后剖面结构示意图如图4L所示。
具体的，在步骤S1042中。在对B区的第二掩模层14刻蚀完毕后，A区中还存在残留的剩余第二掩膜层14A，故剩余第二掩膜层14A在刻蚀该至少两个第二浅沟槽隔离结构13B时起到保护该第一浅沟槽隔离结构13A的作用，而暴露的第一掩模层12可避免B区中除第二浅沟槽隔离结构13B以外的其他结构被刻蚀。另外，当该第一浅沟槽隔离结构13A和第二浅沟槽隔离结构13B设置为等高时，当对该第二浅沟槽隔离结构13B进行刻蚀后，得到的沟槽隔离结构13B’的高度小于该第一浅沟槽隔离结构13A的高度，更进一步的，在本实施例中，选择将第二浅沟槽隔离结构13B刻蚀至低出该衬底10，因此，该第一浅沟槽隔离结构13A高出该衬底10，且该衬底10高出该沟槽隔离结构13B’，使得该衬底10凸出于相邻的两个沟槽隔离结构13B’的部分作为B区中FinFET的“Fin”,也即B区中的半导体突起10B作为FinFET中的鳍结构。
请参阅图3，在步骤S104之后，还包括：
步骤S105:去除该第一掩膜层以及该剩余第二掩模层。
其中，步骤S105完成后剖面结构示意图如图4M所示。其中，步骤S105完成后，该半导体突起10B的顶部上覆盖有部分第二器件氧化层11B’。在本实例中，当该第一掩膜层12和剩余第二掩膜层14A同为氮化硅材料时，可使用热磷酸以湿法刻蚀的方式去除剩余第二掩膜层14A和剩该第一掩膜层12。需要说明的是，在本实施例中，当第二掩膜层14为多晶硅材料，第一掩膜层12为氮化硅材料时，可先采用四甲基氢氧化铵(TMAH)溶液去除该第一区域的该第二掩膜层14A，之后再用热磷酸移除剩余该第一掩膜层12，由于TMAH对多晶硅和单晶硅都具有较强的腐蚀作用，因此为了避免通过湿法工艺去除第二掩膜层14A时，大幅损伤到B区的半导体突起10B，在本实施例中，如图2所示，步骤S105具体可以包括：对该半导体突起的两侧进行碳或锗掺杂；依次去除该剩余第二掩膜层以及该第一掩膜层。
其中，由于TMAH溶液对碳掺杂后的该半导体突起的两侧1011B的刻蚀速度大幅减缓，因此，进行碳掺杂的步骤可以对Fin结构起到保护作用，同理如锗。
请参阅图6A～6B，其中，对该半导体突起的两侧进行碳或锗掺杂的步骤包括：在该剩余第二掩膜层上形成第三掩膜层；以该第三掩膜层以及位于该第二区域的第一掩膜层为掩膜，对该半导体突起的两侧进行碳或锗掺杂。
在本实施例中，第三掩膜层18为光刻胶材料，通过第三掩膜层18的掩膜作用，避免对以多晶硅为材料的第二掩膜层14A进行碳或锗掺杂，从而，在通过TMAH溶液去除该第二掩膜层14A时，由于该第二掩膜层14A未进行碳或锗掺杂，刻蚀的第二掩膜层14A的速度远大于刻蚀该部分隔离槽侧壁1011B的速度，因此，进行碳或锗掺杂的步骤可以对该部分隔离槽侧壁1011B处对应的Fin结构起到相应的保护作用，而其他结构如位于B区的第二浅沟槽隔离结构13B’并不会由于掺杂碳或锗后其绝缘性能受到影响。
步骤S106:在该半导体突起的两侧形成补充氧化层，以延展该第二器件氧化层。
其中，步骤106完成后的结构示意图如图4N所示。
具体的，可直接热氧化工艺对该半导体突起10B进行氧化，以在半导体突起10B的两侧形成补充氧化层，对应的补充氧化层与如图4M中示出的位于半导体突起10B顶部的部分第二器件氧化层11B’构成从顶部以及两侧面1011B呈三面包围鳍结构的延展的第二器件氧化层11B。该延展的第二器件氧化层11B用于FinFET结构的栅极氧化层。
请参阅图3，图3是本发明实施例提供的又一种半导体器件的制作方法流程图，在步骤S106之后，还包括：
步骤S107:在该第一器件氧化层上形成第一栅极层。
步骤S108:在延展的该第二器件氧化层上形成第二栅极层。
步骤108完成后的结构示意图如图4O所示，在图4O中，该第一栅极层16A经过图案化刻蚀后以形成平面型晶体管的栅极，该第二栅极层16B用作FinFET的栅极，第二栅极层16B可从三面包围着沟道，增大了栅极对沟道的控制面积，使得栅控能力大大增强，从而可以有效抑制短沟道效应，减小亚阈值泄露电流。当第一栅极层16A和第二栅极层16B都为金属时，通过低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition)在不同区域上形成。在本实施例中，由于低压器件区还包括第一低压区b 1和第二低压区b 2，为了更好地示出第一低压区b 1和第二低压区b 2上形成的器件结构，请参阅图4P，第一低压区和第二电压区之间形成有相互独立的FinFET，且第一低压区b 1和第二低压区b 2的器件氧化层厚度可以相同或者不同，具有可根据不同低压区对于击穿电压的要求来进行设定。第一低压区和第二低压区中器件的形成方法与一个低压器件区中的器件形成方法类似，第一低压区的器件和第二低压区中器件可以是同时形成，也可以是分开形成。
在本发明提供的半导体器件的制作方法中，通过分别在第一区域和第二区域形成第一浅沟槽隔离结构和第二浅沟槽隔离结构，之后再对相邻两个第二浅沟槽隔离结构进行刻蚀得到半导体突起，从而在半导体器件上形成满足不同区域结构要求的浅沟槽隔离结构，还有利于根据该半导体突起在半导体器件上形成FinFET，减缓短沟道效应。
请参阅图4A～4P，本发明还提供一种半导体器件，该半导体器件可按上述制作方法形成，该半导体器件可具体用于存储装置中的外围电路，进一步的， 该存储装置可以是NAND芯片。该半导体器件，包括衬底10、第一浅沟槽隔离结构13A、沟槽隔离结构13B’、半导体突起10B、第一器件氧化层11A、第二器件氧化层11B、第一栅极层16A以及第二栅极层16B。
具体的，如图A所示，该衬底10的材料可以为硅、锗或绝缘体上硅(Silicon-On-Insulator，SOI)等半导体材料。在本实施例中，该衬底10可以包括第一区域(A区)和第二区域(B区)，其中，A区包含高压器件区,该A区可用于形成本发明实施例中的平面型晶体管；B区包含低压器件区(低压器件区中的器件的工作电压小于高压器件区的器件的工作电压)，进一步的，低压器件区还可以包括第一低压区b1和第二低压区b2，其中，高压器件区、第一低压区以及第二低压区的器件(例如晶体管或CMOS管)的工作电压的大小关系可以是依次递减，在本实施例中，为了精简示图，在图4A后的附图中，用B区对b1及b2进行概括示意；具体的可以B区可以为一个低压器件区，也可以同时包含b1和b2，图4B-4O是以B区包含一个低压器件区为例进行说明。该B区用于形成本发明实施例中的鳍式晶体管(FinFET)，在FinFET中，栅极可从三面包围着沟道，增大了栅极对沟道的控制面积，使得栅控能力大大增强，从而可以有效抑制短沟道效应，减小亚阈值泄露电流。不同器件区的性能可以通过改变在器件内部的一个或多个晶体管的沟道宽度来调整，而FinFET的沟道宽度与鳍结构的高度成正比，由于高压器件区需要较高的驱动电压，因此对应的FinFET的“Fin”(鳍结构)的高度也较高，很难在较高的Fin上形成三面包围的栅极结构，故A区仍采用平面型晶体管。
其中，如图4B所示，该衬底10上还形成有位于该第一区域的第一器件氧化层11A与位于该第二区域的第二器件氧化层11B，该第一器件氧化层11A在第一方向(图中的y方向)上的厚度H 1大于该第二器件氧化层11B在该第一方向上的厚度H 2。
具体地，在本实施例中第一器件氧化层11A和第二器件氧化层11B的形成工艺包括热氧化工艺(ThermalOxidation)、轻等离子体氧化工艺(SoftPlasmaOxidation)或者紫外辅助氧化工艺(UVPhotoAssistantOxidation)，且在本实例中选择衬底10为硅衬底时，可选择在形成第一器件氧化层11A的同时，形成第二器件氧化层11B，此时第一器件氧化层11A和第二器件氧化层11B的成 分均为氧化硅。该第一器件氧化层11A和第二器件氧化层11B分别用作高压器件和低压器件的栅氧化层，由于低压器件和高压器件对于击穿电压的要求不同，为了避免在高压器件区出现过大的漏电流，该第一器件氧化层11A在第一方向上(图中的y方向)，也即在该衬底10的厚度方向上的厚度H 1大于该第二器件氧化层11B在该第一方向上的厚度H 2，为了实现对应的厚度关系，该第一器件氧化层11A和第二器件氧化层11B可在分步或者同步形成。当采用同步形成时，可预先在A区掺杂氯离子，由于A区掺杂了氯离子，A区中衬底10被氧化的速度加快，因此，在相同时间内，形成的该第一器件氧化层11A比第二器件氧化层11B更厚。当采用分步形成时，第一步：在相同时间和工艺条件下，在第一区域和第二区域形成相同厚度的器件氧化层；第二步，选择性刻蚀第二区域的器件氧化层，使得位于第二区域的第二器件氧化层的厚度小于位于第一区域的第一器件氧化层厚度。在本实施例中，如图4O所示，该第二器件氧化层11B从所该半导体突起10B的两侧以及顶部包围该半导体突起10B，也即该第二器件氧化层11B从三面包覆FinFET结构的鳍结构，该第二器件氧化层11B用于FinFET结构的栅极氧化层。
该第一浅沟槽隔离结构13A和第二浅沟槽隔离结构13B’分别位于该第一区域和第二区域。由于该第一浅沟槽隔离结构13A和第二浅沟槽隔离结构13B可以为等高，当对该第二浅沟槽隔离结构13B进行刻蚀后，得到的沟槽隔离结构13B’的高度小于该第一浅沟槽隔离结构13A的高度,更进一步的，在本实施例中，选择将第二浅沟槽隔离结构13B刻蚀至低出该衬底10，因此，该第一浅沟槽隔离结构13A高出该衬底10，且该衬底10高出刻蚀后该第二浅沟槽隔离结构13B’，使得该衬底10凸出于相邻的两个第二浅沟槽隔离结构13B’的部分作为B区中FinFET的“Fin”,也即B区中的半导体突起10B作为FinFET中的鳍结构。
如图4O所示，其中，该半导体器件还包括位于该第一器件氧化层11A上的第一栅极层16A以及位于该第二器件氧化层12A上的第二栅极层16B。
在图4O中，该第一栅极层16A经过图案化刻蚀后以形成平面型晶体管的栅极，该第二栅极层16B用作FinFET的栅极，第二栅极层16B可从三面包围着沟道，增大了栅极对沟道的控制面积，使得栅控能力大大增强，从而可以有效抑制短沟道效应，减小亚阈值泄露电流。当第一栅极层16A和第二栅极层16B都 为金属时，通过低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition)在不同区域上形成。在本实施例中，由于低压器件区还包括第一低压区b1和第二低压区b2，为了更好地示出第一低压区b1和第二低压区b2上形成的器件结构，请参阅图4P，第一低压区和第二电压区之间形成有相互独立的FinFET，且第一低压区b1和第二低压区b2的器件氧化层厚度可以相同或者不同，具有可根据不同低压区对于击穿电压的要求来进行设定。第一低压区和第二低压区中器件的形成方法与一个低压器件区中的器件形成方法类似，第一低压区的器件和第二低压区中器件可以是同时形成，也可以是分开形成。本发明的有益效果为：区别于现有技术，在本发明提供的半导体器件及其制作方法中，通过分别在第一区域和第二区域形成第一浅沟槽隔离结构和第二浅沟槽隔离结构，之后再对相邻两个第二浅沟槽隔离结构进行刻蚀得到半导体突起，从而在半导体器件上形成满足不同区域结构要求的浅沟槽隔离结构，还有利于根据该半导体突起在半导体器件上形成FinFET，减缓短沟道效应。
除上述实施例外，本发明还可以有其他实施方式。凡采用等同替换或等效替换形成的技术方案，均落在本发明要求的保护范围。
综上所述，虽然本发明已将优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种半导体器件的制作方法，其包括：
    提供衬底，所述衬底包括第一区域和第二区域；
    在所述衬底中形成位于所述第一区域的第一浅沟槽隔离结构以及位于所述第二区域的至少两个第二浅沟槽隔离结构；
    在所述衬底、所述第一浅沟槽隔离结构以及所述至少两个第二浅沟槽隔离结构上形成第二掩膜层；
    依次刻蚀位于所述第二区域的第二掩膜层以及所述至少两个第二浅沟槽隔离结构，以于相邻两个所述第二浅沟槽隔离结构之间形成半导体突起。
  2. 根据权利要求1所述的半导体器件的制作方法，其中，所述衬底上形成有第一掩膜层；所述依次刻蚀位于所述第二区域的第二掩膜层以及所述至少两个第二浅沟槽隔离结构，包括：
    在所述第二掩模层上形成第二光阻层；
    依次刻蚀位于所述第二区域的第二光阻层以及第二掩膜层，直至暴露位于所述第二区域的第一掩膜层以及至少两个第二浅沟槽隔离结构；
    去除位于所述第一区域的第二光阻层；
    以暴露的第一掩模层和位于所述第二区域的剩余第二掩膜层为掩模，刻蚀所述至少两个第二浅沟槽隔离结构。
  3. 根据权利要求2所述的半导体器件的制作方法，其中，所述在所述第二掩模层上形成第二光阻层，包括：
    在所述第二掩膜层上形成保护层；
    在所述保护层上形成所述第二光阻层。
  4. 根据权利要求2所述的半导体器件的制作方法，其中，所述衬底与所述第一掩膜层之间还形成有位于所述第一区域的第一器件氧化层和所述第二区域的第二器件氧化层；所述刻蚀至少两个所述第二浅沟槽隔离结构之后，还包括：
    去除所述第一掩模层以及所述剩余第二掩模层；
    在所述半导体突起的两侧形成补充氧化层，以延展所述第二器件氧化层。
  5. 根据权利要求4所述的半导体器件的制作方法，其中，所述第二掩膜层为氮化硅或多晶硅；当所述第二掩膜层为多晶硅时，所述去除所述第一掩模层以及所述剩余第二掩模层，包括：
    对所述半导体突起的两侧进行碳或锗掺杂；
    依次去除所述剩余第二掩膜层以及所述第一掩膜层。
  6. 根据权利要求5所述的半导体器件的制作方法，其中，所述对半导体突起的两侧进行碳掺杂，包括：
    在所述剩余第二掩膜层上形成第三掩膜层；
    以所述第三掩膜层以及位于所述第二区域的第一掩膜层为掩膜，对所述半导体突起的两侧进行碳或锗掺杂。
  7. 根据权利要求4所述的半导体器件的制作方法，其中，所述在所述半导体突起的两侧形成补充氧化层，以延展所述第二器件氧化层之后，还包括：
    在所述第一器件氧化层上形成第一栅极层；
    在延展的所述第二器件氧化层上形成第二栅极层。
  8. 根据权利要求4所述的半导体器件的制作方法，其中，所述第一器件氧化层在第一方向上的厚度大于所述第二器件氧化层在所述第一方向上的厚度。
  9. 根据权利要求1所述的半导体器件的制作方法，其中，在所述衬底中形成位于所述第一区域的第一浅沟槽隔离结构以及位于所述第二区域的至少两个第二浅沟槽隔离结构，包括：
    在所述衬底中形成隔离槽，所述隔离槽包括位于第一区域的第一子隔离槽以及位于第二区域的至少两个第二子隔离槽；
    在所述隔离槽中填充隔离材料，以分别在所述第一区域和第二区域形成所述第一浅沟槽隔离结构和所述至少两个第二浅沟槽隔离结构。
  10. 根据权利要求9所述的半导体器件的制作方法，其中，所述在所述隔离槽中填充隔离材料包括：
    在所述隔离槽中及所述第一掩膜层上沉积所述隔离材料，以填满所述隔离槽；
    平坦化所述隔离材料，以使所述隔离槽中的所述隔离材料与所述第一掩膜 层平齐。
  11. 根据权利要求2所述的半导体器件的制作方法，其中，所述第一掩模层材料为氮化硅。
  12. 根据权利要求2所述的半导体器件的制作方法，其中，所述第二掩膜层为氮化硅或多晶硅；当所述第二掩膜层为多晶硅时，所述在所述衬底、所述第一浅沟槽隔离结构以及至少两个所述第二浅沟槽隔离结构上形成第二掩膜层，包括：
    在所述第一掩膜层、所述第一浅沟槽隔离结构以及所述第二浅沟槽隔离结构上形成缓冲层；
    在所述缓冲层上形成所述第二掩膜层。
  13. 根据权利要求12所述的半导体器件的制作方法，其中，所述缓冲层的厚度范围为8nm～9nm。
  14. 根据权利要求1所述的半导体器件的制作方法，其中，所述第一区域用于形成平面型晶体管，所述第二区域用于形成鳍式晶体管。
  15. 根据权利要求1所述的半导体器件的制作方法，其中，所述第一浅沟槽隔离结构高出所述衬底，且所述衬底高出所述沟槽隔离结构。
  16. 一种半导体器件，其包括：
    衬底，所述衬底包括第一区域和第二区域；
    分别位于所述第一区域和所述第二区域的第一浅沟槽隔离结构和至少两个第二浅沟槽隔离结构，相邻两个所述第二浅沟槽隔离结构之间具有半导体突起；
    位于所述第一区域的第一器件氧化层，以及位于所述第二区域且包覆所述半导体突起的第二器件氧化层；
    位于所述第一器件氧化层上的第一栅极层，以及位于所述第二器件氧化层上的第二栅极层。
  17. 根据权利要求16所述的半导体器件，其中，所述第一区域用于形成平面型晶体管，所述第二区域用于形成鳍式晶体管。
  18. 根据权利要求16所述的半导体器件，其中，所述第一浅沟槽隔离结构高出所述衬底，且所述衬底高出所述第二浅沟槽隔离结构。
  19. 根据权利要求16所述的半导体器件，其中，所述第一器件氧化层在第一方向上的厚度大于所述第二器件氧化层在所述第一方向上的厚度。
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