WO2021210293A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2021210293A1
WO2021210293A1 PCT/JP2021/008891 JP2021008891W WO2021210293A1 WO 2021210293 A1 WO2021210293 A1 WO 2021210293A1 JP 2021008891 W JP2021008891 W JP 2021008891W WO 2021210293 A1 WO2021210293 A1 WO 2021210293A1
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Prior art keywords
trench
contact
region
contact layer
semiconductor device
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English (en)
French (fr)
Japanese (ja)
Inventor
原田　祐一
晴司 野口
典宏 小宮山
伊倉　巧裕
洋輔 桜井
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to CN202180005621.7A priority Critical patent/CN114503280B/zh
Priority to DE112021000105.1T priority patent/DE112021000105T5/de
Priority to JP2022515241A priority patent/JP7384274B2/ja
Publication of WO2021210293A1 publication Critical patent/WO2021210293A1/ja
Priority to US17/700,534 priority patent/US12199162B2/en
Anticipated expiration legal-status Critical
Priority to JP2023191365A priority patent/JP7803330B2/ja
Priority to US19/014,248 priority patent/US20250151365A1/en
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/128—Anode regions of diodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/231—Emitter or collector electrodes for bipolar transistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/422—PN diodes having the PN junctions in mesas
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/143—VDMOS having built-in components the built-in components being PN junction diodes
    • H10D84/144—VDMOS having built-in components the built-in components being PN junction diodes in antiparallel diode configurations
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/232—Emitter electrodes for IGBTs

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2014-158013
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2013-065724
  • Patent Document 3 International Publication No. 2018/052099
  • the first conductive type drift region provided on the semiconductor substrate, the second conductive type base region provided above the drift region, and the second conductive type base region provided above the base region are provided.
  • a plurality of trench portions arranged in a predetermined arrangement direction on the front surface side of the semiconductor substrate, and two adjacent trench portions among the plurality of trench portions.
  • the trench contact portion is provided with a trench contact portion provided on the front surface side of the semiconductor substrate and a second conductive type contact layer provided below the trench contact portion and having a higher doping concentration than the base region.
  • a semiconductor device in which the lower end of the light is deeper than the lower end of the emitter region and the emitter region and the contact layer are in contact with each other on the side wall of the trench contact portion.
  • the length of contact between the lower end of the emitter region and the base region may be larger than the shortest distance between the contact layer and the adjacent trench portion of the plurality of trench portions.
  • the maximum distance from the bottom of the side wall of the trench contact portion to the contact layer may be larger than the shortest distance between the contact layer and the adjacent trench portion among the plurality of trench portions.
  • the shortest distance between the contact layer and the adjacent trench portion among the plurality of trench portions may be 0.1 ⁇ m or more.
  • the contact layer may have a stretched region extending toward the front surface side of the semiconductor substrate from the lower end of the emitter region.
  • the trench contact portion may have a substantially flat bottom surface.
  • the trench contact portion may have a concave bottom surface recessed on the back surface side of the semiconductor substrate.
  • the contact layer may have a first contact layer provided on the side wall of the trench contact portion and a second contact layer provided below the first contact layer on the side wall of the trench contact portion.
  • the shortest distance between the first contact layer and the adjacent trench portion among the plurality of trench portions may be larger than the shortest distance between the second contact layer and the adjacent trench portion among the plurality of trench portions.
  • the doping concentration of the first contact layer may be lower than the doping concentration of the second contact layer.
  • the trench contact portion may be provided by extending in the stretching direction of a plurality of trench portions.
  • a contact layer may be provided on the side wall of the terminal portion, which is the end portion of the trench contact portion in the extending direction.
  • the side wall of the terminal portion may be covered with an emitter region and a contact layer.
  • the side wall of the terminal portion may be covered with a second conductive type region.
  • the front surface of the semiconductor substrate may be provided with a second conductive type contact region having a higher doping concentration than the base region.
  • the side wall of the termination may be covered with a contact area, a base area and a contact layer.
  • the front surface of the semiconductor substrate may be provided with a second conductive type contact region having a higher doping concentration than the base region.
  • the side wall of the termination may be covered with a contact area and a contact layer.
  • a step of providing a first conductive type drift region on the semiconductor substrate, a stage of providing a second conductive type base region above the drift region, and a step of providing a first conductive type above the base region A stage in which an emitter region of a mold is provided, a stage in which a plurality of trench portions are arranged in a predetermined arrangement direction on the front surface side of the semiconductor substrate, and two adjacent trench portions among the plurality of trench portions.
  • a step of providing a trench contact portion on the front surface side of the semiconductor substrate and a step of providing a second conductive type contact layer having a higher doping concentration than the base region below the trench contact portion are provided.
  • a method for manufacturing a semiconductor device in which the lower end of the trench contact portion is deeper than the lower end of the emitter region and the emitter region and the contact layer are in contact with each other on the side wall of the trench contact portion.
  • the method for manufacturing a semiconductor device may include a step of implanting ions to form a contact layer after a step of providing a contact hole in the trench contact portion.
  • the method for manufacturing a semiconductor device may include a step of forming an oxide film mask on the semiconductor substrate and a step of ion implantation to form a contact layer using the oxide film mask as a mask.
  • the method for manufacturing a semiconductor device may include a step of forming a first contact layer on the side wall of the trench contact portion and a step of forming a second contact layer below the first contact layer on the side wall of the trench contact portion. ..
  • the implantation width of the ion implantation for forming the first contact layer may be smaller than the implantation width of the ion implantation for forming the second contact layer.
  • the method for manufacturing a semiconductor device may include a step of forming a first contact layer on the side wall of the trench contact portion and a step of forming a second contact layer below the first contact layer on the side wall of the trench contact portion. ..
  • the doping concentration of the first contact layer may be smaller than the doping concentration of the second contact layer.
  • An example of the top view of the semiconductor device 100 according to the Example is shown. It is a figure which shows an example of the aa'cross section in FIG. 1A. It is a figure which shows an example of the bb'cross section in FIG. 1A. An example of an enlarged view of the vicinity of the trench contact portion 27 is shown. An example of the doping concentration distribution around the trench contact portion 27 is shown. An example of an enlarged cross-sectional view showing the vicinity of the end portion 28 is shown. An example of an enlarged view of the vicinity of the trench contact portion 27 is shown. An example of an enlarged cross-sectional view showing the vicinity of the end portion 28 is shown. An example of the top view of the semiconductor device 100 according to the Example is shown.
  • An example of an enlarged cross-sectional view showing the vicinity of the terminal portion 28 of FIG. 4A is shown.
  • An example of the manufacturing method of the contact layer 19 having a one-stage structure is shown.
  • An example of the manufacturing method of the contact layer 19 having a two-stage structure is shown.
  • the configuration of the semiconductor device 500 according to the comparative example is shown.
  • one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as “upper” and the other side is referred to as “lower”.
  • the upper surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the directions of "top”, “bottom”, “front”, and “back” are not limited to the direction of gravity or the direction of mounting on a substrate or the like when mounting a semiconductor device.
  • the first conductive type is N type and the second conductive type is P type, but the first conductive type may be P type and the second conductive type may be N type.
  • the conductive types such as the substrate, the layer, and the region in each embodiment have opposite polarities.
  • n and p mean that electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively.
  • + and-attached to n and p mean that the doping concentration is higher and the doping concentration is lower than that of the layer or region to which it is not attached, respectively, and ++ is a higher doping concentration than +, ⁇ Means a lower doping concentration than-.
  • the doping concentration refers to the concentration of a donor or acceptorized dopant.
  • the unit is / cm 3.
  • the concentration difference between the donor and the acceptor (that is, the net doping concentration) may be referred to as the doping concentration.
  • the doping concentration can be measured by the SR method.
  • the chemical concentration of the donor and the acceptor may be used as the doping concentration.
  • the doping concentration can be measured by the SIMS method.
  • any of the above may be used as the doping concentration.
  • the peak value of the doping concentration distribution in the doping region may be used as the doping concentration in the doping region.
  • the dose amount means the number of ions per unit area implanted in the wafer when ion implantation is performed. Therefore, the unit is / cm 2 .
  • the dose amount in the semiconductor region can be an integral concentration obtained by integrating the doping concentration over the depth direction of the semiconductor region.
  • the unit of the integrated concentration is / cm 2 . Therefore, the dose amount and the integrated concentration may be treated as the same.
  • the integrated concentration may be an integrated value up to the full width at half maximum, and when it overlaps with the spectrum of another semiconductor region, it may be derived excluding the influence of the other semiconductor region.
  • the high and low doping concentration can be read as the high and low dose amount. That is, when the doping concentration in one region is higher than the doping concentration in the other region, it can be understood that the dose amount in the one region is higher than the dose amount in the other region.
  • FIG. 1A shows an example of a top view of the semiconductor device 100 according to the embodiment.
  • the semiconductor device 100 of this example is a semiconductor chip including a transistor unit 70 and a diode unit 80.
  • the semiconductor device 100 is a reverse conduction IGBT (RC-IGBT: Reverse Conducting IGBT).
  • the semiconductor device 100 may be an IGBT or a MOS transistor.
  • the transistor portion 70 is a region in which a collector region 22 provided on the back surface side of the semiconductor substrate 10 is projected onto the upper surface of the semiconductor substrate 10.
  • the collector region 22 has a second conductive type.
  • the collector area 22 of this example is a P + type as an example.
  • the transistor unit 70 includes a transistor such as an IGBT.
  • the transistor portion 70 includes a boundary portion 90 located at the boundary between the transistor portion 70 and the diode portion 80.
  • the diode portion 80 is a region in which the cathode region 82 provided on the back surface side of the semiconductor substrate 10 is projected onto the upper surface of the semiconductor substrate 10.
  • the cathode region 82 has a first conductive type.
  • the cathode region 82 of this example is N + type as an example.
  • the diode section 80 includes a diode such as a freewheeling diode (FWD: Free Wheel Diode) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.
  • FWD Free Wheel Diode
  • an edge termination structure portion may be provided in a region on the negative side in the Y-axis direction of the semiconductor device 100 of this example.
  • the edge termination structure relaxes the electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure has, for example, a guard ring, a field plate, a resurf, and a structure in which these are combined. In this example, for convenience, the negative edge in the Y-axis direction will be described, but the same applies to the other edges of the semiconductor device 100.
  • the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like.
  • the semiconductor substrate 10 of this example is a silicon substrate.
  • the semiconductor device 100 of this example has a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. To be equipped. The front surface 21 will be described later. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Further, the gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.
  • the emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal.
  • the emitter electrode 52 may be formed of an aluminum, aluminum-silicon alloy, or aluminum-silicon-copper alloy.
  • At least a portion of the gate metal layer 50 may be formed of aluminum, aluminum-silicon alloy, or aluminum-silicon-copper alloy.
  • the emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like in the lower layer of a region formed of aluminum or the like.
  • the emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
  • the emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film 38 interposed therebetween.
  • the interlayer insulating film 38 is omitted in FIG. 1A.
  • the interlayer insulating film 38 is provided with a contact hole 54, a contact hole 55, and a contact hole 56 penetrating.
  • the contact hole 55 connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70.
  • a plug made of tungsten or the like may be formed inside the contact hole 55.
  • the contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30.
  • a plug made of tungsten or the like may be formed inside the contact hole 56.
  • the connecting portion 25 electrically connects the front surface side electrode such as the emitter electrode 52 or the gate metal layer 50 with the semiconductor substrate 10.
  • the connecting portion 25 is provided between the gate metal layer 50 and the gate conductive portion.
  • the connecting portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion.
  • the connection portion 25 is a conductive material such as polysilicon doped with impurities.
  • the connecting portion 25 is polysilicon (N +) doped with N-type impurities.
  • the connecting portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.
  • the gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example).
  • the gate trench portion 40 of this example includes two stretched portions 41 that are parallel to the front surface 21 of the semiconductor substrate 10 and stretched along a stretch direction (Y-axis direction in this example) perpendicular to the arrangement direction. It may have a connecting portion 43 connecting the two stretched portions 41.
  • the connecting portion 43 is formed in a curved shape.
  • the dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Similar to the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example). Like the gate trench portion 40, the dummy trench portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two stretching portions 31 that stretch along the stretching direction and a connecting portion 33 that connects the two stretching portions 31.
  • the transistor portion 70 of this example has a structure in which two gate trench portions 40 and three dummy trench portions 30 are repeatedly arranged. That is, the transistor portion 70 of this example has a gate trench portion 40 and a dummy trench portion 30 at a ratio of 2: 3. For example, the transistor portion 70 has one stretched portion 31 between the two stretched portions 41. Further, the transistor portion 70 has two extending portions 31 adjacent to the gate trench portion 40.
  • the ratio of the gate trench portion 40 and the dummy trench portion 30 is not limited to this example.
  • the ratio of the gate trench portion 40 to the dummy trench portion 30 may be 1: 1 or 2: 4.
  • the transistor portion 70 may have a so-called full gate structure in which the dummy trench portion 30 is not provided and all the gate trench portions 40 are used.
  • the well region 17 is a second conductive type region provided on the front surface 21 side of the semiconductor substrate 10 with respect to the drift region 18 described later.
  • the well region 17 is an example of a well region provided on the edge side of the semiconductor device 100.
  • the well region 17 is P + type as an example.
  • the well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided.
  • the diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • a part of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17.
  • the bottom of the extending end of the gate trench 40 and the dummy trench 30 may be covered by the well region 17.
  • the contact hole 54 is formed in the transistor portion 70 above each region of the emitter region 12 and the contact region 15. Further, the contact hole 54 is provided above the base region 14 in the diode portion 80. The contact hole 54 is provided above the contact area 15 at the boundary 90. The contact hole 54 is provided above the base region 14 in the diode portion 80. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction. As described above, one or a plurality of contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided by being stretched in the stretching direction.
  • the trench contact portion 27 electrically connects the emitter electrode 52 and the semiconductor substrate 10.
  • the trench contact portion 27 is provided in the contact hole 54.
  • the trench contact portion 27 is provided so as to be stretched in the stretching direction.
  • the end portion 28 is the end portion of the trench contact portion 27 in the stretching direction.
  • the terminal portion 28 is provided in the mesa portion 71 in a region where the contact region 15 is formed on the front surface 21.
  • the end portion 28 may be provided in the mesa portion 81 or the mesa portion 91 in a region where the contact region 15 is formed on the front surface 21.
  • the boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80.
  • the boundary 90 has a contact area 15.
  • the boundary portion 90 of this example does not have an emitter region 12.
  • the trench portion of the boundary portion 90 is a dummy trench portion 30.
  • the boundary portion 90 of this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.
  • the mesa portion 71, the mesa portion 91, and the mesa portion 81 are the mesa portions provided adjacent to the trench portion in the plane parallel to the front surface 21 of the semiconductor substrate 10.
  • the mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and is a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. good.
  • the extended portion of each trench portion may be used as one trench portion. That is, the region sandwiched between the two stretched portions may be the mesa portion.
  • the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70.
  • the mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10.
  • the emitter region 12 and the contact region 15 are alternately provided in the stretching direction.
  • the mesa portion 91 is provided at the boundary portion 90.
  • the mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10.
  • the mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.
  • the mesa portion 81 is provided in the diode portion 80 in a region sandwiched between adjacent dummy trench portions 30.
  • the mesa portion 81 has a contact region 15 on the front surface 21 of the semiconductor substrate 10.
  • the mesa portion 81 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.
  • the base region 14 is a second conductive type region provided on the front surface 21 side of the semiconductor substrate 10 in the transistor portion 70 and the diode portion 80.
  • the base region 14 is P-type as an example.
  • the base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 and the mesa portion 91 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.
  • the emitter region 12 is a first conductive type region having a higher doping concentration than the drift region 18.
  • the emitter region 12 of this example is N + type as an example.
  • An example of a dopant in the emitter region 12 is arsenic (As).
  • the emitter region 12 is provided in contact with the gate trench portion 40 on the front surface 21 of the mesa portion 71.
  • the emitter region 12 may be provided so as to extend in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other.
  • the emitter region 12 is also provided below the contact hole 54.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 of this example is in contact with the dummy trench portion 30.
  • the emitter region 12 does not have to be provided in the mesa portion 81 and the mesa portion 91.
  • the contact region 15 is a second conductive type region having a higher doping concentration than the base region 14.
  • the contact region 15 of this example is a P + type as an example.
  • the contact region 15 of this example is provided on the front surface 21 of the mesa portion 71, the mesa portion 81, and the mesa portion 91.
  • the contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71, the mesa portion 81, or the mesa portion 91 to the other.
  • the contact region 15 may or may not be in contact with the gate trench portion 40. Further, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40.
  • the contact area 15 is also provided below the contact hole 54.
  • FIG. 1B is a diagram showing an example of a'a'cross section in FIG. 1A.
  • the aa'cross section is an XZ plane that passes through the emitter region 12 in the transistor portion 70.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the aa'cross section.
  • the emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.
  • the drift region 18 is a first conductive type region provided on the semiconductor substrate 10.
  • the drift region 18 of this example is N-type as an example.
  • the drift region 18 may be a region remaining in the semiconductor substrate 10 without forming another doping region. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.
  • the buffer region 20 is a first conductive type region provided below the drift region 18.
  • the buffer area 20 of this example is N-type as an example.
  • the doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18.
  • the buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the second conductive type collector region 22 and the first conductive type cathode region 82.
  • the collector area 22 is provided below the buffer area 20 in the transistor unit 70.
  • the cathode region 82 is provided below the buffer region 20 in the diode portion 80.
  • the boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80.
  • the collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10.
  • the collector electrode 24 is made of a conductive material such as metal.
  • the base region 14 is a second conductive type region provided above the drift region 18 in the mesa portion 71, the mesa portion 91, and the mesa portion 81.
  • the base region 14 is provided in contact with the gate trench portion 40.
  • the base region 14 may be provided in contact with the dummy trench portion 30.
  • the emitter region 12 is provided between the base region 14 and the front surface 21.
  • the emitter region 12 of this example is provided in the mesa portion 71, and is not provided in the mesa portion 81 and the mesa portion 91.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the contact region 15 is provided above the base region 14 in the mesa portion 81 and the mesa portion 91.
  • the contact region 15 is provided in the mesa portion 81 and the mesa portion 91 in contact with the dummy trench portion 30.
  • the contact region 15 may be provided on the front surface 21 of the mesa portion 71.
  • the trench contact portion 27 has a conductive material filled in the contact hole 54.
  • the trench contact portion 27 is provided between two adjacent trench portions among the plurality of trench portions.
  • the trench contact portion 27 is provided in contact with the contact layer 19 on the front surface 21 side.
  • the trench contact portion 27 of this example is provided so as to penetrate the emitter region 12 from the front surface 21.
  • the trench contact portion 27 may have the same material as the emitter electrode 52.
  • the lower end of the trench contact portion 27 is deeper than the lower end of the emitter region 12.
  • the trench contact portion 27 has a substantially flat bottom surface.
  • the bottom surface of the trench contact portion 27 is covered with the contact layer 19.
  • the trench contact portion 27 of this example has a tapered shape with an inclined side wall.
  • the side wall of the trench contact portion 27 may be provided substantially perpendicular to the front surface 21.
  • the contact layer 19 is provided below the trench contact portion 27.
  • the contact layer 19 is a second conductive type region having a higher doping concentration than the base region 14.
  • the contact layer 19 of this example is of P + type as an example.
  • the contact layer 19 is formed by ion implantation of boron (B) or boron fluoride (BF 2).
  • the contact layer 19 may have the same doping concentration as the contact region 15.
  • the contact layer 19 suppresses latch-up by pulling out a small number of carriers.
  • the contact layer 19 is provided on the side wall and the bottom surface of the trench contact portion 27.
  • the contact layer 19 of this example is provided in each of the mesa portion 71, the mesa portion 81, and the mesa portion 91.
  • the contact layer 19 may be provided so as to extend in the Y-axis direction.
  • the emitter region 12 and the contact layer 19 are in contact with each other on the side wall of the trench contact portion 27.
  • the side wall of the trench contact portion 27 of this example is covered with the emitter region 12 and the contact layer 19. That is, the trench contact portion 27 is not in contact with the base region 14.
  • the contact layer 19 can improve the extraction efficiency of a small number of carriers and stabilize the potential of the base region 14.
  • the storage region 16 is a first conductive type region provided on the front surface 21 side of the semiconductor substrate 10 with respect to the drift region 18.
  • the storage area 16 of this example is N + type as an example.
  • the storage region 16 is provided in the transistor portion 70 and the diode portion 80. However, the storage area 16 may not be provided.
  • the storage area 16 is provided in contact with the gate trench portion 40.
  • the storage region 16 may or may not be in contact with the dummy trench portion 30.
  • the doping concentration in the accumulation region 16 is higher than the doping concentration in the drift region 18.
  • the dose amount of ion implantation in the accumulation region 16 may be 1E12 cm -2 or more and 1E 13 cm -2 or less. Further, the ion implantation dose amount of the accumulation region 16 may be 3E12 cm-2 or more and 6E12 cm- 2 or less.
  • the carrier injection promoting effect IE effect
  • E is meant a power of 10, for example, 1E12 cm -2 refers to 1 ⁇ 10 12 cm -2.
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21.
  • Each trench portion is provided from the front surface 21 to the drift region 18.
  • each trench portion also penetrates these regions and reaches the drift region 18.
  • the penetration of the trench portion through the doping region is not limited to those manufactured in the order of forming the doping region and then forming the trench portion. Those in which a doping region is formed between the trench portions after the trench portion is formed are also included in those in which the trench portion penetrates the doping region.
  • the gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21.
  • the gate insulating film 42 is formed so as to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is formed inside the gate trench inside the gate insulating film 42.
  • the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21.
  • the gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side with the gate insulating film 42 interposed therebetween in the depth direction of the semiconductor substrate 10.
  • a predetermined voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed on the surface layer of the interface in the base region 14 in contact with the gate trench.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40.
  • the dummy trench portion 30 has a dummy trench formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34.
  • the dummy insulating film 32 is formed so as to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is formed inside the dummy trench and inside the dummy insulating film 32.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10.
  • the dummy trench portion 30 is covered with an interlayer insulating film 38 on the front surface 21.
  • the interlayer insulating film 38 is provided on the front surface 21.
  • An emitter electrode 52 is provided above the interlayer insulating film 38.
  • the interlayer insulating film 38 is provided with one or a plurality of contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, the contact hole 55 and the contact hole 56 may be provided so as to penetrate the interlayer insulating film 38.
  • FIG. 1C is a diagram showing an example of a bb'cross section in FIG. 1A.
  • the bb'cross section is an XZ plane that passes through the contact region 15 in the transistor portion 70.
  • the mesa portion 71 has a base region 14, a contact region 15, an accumulation region 16, and a contact layer 19 in a bb'cross section.
  • the mesa portion 91 has a contact region 15, an accumulation region 16, and a contact layer 19 as in the case of the aa'cross section.
  • the mesa portion 71 has the same structure as the mesa portion 91.
  • the mesa portion 81 has a base region 14, a contact region 15, an accumulation region 16, and a contact layer 19 as in the case of the aa'cross section.
  • FIG. 1D shows an example of an enlarged view of the vicinity of the trench contact portion 27.
  • the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40 will be described, but the mesa portion 81 or the mesa portion 91 may have the same structure.
  • Mesa width W M is the X-axis direction of the width of the mesa.
  • Mesa portion 71, the mesa section 81 and the mesa portion 91 may have the same mesa width W M.
  • Mesa width W M of the present embodiment 0.8 or more and 1.5 ⁇ m or less.
  • the length A is the length at which the lower end of the emitter region 12 and the base region 14 are in contact with each other in the arrangement direction.
  • the length A is greater than 0.1 ⁇ m and less than 0.3 ⁇ m.
  • the length B is the shortest distance between the contact layer 19 and the adjacent trench portion among the plurality of trench portions.
  • the contact layer 19 is provided apart from the adjacent trench portion in order to form a channel.
  • the length B is 0.1 ⁇ m or more.
  • Length A is larger than length B. That is, the width of the base region 14 through which the minority carriers pass is smaller than the width of the lower surface of the emitter region 12. This facilitates pulling out the minority carriers in the contact layer 19 before the minority carriers move to the vicinity of the emitter region 12.
  • the stretched region E is a region of the contact layer 19 that is stretched toward the front surface 21 side of the lower end of the emitter region 12.
  • the length C is the difference between the upper end depth of the contact layer 19 and the lower end depth of the emitter region 12. That is, the length C refers to the amount of stretching of the stretching region E to the emitter region 12. The larger the length C, the more the contact layer 19 extends to the emitter region 12.
  • the length D is the maximum distance from the side wall bottom 29 of the trench contact portion 27 to the contact layer 19 in the arrangement direction.
  • the length D of this example is larger than the length B. That is, the contact layer 19 extends closer to the trench portion than the side wall bottom portion 29 of the trench contact portion 27. This makes it easier to guide the minority carriers to the contact layer 19, and it is possible to suppress the amount of minority carriers passing between the contact layer 19 and the trench portion toward the emitter region 12.
  • the trench contact portion 27 has a concave bottom surface recessed on the back surface 23 side.
  • the concave bottom surface of the trench contact portion 27 of this example is recessed from the side wall bottom portion 29 toward the center of the trench contact portion 27.
  • the bottom surface of the trench contact portion 27 may be recessed in an arc.
  • the concave bottom surface of the trench contact portion 27 is formed by etching for forming the contact hole 54 of the trench contact portion 27.
  • the length L1 is the difference between the lower end of the emitter region 12 and the bottom surface of the trench contact portion 27.
  • the contact layer 19 since the contact layer 19 is in contact with the emitter region 12, carrier injection from the emitter region 12 can be suppressed even when the length L1 becomes large.
  • the length L2 is the distance from the front surface 21 to the upper end of the dummy conductive portion 34 or the upper end of the gate conductive portion 44.
  • the length L2 may be the distance from the front surface 21 to the uppermost end of the dummy conductive portion 34 or the gate conductive portion 44.
  • the length L2 is 0.1 ⁇ m or more and 0.4 ⁇ m or less.
  • the depth D12 is the depth from the front surface 21 to the lower end of the emitter region 12.
  • the depth D12 is 0.3 ⁇ m or more and 0.7 ⁇ m or less.
  • the depth D12 may be greater than the length L2. That is, the emitter region 12 is provided so as to extend from the front surface 21 to a depth facing the dummy conductive portion 34 or the gate conductive portion 44.
  • the depth D27 is the depth from the front surface 21 to the bottom surface of the trench contact portion 27.
  • the depth D27 of this example is the depth from the front surface 21 to the lower end of the side wall of the trench contact portion 27.
  • the depth D27 is larger than the depth D12.
  • the depth D27 is 0.5 ⁇ m or more and 1.0 ⁇ m or less.
  • FIG. 1E shows an example of the doping concentration distribution around the trench contact portion 27.
  • the vertical axis represents the doping concentration (cm -2 ), and the horizontal axis represents the distance ( ⁇ m) from the upper end of the contact layer 19 in the depth direction.
  • the solid line shows the doping concentration distribution at the ZZ'position.
  • the broken line indicates the doping concentration of the emitter region 12 having the same depth as the solid line.
  • the contact layer 19 is formed by ion implantation through the trench contact portion 27.
  • the contact layer 19 has one peak, but may have a plurality of peaks.
  • the peak position of the contact layer 19 may be formed at a position deeper than the lower end of the emitter region 12.
  • the peak of the contact layer 19 in this example is approximately 1E20 cm -2 .
  • the distribution of the doping concentration in this example is just an example. In order to realize the semiconductor device 100 disclosed in the present specification, the magnitude and depth of the peak of the doping concentration may be appropriately changed.
  • FIG. 1F shows an example of an enlarged cross-sectional view in the vicinity of the terminal portion 28.
  • the figure shows an XZ plane passing through the end 28.
  • the side wall of the end portion 28 of the trench contact portion 27 is covered with a second conductive type region.
  • the side wall of the end portion 28 of the trench contact portion 27 of this example is covered with the contact region 15 and the contact layer 19.
  • the contact layer 19 may be provided in contact with the emitter region 12 or may be provided in contact with the contact region 15.
  • the length A' is the length at which the lower end of the contact region 15 and the base region 14 are in contact with each other in the arrangement direction.
  • the length A is greater than 0.1 ⁇ m and less than 0.3 ⁇ m.
  • the depth D15 is the depth from the front surface 21 to the lower end of the contact area 15.
  • the depth D15 is 0.3 ⁇ m or more and 0.7 ⁇ m or less.
  • the depth D15 may be larger than the length L2. Further, the depth D15 may be the same as or different from the depth D12 of the emitter region 12.
  • FIG. 2 shows an example of an enlarged view of the vicinity of the trench contact portion 27.
  • the contact layer 19 of this example includes a two-stage contact layer of the contact layer 19a and the contact layer 19b.
  • the contact layer 19a is an example of the first contact layer
  • the contact layer 19b is an example of the second contact layer.
  • the contact layer 19a is provided on the side wall of the trench contact portion 27.
  • the contact layer 19a is provided in contact with the emitter region 12.
  • the contact layer 19a has a stretched region E extending from the lower end of the emitter region 12 to the front surface 21. Even when the trench contact portion 27 is provided so as to project from the emitter region 12 toward the back surface 23 side, the contact layer 19a comes into contact with the emitter region 12. Therefore, the extraction efficiency of a small number of carriers can be improved and latch-up can be suppressed.
  • the contact layer 19b is provided below the contact layer 19a on the side wall of the trench contact portion 27.
  • the contact layer 19b is provided in contact with the contact layer 19a on the side wall of the trench contact portion 27. That is, the side wall of the trench contact portion 27 is covered with the emitter region 12, the contact layer 19a, and the contact layer 19b.
  • the doping concentration of the contact layer 19a may be the same as the doping concentration of the contact layer 19b. Further, the doping concentration of the contact layer 19a and the contact layer 19b may be the same as the doping concentration of the contact region 15. Further, the doping concentration of the contact layer 19a may be lower than the doping concentration of the contact layer 19b.
  • the length B1 is the shortest distance between the contact layer 19a and the adjacent trench portion among the plurality of trench portions.
  • the length B2 is the shortest distance between the contact layer 19b and the adjacent trench portion among the plurality of trench portions.
  • the length B1 is larger than the length B2.
  • FIG. 3 shows an example of an enlarged cross-sectional view in the vicinity of the terminal portion 28.
  • the figure shows an XZ plane passing through the end 28.
  • the differences from the cross-sectional view of FIG. 1D will be particularly described.
  • the side wall of the terminal portion 28 is covered with a second conductive type region.
  • a contact layer 19 is provided on the side wall of the terminal portion 28 of this example.
  • the side wall of the end 28 is covered with a base region 14, a contact region 15 and a contact layer 19. In this way, when the contact region 15 is provided on the front surface 21, the contact layer 19 may be provided at a distance from the contact region 15.
  • FIG. 4A shows an example of a top view of the semiconductor device 100 according to the embodiment.
  • the semiconductor device 100 of this example differs from the top view of FIG. 1A in that the end portion 28 of the front surface 21 is provided in the emitter region 12.
  • the differences from the cross-sectional view of FIG. 1A will be particularly described.
  • the base region 14 is provided adjacent to the emitter region 12 in the mesa portion 71.
  • the emitter region 12 and the contact region 15 are alternately provided on the front surface 21 in the Y-axis direction.
  • the end portion 28 of this example is provided in the region where the emitter region 12 is formed.
  • FIG. 4B shows an example of an enlarged cross-sectional view of the vicinity of the terminal portion 28 of FIG. 4A.
  • the figure shows an XZ plane passing through the end 28.
  • the semiconductor device 100 of this example differs from the cross-sectional view of FIG. 1F in that the emitter region 12 is provided on the front surface 21 of the terminal portion 28. In this example, the differences from the cross-sectional view of FIG. 1F will be particularly described.
  • the side wall of the terminal portion 28 of the trench contact portion 27 is covered with the emitter region 12 and the contact layer 19. As shown in FIG. 1D, the contact layer 19 is provided in contact with the emitter region 12.
  • FIG. 5 shows an example of a method for manufacturing the one-stage contact layer 19.
  • step S100 the emitter region 12 and the base region 14 are formed on the semiconductor substrate 10.
  • An interlayer insulating film 38 is formed on the upper surface of the emitter region 12 of the front surface 21.
  • step S102 the contact hole 54 is formed by penetrating the emitter region 12 and etching to the base region 14.
  • an oxide film mask is formed above the semiconductor substrate 10.
  • step S104 ions are implanted to form the contact layer 19 using the interlayer insulating film 38 as a mask.
  • the dashed line indicates the region in which the dopant of the contact layer 19 is injected.
  • the contact layer 19 is formed by heat treatment.
  • the contact layer 19 may be provided by being stretched to the emitter region 12 by heat treatment. As a result, the emitter region 12 and the contact layer 19 come into contact with each other on the side wall of the trench contact portion 27.
  • ions are implanted to form the contact layer 19. That is, since the dopant of the contact layer 19 is ion-implanted using the interlayer insulating film 38 as a mask, the alignment accuracy of the contact layer 19 with respect to the trench contact portion 27 is improved.
  • FIG. 6 shows an example of a method for manufacturing the contact layer 19 having a two-stage structure.
  • step S200 a dopant for forming the contact layer 19a is injected.
  • the broken line indicates the region where the dopant of the contact layer 19a is injected.
  • step S202 the contact layer 19a is activated by heat treatment.
  • the heat treatment for activating the contact layer 19a is omitted, and the heat treatment may be performed together with the contact layer 19b.
  • step S204 the contact hole 54 is formed by penetrating the emitter region 12 and etching to the base region 14. A part of the contact layer 19a remains on the side wall of the contact hole 54.
  • step S206 a dopant for forming the contact layer 19b is ion-implanted and heat-treated.
  • the contact layer 19b is formed below the contact layer 19a.
  • the dashed line indicates the region where the dopant of the contact layer 19b is injected.
  • the implantation width of the ion implantation for forming the contact layer 19a may be smaller than the implantation width of the ion implantation for forming the contact layer 19b. Further, the doping concentration of the contact layer 19a may be smaller than the doping concentration of the contact layer 19b. As a result, the contact layer 19b can be formed in a wider range than the contact layer 19a.
  • FIG. 7 shows the configuration of the semiconductor device 500 according to the comparative example.
  • a cross-sectional view corresponding to the aa'cross section of FIG. 1A is shown.
  • the contact layer 519 is separated from the emitter region 512 on the side wall of the trench contact portion 527. Therefore, in the semiconductor device 500, it is difficult to suppress the injection of carriers from the emitter region 512.
  • the contact layer 19 is in contact with the emitter region 12, the injection of carriers from the emitter region 12 can be suppressed and the fracture resistance can be improved.
  • gate conductive part 50. ⁇ ⁇ Gate metal layer, 52 ⁇ ⁇ ⁇ Emitter electrode, 54 ⁇ ⁇ ⁇ Contact hole, 55 ⁇ ⁇ ⁇ Contact hole, 56 ⁇ ⁇ ⁇ Contact hole, 70 ⁇ ⁇ ⁇ Transistor part, 71 ⁇ ⁇ ⁇ Mesa part, 80 ⁇ ⁇ Diode part, 81 ⁇ ⁇ ⁇ Mesa part, 82 ⁇ ⁇ ⁇ Cathode region, 90 ⁇ ⁇ ⁇ Boundary part, 91 ⁇ ⁇ ⁇ Mesa part, 100 ⁇ ⁇ ⁇ Semiconductor device, 500 ⁇ ⁇ ⁇ Semiconductor device, 512 ⁇ ⁇ Emitter region, 519 ⁇ ⁇ ⁇ Contact layer, 527 ⁇ ⁇ ⁇ Trench contact part

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