JP7384274B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Description
特許文献1 特開2014-158013号公報
特許文献2 特開2013-065724号公報
特許文献3 国際公開第2018/052099号公報
Claims (25)
- 半導体基板に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の上方に設けられた第2導電型のベース領域と、
前記ベース領域の上方に設けられた第1導電型のエミッタ領域と、
前記半導体基板のおもて面側において、予め定められた配列方向に配列された複数のトレンチ部と、
前記複数のトレンチ部のうち隣接する2つのトレンチ部の間において、前記半導体基板のおもて面側に設けられたトレンチコンタクト部と、
前記トレンチコンタクト部の下方に設けられ、前記ベース領域よりも高ドーピング濃度である第2導電型のコンタクト層と
を備え、
前記トレンチコンタクト部の下端が前記エミッタ領域の下端よりも深く、
前記トレンチコンタクト部の側壁において、前記半導体基板のおもて面に前記エミッタ領域が露出しており、
前記トレンチコンタクト部の側壁において、前記エミッタ領域と前記コンタクト層とが接触しており、
前記配列方向において、前記トレンチコンタクト部の側壁底部から前記コンタクト層の外周面までの最大距離は、前記コンタクト層と前記複数のトレンチ部のうち隣接するトレンチ部との最短距離よりも大きい
半導体装置。 - 半導体基板に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の上方に設けられた第2導電型のベース領域と、
前記ベース領域の上方に設けられた第1導電型のエミッタ領域と、
前記半導体基板のおもて面側において、予め定められた配列方向に配列された複数のトレンチ部と、
前記複数のトレンチ部のうち隣接する2つのトレンチ部の間において、前記半導体基板のおもて面側に設けられたトレンチコンタクト部と、
前記トレンチコンタクト部の下方に設けられ、前記ベース領域よりも高ドーピング濃度である第2導電型のコンタクト層と
を備え、
前記トレンチコンタクト部の下端が前記エミッタ領域の下端よりも深く、
前記トレンチコンタクト部の側壁において、前記半導体基板のおもて面に前記エミッタ領域が露出しており、
前記トレンチコンタクト部の側壁において、前記エミッタ領域と前記コンタクト層とが接触しており、
前記トレンチコンタクト部は、前記複数のトレンチ部の延伸方向に延伸して設けられ、
前記トレンチコンタクト部の前記延伸方向における端部である終端部の側壁には、前記コンタクト層が設けられており、
前記終端部の側壁は、第2導電型の領域で覆われており、
前記半導体基板のおもて面において、前記ベース領域よりも高ドーピング濃度である第2導電型のコンタクト領域を備え、
前記終端部の側壁は、前記コンタクト領域、前記ベース領域および前記コンタクト層で覆われている
半導体装置。 - 半導体基板に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の上方に設けられた第2導電型のベース領域と、
前記ベース領域の上方に設けられた第1導電型のエミッタ領域と、
前記半導体基板のおもて面側において、予め定められた配列方向に配列された複数のトレンチ部と、
前記複数のトレンチ部のうち隣接する2つのトレンチ部の間において、前記半導体基板のおもて面側に設けられたトレンチコンタクト部と、
前記トレンチコンタクト部の下方に設けられ、前記ベース領域よりも高ドーピング濃度である第2導電型のコンタクト層と
を備え、
前記トレンチコンタクト部の下端が前記エミッタ領域の下端よりも深く、
前記トレンチコンタクト部の側壁において、前記半導体基板のおもて面に前記エミッタ領域が露出しており、
前記トレンチコンタクト部の側壁において、前記エミッタ領域と前記コンタクト層とが接触しており、
前記コンタクト層は、
前記トレンチコンタクト部の側壁に接し、底面と離間するように設けられた第1コンタクト層と、
前記第1コンタクト層の下方において、前記トレンチコンタクト部の前記側壁および前記底面に接するように設けられた第2コンタクト層と
を有する半導体装置。 - 前記エミッタ領域は、前記第1コンタクト層と接触している
請求項3に記載の半導体装置。 - 前記配列方向において、前記エミッタ領域の下端と前記ベース領域とが接する長さは、前記コンタクト層と前記複数のトレンチ部のうち隣接するトレンチ部との最短距離よりも大きい
請求項1から4のいずれか一項に記載の半導体装置。 - 前記配列方向において、前記トレンチコンタクト部の側壁底部から前記コンタクト層の外周面までの最大距離は、前記コンタクト層と前記複数のトレンチ部のうち隣接するトレンチ部との最短距離よりも大きい
請求項2から4のいずれか一項に記載の半導体装置。 - 前記コンタクト層と前記複数のトレンチ部のうち隣接するトレンチ部との最短距離は、0.1μm以上である
請求項1から6のいずれか一項に記載の半導体装置。 - 前記コンタクト層は、前記エミッタ領域の下端よりも前記半導体基板のおもて面側に延伸した延伸領域を有する
請求項1から7のいずれか一項に記載の半導体装置。 - 前記トレンチコンタクト部は、略平面形状の底面を有する
請求項1から8のいずれか一項に記載の半導体装置。 - 前記トレンチコンタクト部は、前記半導体基板の裏面側に窪んだ凹状の底面を有する
請求項1から8のいずれか一項に記載の半導体装置。 - 前記コンタクト層は、
前記トレンチコンタクト部の側壁に設けられた第1コンタクト層と、
前記トレンチコンタクト部の側壁において、前記第1コンタクト層の下方に設けられた第2コンタクト層と
を有する請求項1または2に記載の半導体装置。 - 前記第1コンタクト層と、前記複数のトレンチ部のうち隣接するトレンチ部との最短距離は、前記第2コンタクト層と、前記複数のトレンチ部のうち隣接するトレンチ部との最短距離よりも大きい
請求項3、4または11のいずれか一項に記載の半導体装置。 - 前記第1コンタクト層のドーピング濃度は、前記第2コンタクト層のドーピング濃度よりも低い
請求項3、4、11または12のいずれか一項に記載の半導体装置。 - 前記トレンチコンタクト部は、前記複数のトレンチ部の延伸方向に延伸して設けられ、
前記トレンチコンタクト部の前記延伸方向における端部である終端部の側壁には、前記コンタクト層が設けられている
請求項1、3または4のいずれか一項に記載の半導体装置。 - 前記終端部の側壁は、前記エミッタ領域および前記コンタクト層で覆われている
請求項2または14に記載の半導体装置。 - 前記終端部の側壁は、第2導電型の領域で覆われている
請求項14に記載の半導体装置。 - 前記半導体基板のおもて面において、前記ベース領域よりも高ドーピング濃度である第2導電型のコンタクト領域を備え、
前記終端部の側壁は、前記コンタクト領域、前記ベース領域および前記コンタクト層で覆われている
請求項16に記載の半導体装置。 - 前記半導体基板のおもて面において、前記ベース領域よりも高ドーピング濃度である第2導電型のコンタクト領域を備え、
前記終端部の側壁は、前記コンタクト領域および前記コンタクト層で覆われている
請求項2または16に記載の半導体装置。 - 半導体基板に第1導電型のドリフト領域を設ける段階と、
前記ドリフト領域の上方に第2導電型のベース領域を設ける段階と、
前記ベース領域の上方に第1導電型のエミッタ領域を設ける段階と、
前記半導体基板のおもて面側において、複数のトレンチ部を予め定められた配列方向に配列して設ける段階と、
前記複数のトレンチ部のうち隣接する2つのトレンチ部の間において、前記半導体基板のおもて面側にトレンチコンタクト部を設ける段階と、
前記トレンチコンタクト部の下方に、前記ベース領域よりも高ドーピング濃度である第2導電型のコンタクト層を設ける段階と
を備え、
前記トレンチコンタクト部の下端が前記エミッタ領域の下端よりも深く、
前記トレンチコンタクト部の側壁において、前記半導体基板のおもて面に前記エミッタ領域が露出しており、
前記トレンチコンタクト部の側壁において、前記エミッタ領域と前記コンタクト層とが接触しており、
前記配列方向において、前記トレンチコンタクト部の側壁底部から前記コンタクト層の外周面までの最大距離は、前記コンタクト層と前記複数のトレンチ部のうち隣接するトレンチ部との最短距離よりも大きい
半導体装置の製造方法。 - 前記トレンチコンタクト部のコンタクトホールを設ける段階の後に、前記コンタクト層を形成するためにイオン注入する段階を備える
請求項19に記載の半導体装置の製造方法。 - 前記半導体基板の上方に酸化膜マスクを形成する段階と、
前記酸化膜マスクをマスクとして前記コンタクト層を形成するためにイオン注入する段階と
を備える請求項19または20に記載の半導体装置の製造方法。 - 前記トレンチコンタクト部の側壁に第1コンタクト層を形成する段階と、
前記トレンチコンタクト部の側壁において、前記第1コンタクト層の下方に第2コンタクト層を形成する段階と
を備え、
前記第1コンタクト層を形成するためのイオン注入の注入幅は、前記第2コンタクト層を形成するためのイオン注入の注入幅よりも小さい
請求項19から21のいずれか一項に記載の半導体装置の製造方法。 - 前記トレンチコンタクト部の側壁に第1コンタクト層を形成する段階と、
前記トレンチコンタクト部の側壁において、前記第1コンタクト層の下方に第2コンタクト層を形成する段階と
を備え、
前記第1コンタクト層のドーピング濃度は、前記第2コンタクト層のドーピング濃度よりも小さい
請求項19から21のいずれか一項に記載の半導体装置の製造方法。 - 前記ドリフト領域の前記半導体基板おもて面側に設けられ、前記ドリフト領域よりもドーピング濃度が大きい第1導電型の蓄積領域を備える
請求項1から18のいずれか一項に記載の半導体装置。 - 前記ドリフト領域の前記半導体基板おもて面側に、前記ドリフト領域よりもドーピング濃度が大きい第1導電型の蓄積領域を形成する段階を備える
請求項19から23のいずれか一項に記載の半導体装置の製造方法。
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