WO2020213230A1 - シリコン単結晶ウェーハの製造方法及びシリコン単結晶ウェーハ - Google Patents

シリコン単結晶ウェーハの製造方法及びシリコン単結晶ウェーハ Download PDF

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WO2020213230A1
WO2020213230A1 PCT/JP2020/004397 JP2020004397W WO2020213230A1 WO 2020213230 A1 WO2020213230 A1 WO 2020213230A1 JP 2020004397 W JP2020004397 W JP 2020004397W WO 2020213230 A1 WO2020213230 A1 WO 2020213230A1
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layer
single crystal
silicon single
crystal wafer
bmd
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English (en)
French (fr)
Japanese (ja)
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曲　偉峰
静男 井川
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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Priority to US17/601,112 priority Critical patent/US11959191B2/en
Priority to KR1020217032523A priority patent/KR102741720B1/ko
Priority to CN202080028464.7A priority patent/CN113906171B/zh
Priority to JP2021514801A priority patent/JP7388434B2/ja
Publication of WO2020213230A1 publication Critical patent/WO2020213230A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment

Definitions

  • the present invention relates to a method for manufacturing a silicon single crystal wafer for a multilayer structure device and a silicon single crystal wafer.
  • nitrogen, carbon, and boron are doped into a silicon single crystal for the purpose of imparting gettering ability and improving the strength of the bulk portion.
  • nitrogen, carbon, and boron are doped at high concentrations, there is a problem that oxygen precipitates are formed on the surface layer and the electrical characteristics are deteriorated.
  • measures have been taken to diffuse impurities outward by heat treatment.
  • a DZ layer is formed on the surface layer. In this DZ layer, oxygen is low due to the outward diffusion of oxygen, and slip is likely to occur due to the stress received during device formation.
  • Patent Document 1 Patent Document 2, and Patent Document 3 describe a technique for controlling the BMD density so that excessive oxygen precipitates are not formed, and Patent Document 4 provides proximity gettering adjacent to a defect-free region.
  • a capable single crystal wafer is disclosed.
  • Japanese Unexamined Patent Publication No. 2016-100542 Japanese Patent No. 4055343 Japanese Patent No. 4794137 Japanese Unexamined Patent Publication No. 2015-216375 Japanese Unexamined Patent Publication No. 2016-111044
  • the present invention has been made to solve the above problems, and defects caused by strain due to stress received on the surface of the silicon wafer during device formation can be absorbed by the BMD layer immediately below the surface layer portion, and the device forming region can be formed. It is an object of the present invention to provide a method for manufacturing a silicon single crystal wafer and a silicon single crystal wafer for a multilayer structure device capable of improving strength and suppressing the occurrence and elongation of dislocations on the surface layer.
  • the present invention has been made in order to achieve the above object, a method for producing a silicon single crystal wafer for a multi-layer structure device, the oxygen concentration is 12 ppma (JEITA) above, the silicon single crystal wafer of the N V region The thickness is 5 to 12.5 ⁇ m in order from the surface of the silicon single crystal wafer by performing RTA treatment, mirror polishing processing, and BMD forming heat treatment in a nitrogen-containing atmosphere and a temperature of 1225 ° C. or higher.
  • a silicon single crystal wafer for a multilayer structure device capable of improving the strength of the device forming region and suppressing dislocation generation and elongation in the surface layer.
  • the RTA treatment can be performed under heat treatment conditions of less than 10 seconds and a temperature lowering rate of 30 ° C./sec or more.
  • the effect of suppressing the outward diffusion of pores is higher, the pore distribution in the depth direction can be made steeper, and a steeper BMD density distribution can be obtained.
  • the BMD forming heat treatment can be performed under an argon atmosphere and heat treatment conditions at a temperature of 870 to 950 ° C. for 2 hours or more.
  • a silicon single crystal wafer for a multi-layer structure device the silicon single crystal wafer is of the N V region, a surface of a silicon single crystal wafer
  • the DZ layer and the BMD layer located immediately below the DZ layer are at least in this order, the thickness of the DZ layer is 5 to 12.5 ⁇ m, and the BMD density of the BMD layer is 1 ⁇ 10 11 / cm.
  • silicon single crystal wafer for a multilayer structure device capable of improving the strength of the device forming region and suppressing the occurrence and elongation of dislocations in the surface layer.
  • the strain layer, the DZ layer It has a laminated structure of at least three layers including a BMD layer, and when the silicon single crystal wafer on which the dents are formed is heat-treated at a temperature of 900 ° C. for 1 hour, the heat treatment is performed.
  • the rosette length of the dislocations of the DZ layer may be shorter than the rosette length of the dislocations of the DZ layer before the heat treatment.
  • a silicon single crystal wafer for a multilayer structure device capable of improving the strength of the device forming region and suppressing the occurrence and elongation of dislocations in the surface layer.
  • the silicon single crystal wafer of the present invention it is a silicon single crystal wafer for a multilayer structure device capable of improving the strength of the device forming region and suppressing the occurrence and elongation of dislocations in the surface layer.
  • the silicon single crystal wafer according to the present invention is shown.
  • An explanatory diagram of the rosette test is shown.
  • the relationship between the DZ layer thickness, the BMD density, and the rosette length difference value is shown.
  • the cross-sectional observation photograph of the silicon single crystal wafer which concerns on this invention is shown.
  • the relationship between the DZ layer thickness, the BMD density, and the rosette difference value of Example 2 and Comparative Example 2 is shown.
  • the relationship between the DZ layer thickness, the BMD density, and the rosette length difference value of Comparative Example 3 is shown.
  • defects caused by strain due to stress received on the surface of the silicon wafer during device formation can be absorbed by the BMD layer immediately below the surface layer, improving the strength of the device formation region and suppressing the occurrence and elongation of dislocations on the surface layer.
  • the present inventors have made intensive studies for the above problem, a method for producing a silicon single crystal wafer for a multi-layer structure device, the oxygen concentration is 12 ppma (JEITA) above, the silicon single crystal wafer of N V region DZ having a thickness of 5 to 12.5 ⁇ m in order from the surface of the silicon single crystal wafer by performing RTA treatment, mirror polishing processing, and BMD forming heat treatment in a nitrogen-containing atmosphere and a temperature of 1225 ° C. or higher.
  • a device forming region is formed by a method for manufacturing a silicon single crystal wafer, which manufactures a silicon single crystal wafer having a layer and a BMD layer having a BMD density of 1 ⁇ 10 11 / cm 3 or more located immediately below the DZ layer.
  • the present invention has been completed by finding that it is possible to manufacture a silicon single crystal wafer for a multilayer structure device capable of improving strength and suppressing generation and elongation of rearrangement in the surface layer.
  • a silicon single crystal wafer for a multi-layer structure device the silicon single crystal wafer is of the N V region, in order from the surface of a silicon single crystal wafer, and the DZ layer, located immediately under the said DZ layer
  • a silicon single crystal wafer having at least a BMD layer, the thickness of the DZ layer being 5 to 12.5 ⁇ m, and the BMD density of the BMD layer being 1 ⁇ 10 11 / cm 3 or more, the strength of the device forming region.
  • the present inventor has the thickness of the DZ layer 1 and the thickness of the BMD layer 2 of the silicon single crystal wafer 100 having at least the DZ layer 1 and the BMD layer 2 located immediately below the DZ layer 1 as shown in FIG.
  • the thickness of the DZ layer 1 and the BMD density of the BMD layer 2 satisfy a certain relationship, the strength of the device forming region is improved and the occurrence and elongation of dislocations in the surface layer are suppressed. I found that it would be possible.
  • the defect region is prepared entirely N V region a and the oxygen concentration is different from silicon single crystal CW (Chemical etched wafer) wafer, by changing the conditions of the RTA treatment and BMD formation heat treatment, various DZ layer thickness, BMD layer A silicon single crystal PW (Polished wafer) wafer having the BMD density of the above was prepared, and the effect of suppressing the occurrence and elongation of dislocations (dislocation absorption effect) was investigated. The contents and results of the survey will be described below.
  • This CW wafer was heat-treated as an RTA treatment at a temperature of 1150 to 1300 ° C., a time of 9 seconds, and an NH 3 + Ar atmosphere. Then, PW processing was performed with a targeting allowance of 6 ⁇ m. As a result, the nitride film formed by the RTA treatment was removed. Finally, as the BMD forming heat treatment, a heat treatment was performed at a temperature of 1200 ° C.
  • the thickness of the DZ layer was 0.5 to 19.4 ⁇ m and the BMD density was 3.5 ⁇ 10 9 / cm 3 to.
  • a sample of 4.9 ⁇ 10 11 / cm 3 was obtained.
  • the effect of suppressing the occurrence and elongation of dislocations was evaluated by a rosette test (measurement and comparison of rosette length).
  • the depth is 0.01 ⁇ m or more at a dent pressure of 0.24 to 2.9 N.
  • a dent of less than 00 ⁇ m was formed and the rosette length was measured.
  • the rosette length was also measured after the dents were formed and then heat-treated at 900 ° C. for 1 hour. Then, the rosette lengths before and after these heat treatments were compared.
  • the dislocation suppressing effect of the silicon single crystal wafer according to the present invention can be evaluated by the dislocation length (roset length).
  • the rosette test is an evaluation method described in Patent Document 5. In this evaluation method, strain is applied to the surface layer of the wafer by forming dents on the surface of the wafer to be evaluated. After that, heat treatment is performed to extend the dislocations, and the length of the dislocations (roset length) is measured. It can be judged that the shorter the length of the dislocation, the higher the ability to suppress the occurrence and elongation of dislocations.
  • a pressing pressure is applied to the surface layer of the prepared silicon single crystal wafer 100 using, for example, a Vickers hardness tester to form a dent 3. It should be noted that the machine or the like to be used is not particularly limited as long as it can form a dent by applying a pushing pressure to the surface layer of the wafer.
  • a pushing pressure Fz to form a dent 3 having a dent depth of Depth on the surface of the wafer so as to satisfy the relational expression of (less than .00 ⁇ m).
  • the dislocation extension region 5 is formed (FIG. 2).
  • the heat treatment temperature can be 850 ° C. or higher and 1200 ° C. or lower. As described above, when the temperature is 850 ° C. or higher, the temperature is equal to or higher than the brittleness-ductile displacement temperature of silicon, and sufficient dislocations can be extended for evaluation. Further, if the temperature is 1200 ° C. or lower, the treatment can be performed in a vertical heat treatment furnace.
  • the heat treatment time can be, for example, 30 minutes or more and 1 hour or less. Times in this range are sufficient to extend dislocations. Further, it can have an Ar atmosphere. This is because Ar has no effect of inhibiting the movement of dislocations, so that the strength of the wafer itself can be evaluated more accurately.
  • the heat treatment condition is 900 ° C. for 1 hour, the dislocations in the DZ layer can be efficiently extended, and the absorption effect of the dislocations on the BMD layer after the heat treatment can be confirmed more accurately. As a result, it is possible to obtain a product having a higher ability to suppress the generation and elongation of dislocations.
  • selective etching is performed to make the dislocations manifest.
  • the selective etching is limited as long as the dislocations can be manifested, and the method is not particularly limited.
  • wet etching can be performed using an etching solution (solution C in JISH0609-199) in which hydrofluoric acid, nitric acid, acetic acid, and water are mixed.
  • dry etching such as reactive ion etching (RIE) may be performed.
  • the length of the dislocations is measured.
  • FIG. 3 shows the results of a survey conducted by the present inventor to achieve the above object.
  • FIG. 3 shows the relationship between the rosette length, the DZ layer thickness, and the BMD density.
  • the horizontal axis of the graph shown in FIG. 3 shows the reference value (reference) when the rosette length of the silicon single crystal PW wafer before the heat treatment at the temperature of 900 ° C. for 1 hour is used as the reference value, and each sample.
  • first axis (left vertical axis) of the vertical axis of FIG. 3 indicates the DZ layer thickness of the silicon single crystal wafer subjected to the RTA treatment and the BMD formation heat treatment
  • second axis of the vertical axis (right vertical axis). ) Indicates the BMD density of the BMD layer of the silicon single crystal wafer subjected to the RTA treatment and the BMD formation heat treatment.
  • the range of the region where the rosette length difference value is a positive value As shown in FIG. 3, in the range where the thickness of the DZ layer is 12.5 ⁇ m or less and the BMD density of the BMD layer is 1 ⁇ 10 11 / cm 3 or more, the range of the region where the rosette length difference value is a positive value. That is, it has been found that the effect of suppressing the generation and elongation of dislocations is enhanced, and the wafer is suitable for a multilayer structure device. When the thickness of the DZ layer is 10 ⁇ m or less, the above effect can be obtained more stably. As will be described in detail in comparison with Example 1 and Comparative Example 1 described later, the condition that the rosette length difference value is in the range of positive values is that the RTA processing temperature is in the range of 1225 ° C. or higher. The thickness of the DZ layer is set to 5 ⁇ m or more in order to secure a device manufacturing area.
  • the silicon single crystal wafer 100 according to the present invention are those of the N V region. Then, as shown in FIG. 1, it has at least a DZ layer 1 and a BMD layer 2 located immediately below the DZ layer 1 in order from the surface of the wafer.
  • a DZ layer 1 located immediately below the DZ layer 1 in order from the surface of the wafer.
  • BMD layer 2 may be the BMD layer 2 in all parts of the silicon single crystal wafer 100 except the DZ layer 1, or only a part of the silicon single crystal wafer 100 other than the DZ layer 1. May be the BMD layer 2.
  • the thickness of the DZ layer is particularly 5 to 12.5 ⁇ m, preferably 5 to 10 ⁇ m, and the BMD density of the BMD layer is 1 ⁇ 10 11 / cm 3 or more. It is characterized by points.
  • the thickness of the DZ layer and the BMD density of the BMD layer are within the above ranges, a silicon single crystal wafer having an extremely high effect of absorbing dislocations can be obtained.
  • a multilayer structure device is formed using such a silicon single crystal wafer, it is possible to suppress the generation and elongation of dislocations generated in the device forming region, and it is possible to suppress the occurrence of defects such as slips.
  • the rosette length of dislocations of the DZ layer after the heat treatment is increased. It is shorter than the rosette length of the dislocation of the DZ layer of the silicon single crystal wafer (PW) on which the BMD layer is not formed.
  • PW silicon single crystal wafer
  • the oxygen concentration is 12 ppma (JEITA) above, a silicon single crystal wafer of the N V region.
  • the upper limit of the oxygen concentration is not particularly limited, but can be, for example, 17 ppma (JEITA) or less.
  • a CW wafer satisfying such specifications is prepared, and first, RTA treatment is performed in a nitrogen-containing atmosphere and a temperature of 1225 ° C. or higher.
  • the heat treatment conditions for this RTA treatment are preferably less than 10 seconds and a temperature lowering rate of 30 ° C./sec or more.
  • the lower limit of the heat treatment time for the RTA treatment is not particularly limited, and may be, for example, 1 second or more.
  • the upper limit of the temperature lowering rate is not particularly limited, but can be, for example, 100 ° C./sec or less.
  • the density distribution can be made steeper.
  • the upper limit of the BMD density is not particularly limited, but can be, for example, 1 ⁇ 10 12 / cm 3 or less.
  • mirror polishing is performed.
  • the mirror polishing processing conditions are not particularly limited, and mirror polishing that satisfies the usual specifications may be performed.
  • a BMD layer having a BMD density of 1 ⁇ 10 11 / cm 3 or more is formed by performing a BMD forming heat treatment on a silicon single crystal wafer that has been subjected to a mirror polishing process.
  • the heat treatment conditions for forming the BMD at this time are preferably an argon atmosphere, 870 to 950 ° C., and 2 hours or more. Under such heat treatment conditions, only those having a large precipitated nucleus size to some extent grow, so that the BMD distribution can be made steeper.
  • the heat treatment time even if it is excessively long, no change in the BMD density distribution is observed. Therefore, for example, it is efficient and preferable to set it to 8 hours or less.
  • Example 1 a silicon single crystal CW wafer having a diameter of 300 mm, ⁇ 100>, P type, 10 ⁇ cm, an oxygen concentration of 14 ppma (JEITA), and a defect region of the entire Nv region was prepared.
  • This CW wafer was heat-treated as an RTA treatment at a temperature of 1225-1300 ° C. for 9 seconds in an NH 3 + Ar atmosphere.
  • PW processing was performed with a targeting allowance of 6 ⁇ m.
  • the nitride film formed by the RTA treatment was removed.
  • a heat treatment was performed at a temperature of 1200 ° C. for 2 hours in an Ar atmosphere.
  • the DZ layer thickness and BMD density of the obtained silicon single crystal wafer were measured.
  • the DZ layer thickness was 6.7 to 10.5 ⁇ m
  • the BMD density was 1.8 ⁇ 10 11 to 4.9 ⁇ 10 11 / cm 3 .
  • FIG. 4 shows a cross-sectional TEM image when the RTA treatment temperature is 1300 ° C., the DZ layer thickness is 6.7 ⁇ m, and the BMD density is 4.9 ⁇ 10 11 / cm 3 .
  • dents having a depth of 1 to 5 ⁇ m are formed on the wafer surface at a pushing pressure of 0.24 to 2.9 N.
  • the rosette length was measured by a rosette test before and after the heat treatment at 900 ° C. for 1 hour. The difference in rosette lengths obtained in this way was calculated as a rosette length difference value.
  • Example 1 The treatment and evaluation were carried out in the same manner as in Example 1 except that the RTA treatment temperature was set to 1150 ° C to 1200 ° C.
  • the DZ layer thickness was 14.7 to 19.4 ⁇ m, and the BMD density was 3.5 ⁇ 10 9 to 6.6 ⁇ 10 10 / cm 3 .
  • the rosette length difference value of Example 1 was 2 to 13 ⁇ m.
  • the rosette length difference value of Comparative Example 1 was -3 to -12 ⁇ m.
  • Example 2 A sample was prepared using a silicon single crystal CW wafer having an oxygen concentration of 12 ppma (JEITA) under the same conditions as in Example 1 except that the RTA treatment temperature was 1225 to 1250 ° C.
  • the DZ layer thickness of the obtained silicon single crystal wafer was 10.3 to 12.3 ⁇ m, and the BMD density was 1.3 ⁇ 10 11 to 1.7 ⁇ 10 11 / cm 3 .
  • the rosette length difference value was 0.5 to 6.0 ⁇ m.
  • Comparative Example 2 A sample was prepared using a silicon single crystal CW wafer having an oxygen concentration of 12 ppma (JEITA) under the same conditions as in Example 1 except that the RTA treatment temperature was 1175 to 1200 ° C.
  • the DZ layer thickness of the obtained silicon single crystal wafer was 15.7 to 18.7 ⁇ m, and the BMD density was 5.4 ⁇ 10 9 to 7.1 ⁇ 10 10 / cm 3 .
  • the rosette length difference value was -2.0 to -5.5 ⁇ m.
  • Example 2 The results of Example 2 and Comparative Example 2 are shown in FIG. In Example 2, it was possible to obtain a silicon single crystal wafer in which the rosette length difference value is in the positive range.
  • Example 3 A sample was prepared using a silicon single crystal CW wafer having an oxygen concentration of 11 ppma (JEITA) under the same conditions as in Example 1 except that the RTA treatment temperature was set to 1225 to 1300 ° C.
  • the DZ layer thickness of the obtained silicon single crystal wafer was 21.5 to 33.0 ⁇ m, and the BMD density was 1.0 ⁇ 10 9 to 4.6 ⁇ 10 9 / cm 3 .
  • the rosette length difference value was -5.0 to -12.0 ⁇ m.
  • Comparative Example 3 The result of Comparative Example 3 is shown in FIG.
  • the oxygen concentration was less than 12 ppma (JEITA)
  • JEITA a silicon single crystal wafer having a positive rosette length difference value could not be obtained even if the RTA treatment temperature was raised.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an example, and any object having substantially the same configuration as the technical idea described in the claims of the present invention and exhibiting the same effect and effect is the present invention. Is included in the technical scope of.

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PCT/JP2020/004397 2019-04-16 2020-02-05 シリコン単結晶ウェーハの製造方法及びシリコン単結晶ウェーハ Ceased WO2020213230A1 (ja)

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US17/601,112 US11959191B2 (en) 2019-04-16 2020-02-05 Method for manufacturing silicon single crystal wafer and silicon single crystal wafer
KR1020217032523A KR102741720B1 (ko) 2019-04-16 2020-02-05 실리콘 단결정 웨이퍼의 제조방법 및 실리콘 단결정 웨이퍼
CN202080028464.7A CN113906171B (zh) 2019-04-16 2020-02-05 单晶硅晶圆的制造方法及单晶硅晶圆
JP2021514801A JP7388434B2 (ja) 2019-04-16 2020-02-05 シリコン単結晶ウェーハの製造方法及びシリコン単結晶ウェーハ

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