WO2019244383A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2019244383A1
WO2019244383A1 PCT/JP2019/001315 JP2019001315W WO2019244383A1 WO 2019244383 A1 WO2019244383 A1 WO 2019244383A1 JP 2019001315 W JP2019001315 W JP 2019001315W WO 2019244383 A1 WO2019244383 A1 WO 2019244383A1
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WIPO (PCT)
Prior art keywords
layer
main surface
semiconductor device
semiconductor
metal
Prior art date
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Ceased
Application number
PCT/JP2019/001315
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English (en)
French (fr)
Japanese (ja)
Inventor
知恵 藤岡
吉田　弘
芳宏 松島
水原　秀樹
正生 浜崎
光章 坂本
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Filing date
Publication date
Application filed by Panasonic Intellectual Property Management Co Ltd filed Critical Panasonic Intellectual Property Management Co Ltd
Priority to CN201980040521.0A priority Critical patent/CN112368845B/zh
Priority to US16/488,199 priority patent/US10903359B2/en
Priority to JP2019533664A priority patent/JP6614470B1/ja
Priority to KR1020217006309A priority patent/KR102234945B1/ko
Priority to KR1020207036456A priority patent/KR102571505B1/ko
Publication of WO2019244383A1 publication Critical patent/WO2019244383A1/ja
Priority to US17/125,635 priority patent/US11107915B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/477—Vertical HEMTs or vertical HHMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/478—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

  • the metal layer 31 has a main surface 31a (third main surface) and a main surface 31b (fourth main surface) facing each other, and the main surface 31a is formed in contact with the main surface 40b.
  • a first metal layer made of a first metal material.
  • the first metal material includes, for example, silver (Ag), copper (Cu), or gold (Au).
  • the Ag layer having a relatively large linear expansion coefficient is in contact with the Ag layer having a relatively large linear expansion coefficient
  • the Ag layer having a relatively large crystal grain size is also in contact with the Ag layer having a relatively large crystal grain size. Since the Ni layer having a relatively small diameter is in contact with the Ni layer, the Ag layer is less likely to extend when the temperature is raised, and the effect of suppressing the warpage of the semiconductor device 1 is increased.
  • the metal layer 30 (Ni layer) includes the first layer having the main surface 30a and the second layer having the main surface 30b, and the first layer in the horizontal direction of the main surface 30b.
  • the metal crystals forming the layer and the metal crystals forming the second layer may have different preferred orientation planes.
  • the mechanical strength and hardness at the outer periphery of the Ni layer can be reinforced, so that the suppression of the warpage of the semiconductor device 1A can be enhanced.
  • the protrusions 36A and 36B may be formed on two or all sides of the metal layer 30 (Ni layer) facing each other in plan view.
  • the protrusion width of the protrusions 36A and 36B is, for example, 4 ⁇ m or more.
  • the content of the second metal material is larger than the content of the first metal material.
  • the Ni content in the protrusions 36A and 36B is larger than the Ag content.
  • the protrusions 37A and 37B are provided on the outer periphery of the metal layer 31 (Ag layer) in a direction from the main surface 31b to the main surface 31a (z-axis positive direction). ) Are the second protrusions protruding from the main surface 31a.
  • the protrusions 37A and 37B include at least one of a first metal material of the metal layer 31 (Ag layer) and a second metal material of the metal layer 30 (Ni layer).
  • the protrusions 37A and 37B include at least one of Ag and Ni.
  • FIG. 14 is a cross-sectional view of the semiconductor device 1G according to the embodiment.
  • the semiconductor device 1G includes a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), and transistors 10 and 20.
  • the semiconductor device 1G is different from the semiconductor device 1 in that, when the semiconductor layer 40 (Si layer) is viewed in plan, the outer periphery of the semiconductor layer 40 (Si layer) is formed of the metal layers 30 (Ni layer) and 31 (Ag layer). The difference is that the semiconductor device 1G is retracted toward the center of the semiconductor device 1G from the outer periphery.
  • the same points of the semiconductor device 1G as those of the semiconductor device 1 will not be described, and different points will be mainly described.
  • FIG. 15 is a diagram illustrating the receding distance of the Si layer in the semiconductor device 1G according to the embodiment.
  • FIG. 3 is a cross-sectional view of a boundary region between two adjacent semiconductor devices 1G in a manufacturing process.
  • Plasma dicing is a dry etching method in which a Si layer is chemically removed using a plasma reaction, and can be cut without causing chipping on a cut surface of the Si layer.
  • a margin width is added to a later blade dicing or laser dicing dicing cutting width (a laser processing width or a blade processing width in FIG. 15) of a region where blade dicing or laser dicing is performed later.
  • the Si layer corresponding to the cutting width is removed by plasma dicing.
  • the Ag layer and the Ni layer are cut by blade dicing or laser dicing. Thereby, individualization of the semiconductor device 1G can be performed without causing chipping on the outer peripheral portion of the Si layer.
  • the interval between the Si layers of the adjacent semiconductor devices 1G should be smaller than the laser processing width or the blade processing width. It is necessary to secure a large amount.
  • the outer periphery of the Si layer is formed inside at an interval from the outer periphery of the Ag layer.
  • FIG. 16 is an electron micrograph of a side surface of the Si layer in the semiconductor device 1G according to the embodiment.
  • the maximum height roughness Rz of the unevenness on the side surface of the outer peripheral side surface of the semiconductor layer 40 (Si layer) on the side of the main surface 40b in contact with the main surface 31a is equal to the semiconductor layer 40 (Si layer).
  • FIG. 19 is a cross-sectional view of the semiconductor device 1J according to the embodiment.
  • the semiconductor device 1J has a semiconductor layer 40 (Si layer), metal layers 30 (Ni layer) and 31 (Ag layer), transistors 10 and 20, and grooves 43A and 43B.
  • the semiconductor device 1J is different from the semiconductor device 1G in that the semiconductor device 1J has grooves 43A and 43B.
  • the same points of the semiconductor device 1J as those of the semiconductor device 1G will not be described, and different points will be mainly described.
  • a two-dimensional electron gas 136 is generated near the boundary between the group III nitride semiconductor layer 137 and the group III nitride semiconductor layer 135.
  • a two-dimensional electron gas 146 is generated near the boundary between the group III nitride semiconductor layer 147 and the group III nitride semiconductor layer 145.
  • the group III nitride semiconductor layers 133 and 143 may be one continuous layer. Further, group III nitride semiconductor layers 135 and 145 may be one continuous layer. Further, group III nitride semiconductor layers 137 and 147 may be one continuous layer. Further, the two-dimensional electron gases 136 and 146 may be continuous.
  • a source electrode 211 (and 221) is provided in contact with the surface of the high-concentration n-type impurity layer inside the p-type impurity layer and the surface of the p-type impurity layer, and the high-concentration n-type impurity inside the p-type impurity layer is provided.
  • a gate conductor 219 (and 229) is provided between the layer and the low-concentration n-type impurity layer 233 at a position facing the p-type impurity layer via an insulating film 216.
  • the metal layer 231 functions as a common drain electrode of the first vertical SiC transistor and the second vertical SiC transistor.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Laser Beam Processing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Bipolar Transistors (AREA)
  • Noodles (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
PCT/JP2019/001315 2018-06-19 2019-01-17 半導体装置 Ceased WO2019244383A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN201980040521.0A CN112368845B (zh) 2018-06-19 2019-01-17 半导体装置
US16/488,199 US10903359B2 (en) 2018-06-19 2019-01-17 Semiconductor device
JP2019533664A JP6614470B1 (ja) 2018-06-19 2019-01-17 半導体装置
KR1020217006309A KR102234945B1 (ko) 2018-06-19 2019-01-17 반도체 장치
KR1020207036456A KR102571505B1 (ko) 2018-06-19 2019-01-17 반도체 장치
US17/125,635 US11107915B2 (en) 2018-06-19 2020-12-17 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201862687051P 2018-06-19 2018-06-19
US62/687,051 2018-06-19

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/488,199 A-371-Of-International US10903359B2 (en) 2018-06-19 2019-01-17 Semiconductor device
US17/125,635 Continuation US11107915B2 (en) 2018-06-19 2020-12-17 Semiconductor device

Publications (1)

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WO2019244383A1 true WO2019244383A1 (ja) 2019-12-26

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US (2) US10903359B2 (enExample)
JP (2) JP6614470B1 (enExample)
KR (2) KR102571505B1 (enExample)
CN (2) CN112368845B (enExample)
TW (2) TWI789481B (enExample)
WO (1) WO2019244383A1 (enExample)

Cited By (3)

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US20220310539A1 (en) * 2021-03-23 2022-09-29 Kabushiki Kaisha Toshiba Semiconductor device
WO2023139813A1 (ja) * 2022-01-19 2023-07-27 ヌヴォトンテクノロジージャパン株式会社 半導体装置及びレーザマーキング方法
TWI880637B (zh) * 2023-12-27 2025-04-11 台灣積體電路製造股份有限公司 半導體結構以及製造半導體結構的方法

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CN108598161B (zh) * 2018-04-29 2021-03-09 杭州电子科技大学 一种利用全固态电池实现的增强型iii-v hemt器件
KR102571505B1 (ko) * 2018-06-19 2023-08-28 누보톤 테크놀로지 재팬 가부시키가이샤 반도체 장치
CN111684608B (zh) 2018-12-19 2021-05-04 新唐科技日本株式会社 半导体装置
US12369381B2 (en) * 2019-09-30 2025-07-22 Rohm Co., Ltd. Semiconductor device
JP7470070B2 (ja) * 2021-02-18 2024-04-17 株式会社東芝 半導体装置
KR102550988B1 (ko) * 2021-03-29 2023-07-04 누보톤 테크놀로지 재팬 가부시키가이샤 반도체 장치, 전지 보호 회로, 및, 파워 매니지먼트 회로
JP7551554B2 (ja) * 2021-03-30 2024-09-17 株式会社東芝 半導体装置
TW202301451A (zh) 2021-06-25 2023-01-01 日商佳能股份有限公司 半導體裝置和製造半導體裝置的方法
US12155245B2 (en) 2022-01-18 2024-11-26 Innoscience (suzhou) Semiconductor Co., Ltd. Nitride-based bidirectional switching device for battery management and method for manufacturing the same
EP4244893A4 (en) * 2022-01-18 2023-11-29 Innoscience (Suzhou) Semiconductor Co., Ltd. Nitride-based bidirectional switching device for battery management and method for manufacturing the same
CN117441235B (zh) * 2022-08-24 2024-05-10 新唐科技日本株式会社 半导体装置
WO2024042809A1 (ja) * 2022-08-24 2024-02-29 ヌヴォトンテクノロジージャパン株式会社 半導体装置
CN119096357B (zh) 2023-01-23 2025-10-17 新唐科技日本株式会社 半导体装置
JP7651085B1 (ja) * 2024-03-21 2025-03-25 ヌヴォトンテクノロジージャパン株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011219828A (ja) * 2010-04-12 2011-11-04 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JP2013247309A (ja) * 2012-05-29 2013-12-09 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
US20170358510A1 (en) * 2016-06-09 2017-12-14 Magnachip Semiconductor, Ltd. Wafer-level chip-scale package including power semiconductor and manufacturing method thereof
JP2018049974A (ja) * 2016-09-23 2018-03-29 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100374204B1 (ko) * 2000-05-03 2003-03-04 한국과학기술원 2차원 노즐배치를 갖는 잉크젯 프린트헤드 및 그 제조방법
JP2006147700A (ja) * 2004-11-17 2006-06-08 Sanyo Electric Co Ltd 半導体装置
JP2007088030A (ja) * 2005-09-20 2007-04-05 Fuji Electric Holdings Co Ltd 半導体装置
JP5073992B2 (ja) * 2006-08-28 2012-11-14 オンセミコンダクター・トレーディング・リミテッド 半導体装置
KR100942555B1 (ko) * 2008-02-29 2010-02-12 삼성모바일디스플레이주식회사 플렉서블 기판, 이의 제조 방법 및 이를 이용한 박막트랜지스터
JP2008199037A (ja) * 2008-03-10 2008-08-28 Renesas Technology Corp 電力用半導体装置および電源回路
JP2010092895A (ja) * 2008-10-03 2010-04-22 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US8513798B2 (en) * 2010-09-09 2013-08-20 Infineon Technologies Ag Power semiconductor chip package
JP2012182238A (ja) 2011-02-28 2012-09-20 Panasonic Corp 半導体装置
JP2012182239A (ja) * 2011-02-28 2012-09-20 Panasonic Corp 半導体装置の製造方法
JP5995435B2 (ja) * 2011-08-02 2016-09-21 ローム株式会社 半導体装置およびその製造方法
JP5481605B2 (ja) * 2012-03-23 2014-04-23 パナソニック株式会社 半導体素子
JP2015231033A (ja) * 2014-06-06 2015-12-21 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US9793243B2 (en) * 2014-08-13 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer(s) on a stacked structure having a via
JP2016086006A (ja) 2014-10-23 2016-05-19 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
GB2535484B (en) * 2015-02-17 2019-10-09 Dynex Semiconductor Ltd Wafer metallization of high power semiconductor devices
CN107710400A (zh) 2015-07-01 2018-02-16 松下知识产权经营株式会社 半导体装置
WO2018025839A1 (ja) 2016-08-02 2018-02-08 パナソニックＩｐマネジメント株式会社 半導体装置、半導体モジュール、および半導体パッケージ装置
CN114975302A (zh) 2016-12-27 2022-08-30 新唐科技日本株式会社 半导体装置
KR102571505B1 (ko) * 2018-06-19 2023-08-28 누보톤 테크놀로지 재팬 가부시키가이샤 반도체 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011219828A (ja) * 2010-04-12 2011-11-04 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JP2013247309A (ja) * 2012-05-29 2013-12-09 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
US20170358510A1 (en) * 2016-06-09 2017-12-14 Magnachip Semiconductor, Ltd. Wafer-level chip-scale package including power semiconductor and manufacturing method thereof
JP2018049974A (ja) * 2016-09-23 2018-03-29 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220310539A1 (en) * 2021-03-23 2022-09-29 Kabushiki Kaisha Toshiba Semiconductor device
WO2023139813A1 (ja) * 2022-01-19 2023-07-27 ヌヴォトンテクノロジージャパン株式会社 半導体装置及びレーザマーキング方法
JP7355970B1 (ja) * 2022-01-19 2023-10-03 ヌヴォトンテクノロジージャパン株式会社 半導体装置及びレーザマーキング方法
CN117425948A (zh) * 2022-01-19 2024-01-19 新唐科技日本株式会社 半导体装置及激光打标方法
CN117425948B (zh) * 2022-01-19 2024-05-28 新唐科技日本株式会社 半导体装置及激光打标方法
US12322709B2 (en) 2022-01-19 2025-06-03 Nuvoton Technology Corporation Japan Semiconductor device and laser marking method
TWI880637B (zh) * 2023-12-27 2025-04-11 台灣積體電路製造股份有限公司 半導體結構以及製造半導體結構的方法

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