TW201611111A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

Info

Publication number
TW201611111A
TW201611111A TW104106550A TW104106550A TW201611111A TW 201611111 A TW201611111 A TW 201611111A TW 104106550 A TW104106550 A TW 104106550A TW 104106550 A TW104106550 A TW 104106550A TW 201611111 A TW201611111 A TW 201611111A
Authority
TW
Taiwan
Prior art keywords
semiconductor substrate
grinding
semiconductor
manufacturing
semiconductor device
Prior art date
Application number
TW104106550A
Other languages
English (en)
Inventor
Shingo Masuko
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201611111A publication Critical patent/TW201611111A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

本發明之實施形態係提供一種抑制半導體基板之翹曲之半導體裝置之製造方法。 本發明之實施形態之半導體裝置之製造方法為：對具備具有第1面與第2面之半導體基板及設置於上述半導體基板之上述第1面上之含氮化鎵層，且厚度為d1之上述半導體基板之上述第2面進行研削，其後以上述研削時之削去量之1/2~1/50之量對上述第2面進行研磨，其後以上述研削時之削去量之1/200~1/5000之量對上述第2面進行蝕刻，而使上述半導體基板之厚度小於等於上述d1之5分之1。

Description

半導體裝置之製造方法
[相關申請]
本申請案享有以日本專利申請2014-185632號(申請日：2014年9月11日)為基礎申請之優先權。本申請案藉由參照該基礎申請而包含基礎申請之全部內容。
本發明之實施形態係關於一種半導體裝置之製造方法。
對於使用氮化鎵之裝置而言，使裝置內之半導體基板儘量薄化而謀求裝置之小型化正成為一種趨勢。半導體基板之薄化例如係藉由背面研削(backgrind)而進行。
但是，於使用矽基板作為氮化鎵之基板之情形時，由於矽之晶格常數與氮化鎵之晶格常數之失配，故而矽基板內部存在應力。若於此種狀況下對半導體基板進行背面研削，則有如下情況：因藉由背面研削而產生之研削痕跡，導致矽基板產生較大翹曲。並且，若該翹曲超過限度，則有矽基板破裂之可能性。
本發明所欲解決之問題在於提供一種抑制半導體基板之翹曲之半導體裝置之製造方法。
本發明之實施形態之半導體裝置之製造方法係對具備具有第1面與第2面之半導體基板及設置於上述半導體基板之上述第1面上之含氮化鎵層，且厚度為d1之上述半導體基板之上述第2面進行研削，其後 以上述研削時之削去量之1/2~1/50之量對上述第2面進行研磨，其後以上述研削時之削去量之1/200~1/5000之量對上述第2面進行蝕刻，而使上述半導體基板之厚度小於等於上述d1之5分之1。
1‧‧‧半導體晶片
10‧‧‧半導體基板
10ca‧‧‧研削痕跡
10cb‧‧‧研削痕跡
10r‧‧‧第2面
10s‧‧‧第1面
10d‧‧‧切割線
30‧‧‧含氮化鎵層
31‧‧‧含氮化鋁層
32‧‧‧含氮化鋁鎵層
33‧‧‧含氮化鎵層
34‧‧‧含氮化鋁鎵層
50‧‧‧第1電極
51‧‧‧第2電極
52‧‧‧第3電極
53‧‧‧閘極絕緣膜
55‧‧‧導電層
90‧‧‧加工機
91‧‧‧研磨帶
圖1係表示實施形態之半導體裝置之製造方法的流程圖。
圖2係表示對實施形態之半導體基板進行研削或研磨之加工機之主要部分的模式性立體圖。
圖3(a)及圖3(b)係表示實施形態之半導體裝置之製造過程的模式圖，圖3(a)係表示半導體基板之背面的模式性俯視圖，圖3(b)係圖3(a)之A-A'線之模式性剖視圖。
圖4(a)及圖4(b)係表示實施形態之半導體裝置之製造過程的模式圖，圖4(a)係表示半導體基板之背面的模式性俯視圖，圖4(b)係圖4(a)之A-A'線之模式性剖視圖。
圖5(a)及圖5(b)係表示實施形態之半導體裝置之製造過程的模式圖，圖5(a)係表示半導體基板之背面的模式性俯視圖，圖5(b)係圖5(a)之A-A'線之模式性剖視圖。
圖6(a)及圖6(b)係表示實施形態之半導體裝置之製造過程的模式圖，圖6(a)係表示半導體基板之背面的模式性俯視圖，圖6(b)係圖6(a)之A-A'線之模式性剖視圖。
圖7(a)及圖7(b)係表示實施形態之半導體裝置之製造過程的模式圖，圖7(a)係表示半導體基板之背面的模式性俯視圖，圖7(b)係圖7(a)之A-A'線之模式性剖視圖。
圖8(a)及圖8(b)係表示實施形態之半導體裝置之製造過程的模式圖，圖8(a)係表示單片化後之半導體基板之背面的模式性俯視圖，圖8(b)係表示單片化後之半導體裝置之剖面的模式性剖視圖。
圖9係實施形態之半導體晶片之主要部分之模式性剖視圖。
以下，一面參照圖式一面對實施形態進行說明。於以下之說明中，對相同之構件附上相同符號，且對於說明過一次之構件，適當省略其說明。
圖1係表示實施形態之半導體裝置之製造方法的流程圖。
例如，於設置於半導體基板之上之含氮化鎵層之表面形成第1電極、第2電極及第3電極(步驟S10)。此處，半導體基板為矽基板。作為一例，第1電極~第3電極對應於高電子遷移率電晶體之源極、汲極及閘極。又，並不限於高電子遷移率電晶體，亦可為MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金屬-氧化物半導體場效應電晶體)之源極、汲極及閘極。
繼而，對半導體基板之背面進行研削、研磨及蝕刻，而使半導體基板之厚度小於等於5分之1(步驟S20)。
繼而，於進行過研削、研磨及蝕刻之半導體基板之背面形成導電層(步驟S30)。
繼而，藉由切割而將半導體基板、含氮化鎵層及導電層進行分離(步驟S40)。
以下，具體地說明圖1所表示之流程圖。
首先，於對實施形態之半導體裝置之製造過程進行說明之前，對研削或研磨半導體基板之加工機進行說明。
圖2係表示研削或研磨實施形態之半導體基板之加工機之主要部分的模式性立體圖。
如圖2所示，向載置於研磨膠帶91上之半導體基板10之背面10r抵壓對該背面10r進行研削(背面研削(B.G.))或研磨(拋光研磨(P.G.))之加工機90。加工機90或半導體基板10可向箭頭之方向旋轉。
加工機90並非覆蓋半導體基板10之整面，例如加工機90之直徑 被設計大於等於半導體基板10之半徑。於加工機90與半導體基板10之間介置金剛石等研削(研磨)粒，藉由加工機90之旋轉或半導體基板10之旋轉而對半導體基板10之背面10r進行研削或研磨。
此處，利用研削之半導體基板10之去除速度快於利用研磨之半導體基板10之去除速度。又，研磨時所使用之研磨粒之平均粒徑小於研削中所使用之研削粒之平均粒徑。換言之，研磨係研削之所謂精加工處理。
對實施形態之半導體裝置之製造過程進行說明。
圖3(a)~圖7(b)係表示實施形態之半導體裝置之製造過程的模式圖，各圖(a)係表示半導體基板之背面的模式性俯視圖，各圖(b)係表示圖(a)之A-A'線之剖面之模式性剖視圖。
例如，如圖3(a)、(b)所示，於具有第1面(以下，例如稱為表面10s)與第2面(以下，例如稱為背面10r)之半導體基板10之表面10s使含氮化鎵層30磊晶成長(epitaxial growth)。此處，含氮化鎵層30具有複數層(下述)。又，將該階段之半導體基板10之厚度設為d1(例如，1mm)。含氮化鎵層30之厚度為10μm。
繼而，於含氮化鎵層30之上形成第1電極(以下，例如稱為源極電極50)、第2電極(以下，例如稱為汲極電極51)及第3電極(以下，例如稱為閘極電極52)。此處，汲極電極51係與源極電極50並排，且閘極電極52被配置於源極電極50與汲極電極51之間。於閘極電極52與含氮化鎵層30之間設置有閘極絕緣膜53。源極電極50、汲極電極51及閘極電極52之組合可設置複數個。
再者，亦可於形成源極電極50、汲極電極51及閘極電極52之後，形成被覆半導體基板10及含氮化鎵層30之表面的鈍化膜(未圖示)。又，亦可形成分別電性連接於源極電極50、汲極電極51及閘極電極52之電極墊(未圖示)。
繼而，如圖4(a)、(b)所示，使用加工機90對半導體基板10之背面10r進行研削。
研削例如可使用JIS標準之粒度# 1500之研削粒(例如，金剛石研削粒)而進行。例如將金剛石研削粒(固定研削粒)固定於加工機90之與半導體基板10之抵接面，而對半導體基板10之背面10r進行研削。
研削中，亦可將油等溶劑、醇等有機溶劑、水等溶劑介置於加工機90與半導體基板10之間。或者，亦可不使用該等溶劑而進行研削。
對半導體基板10進行研削後，於半導體基板10之背面10r形成與加工機90之旋轉方向對應之研削痕跡10ca。若於半導體基板10上形成研削痕跡10ca，則對半導體基板10施加之應力之一部分被釋放，會導致半導體基板10翹曲。
此處，於翹曲之程度超過限度之情形時，有半導體基板10發生破裂之情況。或者，若將形成有研削痕跡10ca之半導體基板10設置於成膜裝置等別的處理裝置內，則有半導體基板10發生破裂之情況。又，即便半導體基板10未破裂，使用殘留有研削痕跡10ca之半導體基板10之裝置之抗彎強度亦會降低。
因此，於實施形態中，其後進行使形成於半導體基板10上之研削痕跡10ca減少之處理。
例如，如圖5(a)、(b)所示，使較研削時更細之金剛石研磨粒介置於加工機90與半導體基板10之間，而對半導體基板10之背面10r進行研磨。
例如，使金剛石研磨粒游離於背面10r之上，對半導體基板10之背面10r進行研磨。或者，藉由化學機械研磨法(CMP)而對半導體基板10之背面10r進行研磨。
該研磨時之背面10r之削去量少於研削時之削去量，例如設為研 削時之削去量之1/2~1/50。
藉由該研磨處理，於半導體基板10之背面10r殘留研削痕跡10ca之深度變得更淺之研削痕跡10cb。又，與形成有研削痕跡10ca之情況相比，半導體基板10之翹曲程度得以緩和。
繼而，如圖6(a)、(b)所示，對半導體基板10之背面10r進行蝕刻。例如，利用包含碳、硫及氟之至少1種之氣體而對半導體基板10之背面10r進行乾式蝕刻。
或者，利用包含氟之溶液，對半導體基板10之背面10r進行濕式蝕刻。
該蝕刻時之背面10r之削去量少於研磨時之削去量，例如設為研削時之削去量之1/200~1/5000。
藉由該蝕刻處理，殘留於半導體基板10之背面10r處之研削痕跡10cb進一步減少。又，與形成有研削痕跡10cb之情況相比，半導體基板10之翹曲程度得以緩和。即，與僅進行過研削處理之半導體基板10相比，實施形態之半導體基板10之研削痕跡較少而變得不易破裂。
例如，結束圖4(a)、(b)~圖6(a)、(b)之處理之後，半導體基板10之厚度變得小於等於當初厚度d1之5分之1。例如，於圖3(a)、(b)所示之階段，半導體基板10之厚度為1mm之情形時，結束圖4(a)、(b)~圖6(a)、(b)之處理之後，半導體基板10之厚度變得小於等於200μm。
結束圖4(a)、(b)~圖6(a)、(b)之處理後之半導體基板10之厚度不限於小於等於200μm。
例如，將結束圖4(a)、(b)~圖6(a)、(b)之處理後之半導體基板10之厚度、與含氮化鎵層30之厚度相加而獲得之厚度係半導體基板之直徑每1英吋小於等於50μm。例如於使用直徑8英吋之半導體基板10之情形時，結束圖4(a)、(b)~圖6(a)、(b)之處理後之半導體基板10與含氮化鎵層30之厚度變得小於等於400μm。
或者，將結束圖4(a)、(b)~圖6(a)、(b)之處理後之半導體基板10之厚度、與含氮化鎵層30之厚度相加而獲得之厚度係半導體基板之直徑每1英吋小於等於25μm。例如於使用直徑8英吋之半導體基板10之情形時，結束圖4(a)、(b)~圖6(a)、(b)之處理後之半導體基板10與含氮化鎵層30之厚度變得小於等於200μm。
又，結束圖4(a)、(b)~圖6(a)、(b)之處理後之半導體基板10之背面10r之表面粗糙度Ra大於等於0.006μm且小於等於0.008μm。
又，於將結束圖4(a)、(b)~圖6(a)、(b)之處理後之半導體基板10載置於平坦之支持台(未圖示)上之情形時，半導體基板10之中心距支持台之高度、與半導體基板10之邊緣距支持台之高度的差變得小於等於150μm。
繼而，如圖7(a)、(b)所示，於半導體基板10之背面10r形成導電層55。導電層55於安裝半導體基板10時可用作焊接用之電極。或者，導電層55可用作使半導體基板10之背面10r側之電位穩定之接地層，進而可用作散熱體。
圖8(a)及圖8(b)係表示實施形態之半導體裝置之製造過程的模式圖，圖8(a)係表示單片化後之半導體基板之背面的模式性俯視圖，圖8(b)係表示單片化後之半導體裝置之剖面的模式性剖視圖。
繼而，如圖8(a)、(b)所示，每包含源極電極50、汲極電極51及閘極電極52為一組將半導體基板10、含氮化鎵層30及導電層55進行分離。例如，沿著切割線10d，藉由分割處理而將半導體基板10、含氮化鎵層30及導電層55進行分離。由此，形成經單片化之多個半導體晶片1。其後，使用黏晶(die bonding)、打線接合(wire bonding)及密封樹脂而進行半導體晶片1之封裝化。
如上所述，於實施形態中，對支持含氮化鎵層30之矽基板等半導體基板10之背面10r進行研削、研磨及蝕刻。由此，半導體基板10 之研削痕跡減少，而抑制半導體基板10之翹曲。其結果為，半導體基板10變得不易破裂。
又，於實施形態中，由於可使半導體基板10之厚度變薄，故而可謀求半導體晶片1之薄型化。由此，半導體封裝之厚度亦變薄。又，由於使研削痕跡減少，故而半導體晶片1之抗彎強度增加。
圖9係實施形態之半導體晶片之主要部分之模式性剖視圖。
圖9所示之半導體晶片1包括：半導體基板10；設置於半導體基板10之上之含氮化鎵層30；設置於含氮化鎵層30之上之源極電極50；與源極電極50並排之汲極電極51；設置於源極電極50與汲極電極51之間之閘極電極52；及設置於半導體基板10下方之導電層55。於閘極電極52與含氮化鎵層30之間設置有閘極絕緣膜53。半導體晶片1為HEMT(high electron mobility transistorm，高電子遷移率電晶體)。
含氮化鎵層30具有：含氮化鋁層31、含氮化鋁鎵層32、含氮化鎵層33及含氮化鋁鎵層34。
源極電極50及汲極電極51係與含氮化鋁鎵層34歐姆接觸。閘極絕緣膜53包含氮化矽膜(Si3N4)、氧化矽膜(SiO2)、氧化鋁(Al2O3)中之任一種。
含氮化鋁層31與含氮化鋁鎵層32係作為HEMT之緩衝層而發揮功能。含氮化鎵層33係作為HEMT之載子移動層而發揮功能。含氮化鋁鎵層34係作為HEMT之阻擋層而發揮功能。含氮化鋁鎵層34係非摻雜或n型之AlXGa1-XN(0<X≦1)層。於含氮化鎵層33內之含氮化鎵層33與含氮化鋁鎵層34之界面附近產生二維電子。此種半導體晶片1亦包含於實施形態中。
再者，本說明書中所謂「氮化物半導體」，總體而言，包括成為BxInyAlzGa1-x-y-zN(0≦x≦1，0≦y≦1，0≦z≦1，x+y+z≦1)之化學式中使組成比x、y及z於各自範圍內進行變化之全部組成之半導體。 又，「氮化物半導體」進而包括上述化學式中進一步包含N(氮)以外之V族元素之半導體、進一步包含為了控制導電型等各種物性而添加之各種元素之氮化物半導體、及進一步包含非刻意含有之各種元素之氮化物半導體。
於上述實施形態中，所謂表述為「部位A設置於部位B之上」之情況下之「之上」，除部位A與部位B接觸，且在部位B之上設置有部位A之情況外，亦有以如下含義使用之情況，即部位A不與部位B接觸，而於部位B之上方設置有部位A之情況。又，「部位A設置於部位B之上」存在如下情況，即亦適用於使部位A與部位B反轉從而部位A位於部位B之下之情況；或部位A與部位B橫向排列之情況。其原因在於：即便使實施形態之半導體裝置旋轉，於旋轉前後半導體裝置之構造不發生改變。
以上，一面參照具體例一面對實施形態進行了說明。但是，實施形態並不限定於該等具體例。即，只要具有實施形態之特徵，則業者對該等具體例適當加以設計變更之實施形態亦包含在實施形態之範圍內。上述各具體例所包含之各要素及其配置、材料、條件、形狀、尺寸等並不限定於所例示之具體例，可適當進行變更。
又，上述之各實施形態所包含之各要素只要技術上可能，則可進行組合，只要具有實施形態之特徵，則將該等組合而成之實施形態亦包含在實施形態之範圍內。此外，於實施形態之思想範疇中，業者可想到各種變化例及修正例，且明瞭該等變化例及修正例亦屬於實施形態之範圍。
對本發明之若干實施形態進行了說明，但該等實施形態係作為例子而提示之實施形態，並非意在限定發明之範圍。該等新穎實施形態可於其他各種形態下實施，且可於不脫離發明之主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含在發明之範圍及 主旨內，並且亦包含在申請專利範圍所記載之發明及與其等同之範圍內。

Claims (10)

  1. 一種半導體裝置之製造方法，其係對具備具有第1面與第2面之半導體基板及設置於上述半導體基板之上述第1面上之含氮化鎵層，且厚度為d1之上述半導體基板之上述第2面進行研削，其後以上述研削時之削去量之1/2~1/50之量對上述第2面進行研磨，其後以上述研削時之削去量之1/200~1/5000之量對上述第2面進行蝕刻，而使上述半導體基板之厚度小於等於上述d1之5分之1。
  2. 如請求項1之半導體裝置之製造方法，其中對上述半導體基板之上述第2面進行研削、研磨及蝕刻後之上述半導體基板之上述第2面之表面粗糙度Ra大於等於0.006μm且小於等於0.008μm。
  3. 如請求項1或2之半導體裝置之製造方法，其中將對上述半導體基板之上述第2面進行研削、研磨及蝕刻後之上述半導體基板之厚度、與上述含氮化鎵層之厚度相加而獲得之厚度係上述半導體基板之直徑每1英吋小於等於25μm。
  4. 如請求項1或2之半導體裝置之製造方法，其中於將對上述半導體基板之上述第2面進行研削、研磨及蝕刻後之上述半導體基板載置於支持台上之情形時，上述半導體基板之中心距上述支持台之高度、與上述半導體基板之邊緣距上述支持台之高度的差小於等於150μm。
  5. 如請求項1或2之半導體裝置之製造方法，其中藉由固定於研削上述半導體基板之研削機上之固定研削粒而對上述半導體基板之上述第2面進行研削。
  6. 如請求項5之半導體裝置之製造方法，其中利用上述固定研削粒之研削係不使用溶劑而進行。
  7. 如請求項1或2之半導體裝置之製造方法，其中使研磨粒於上述半導體基板之上述第2面之上游離而對上述第2面進行研磨。
  8. 如請求項1或2之半導體裝置之製造方法，其中藉由化學機械研磨法對上述半導體基板之上述第2面進行研磨。
  9. 如請求項1或2之半導體裝置之製造方法，其中利用包含碳、硫及氟之至少1種之氣體對上述半導體基板之上述第2面進行蝕刻。
  10. 如請求項1或2之半導體裝置之製造方法，其中利用包含氟之溶液對上述半導體基板之上述第2面進行蝕刻。
TW104106550A 2014-09-11 2015-03-02 半導體裝置之製造方法 TW201611111A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014185632A JP2016058651A (ja) 2014-09-11 2014-09-11 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW201611111A true TW201611111A (zh) 2016-03-16

Family

ID=55455465

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104106550A TW201611111A (zh) 2014-09-11 2015-03-02 半導體裝置之製造方法

Country Status (4)

Country Link
US (1) US9472467B2 (zh)
JP (1) JP2016058651A (zh)
CN (1) CN105990136A (zh)
TW (1) TW201611111A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI747496B (zh) * 2020-09-16 2021-11-21 世界先進積體電路股份有限公司 晶粒結構及電子裝置
US11588036B2 (en) 2020-11-11 2023-02-21 Vanguard International Semiconductor Corporation High-efficiency packaged chip structure and electronic device including the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114050198B (zh) * 2021-09-30 2024-05-17 北京大学 一种基于半导体材料的辐射热流调控器件及其应用

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004165564A (ja) * 2002-11-15 2004-06-10 Showa Denko Kk 窒化ガリウム結晶基板の製造方法と窒化ガリウム結晶基板及びそれを備えた窒化ガリウム系半導体素子
US6866560B1 (en) * 2003-01-09 2005-03-15 Sandia Corporation Method for thinning specimen
EP1709670B1 (en) * 2004-01-26 2012-09-12 Showa Denko K.K. Group iii nitride semiconductor multilayer structure
JP4790322B2 (ja) * 2005-06-10 2011-10-12 株式会社ディスコ 加工装置および加工方法
JP4696886B2 (ja) * 2005-12-08 2011-06-08 日立電線株式会社 自立した窒化ガリウム単結晶基板の製造方法、および窒化物半導体素子の製造方法
JP2011009563A (ja) * 2009-06-26 2011-01-13 Showa Denko Kk 半導体発光素子の製造方法及び半導体発光素子
JP5348075B2 (ja) * 2010-06-02 2013-11-20 ソニー株式会社 半導体発光素子の製造方法、半導体素子の製造方法および素子の製造方法
TWI443741B (zh) * 2011-01-14 2014-07-01 Univ Nat Chiao Tung 一種平整化氮化物基板的方法
JP2012160515A (ja) 2011-01-31 2012-08-23 Disco Abrasive Syst Ltd 被加工物の加工方法
JP5919626B2 (ja) * 2011-02-25 2016-05-18 富士通株式会社 化合物半導体装置及びその製造方法
JP5433909B2 (ja) * 2012-05-22 2014-03-05 株式会社パウデック ＧａＮ系半導体素子の製造方法
CN102832224B (zh) * 2012-09-10 2015-04-15 豪威科技(上海)有限公司 晶圆减薄方法
CN103606517B (zh) * 2013-09-18 2016-06-01 中国东方电气集团有限公司 一种硅片减薄方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI747496B (zh) * 2020-09-16 2021-11-21 世界先進積體電路股份有限公司 晶粒結構及電子裝置
US11588036B2 (en) 2020-11-11 2023-02-21 Vanguard International Semiconductor Corporation High-efficiency packaged chip structure and electronic device including the same

Also Published As

Publication number Publication date
JP2016058651A (ja) 2016-04-21
CN105990136A (zh) 2016-10-05
US20160079123A1 (en) 2016-03-17
US9472467B2 (en) 2016-10-18

Similar Documents

Publication Publication Date Title
US8487316B2 (en) Method of manufacturing an integrated semiconductor substrate structure with device areas for definition of GaN-based devices and CMOS devices
JP6214172B2 (ja) 高電子移動度トランジスタ及びその製造方法
US10115802B2 (en) Manufacturing method for compound semiconductor device
US9966311B2 (en) Semiconductor device manufacturing method
CN107863294B (zh) 半导体晶片和方法
KR101932327B1 (ko) 반도체 웨이퍼 및 방법
KR20120037315A (ko) 이 모드(Ｅ-ｍｏｄｅ) 고 전자 이동도 트랜지스터 및 그 제조방법
WO2019244383A1 (ja) 半導体装置
US20170365667A1 (en) Epitaxial substrate
JP5687422B2 (ja) 半導体装置
TW201611111A (zh) 半導體裝置之製造方法
US9941386B2 (en) Semiconductor device structure with fin structure and method for forming the same
US9865679B2 (en) Compound semiconductor device, method for producing same, and resin-sealed type semiconductor device
JP2016058678A (ja) 半導体装置およびその製造方法
US9711404B2 (en) Semiconductor device and manufacturing method thereof
CN107871662B (zh) 使表面平面化的方法
US11239327B2 (en) HEMT and method of adjusting electron density of 2DEG
US20140284660A1 (en) Method for manufacturing semiconductor wafer, and semiconductor wafer
WO2023164821A1 (en) Semiconductor device and method for manufacturing the same
WO2017158747A1 (ja) エピタキシャル基板の製造方法および半導体装置の製造方法
WO2024040513A1 (en) Semiconductor device and method for manufacturing the same
WO2014038374A1 (ja) 半導体装置の製造方法
JP2017055014A (ja) 半導体装置の製造方法
JP2014127698A (ja) 半導体装置の製造方法