CN101028728A - 晶片级尺寸封装的切割方法 - Google Patents

晶片级尺寸封装的切割方法 Download PDF

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CN101028728A
CN101028728A CNA2006101527402A CN200610152740A CN101028728A CN 101028728 A CN101028728 A CN 101028728A CN A2006101527402 A CNA2006101527402 A CN A2006101527402A CN 200610152740 A CN200610152740 A CN 200610152740A CN 101028728 A CN101028728 A CN 101028728A
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encapsulation
substrate
cushion
wafer size
separating
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杨文焜
余俊辉
张瑞贤
许献文
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Yupei Science & Technology Co Ltd
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Abstract

本发明提供了一种半导体组件封装的分离方法，属于半导体组件封装领域。所述方法包括：在晶片的基板背面涂一层光环氧化物(photo epoxy)层，以标记所要切割的切割线。然后，沿着上述光环氧化物层中的记号蚀刻上述基板。使用一般美工刀将上述面板切割成为单一封装。本发明提供的半导体组件封装的分离方法不仅可以避免每个晶粒的边缘粗糙，并且可以降低切割程序的成本。

Description

晶片级尺寸封装的切割方法
技术领域
本发明涉及半导体组件封装领域，特别涉及一种半导体组件封装的切割方法，用于将面板(panel)分离成为分离的封装。
背景技术
在电子组件领域中，集成电路(IC)通常是制造在半导体基板上的，如已知的芯片(chip)，并且该芯片通常由硅(silicon)构成。这种硅芯片通常装配在大型封装中，以有效增加输入/输出硅接点间的距离或间距(pitch)，这样才适合装配到印刷电路板(printed circuitboard)，并且保护IC免受机械或环境的损害。
一般IC是由晶片切割之后再一一封装，而晶片级尺寸封装(wafer level package；WLP)或芯片尺度封装(chip scale package；CSP)的发展提供了另一种解决手段，这种手段直接附属覆晶组件，多个晶粒是封装之后才被切割成为单个组件。晶粒的分离是通过一切割步骤将半导体基板切割成为个别的晶粒。晶片切割技术的快速发展满足了封装上的各种需求，能够提高产量、提高量率以及降低成本。
如图1所示，是现有技术晶片中的多个覆晶组件的侧视图。复晶100包括具有金属垫106的晶粒105，它通常具有一般IC组件的结构。上述晶粒105是通过黏着层104附着在一基板102上，并且晶粒105具有多个电性连接108，例如：重布层(redistribution layer；RDL)线路。凸块，例如：锡球107，形成在电性连接108上。保护层109覆盖在电性连接108上，同时为连接锡球107部分电性连接108没有覆盖层。此外，缓冲层101形成在基板102的底部表面。
组件100通常通过切割刀在具有锡球107的表面上沿着虚线110切割来分离面板。上述切割刀通常由一些坚硬的材料构成，目前市面上有这种刀具，例如：(1)钻石烧结刀(sintereddiamond blade)，将钻石粒子熔入如黄铜或红铜等软金属中，或是通过粉末冶金的方法结合而成；(2)碟式钻石刀，是通过电镀处理将钻石粒子熔入镍中与镍结合形成的；(3)树脂钻石刀，将钻石粒子熔入树脂中产生均质的基础。硅晶片切割大多采用碟式钻石刀，该应用已经获得了成功的验证。
一般工业标准上虽然已经采用切割刀来切割晶片以及面板，但是上述切割还存在某些缺点。首先，切割刀会随着工作时间而受到磨损，因而新刀具与使用过的刀具的切割质量不同。因此，操作者必须提前估计刀具什么时候到达它的使用寿命，但是该使用寿命通常无法准确地被估计。所以上述刀具通常会在到达使用寿命之前被更换，因而增加了设备成本。另外，在切割过程中，刀具会将机械应力引入工作对象中，特别是工作物的表面上，所以刀具无法切割非常薄的工作件，例如超薄半导体晶片。IC技术在微波与混合电路、内存、计算机、医疗保健类等电子应用的增加为该应用在工业上带来了新的难题。
使用切割刀的另一缺点是耗费时间。通常处理一片晶片必须花费2至3小时。上述问题不仅影响到产品的生产量，也增加了处理晶片或面板所需的成本。
使用切割刀的还有一个缺点是成本较高。由于切割刀并非普通刀具，它通常比一般刀具昂贵。一个切割刀通常约为60美元，而根据切割机械的设计通常一个切割机械上不止一把切割刀。
使用切割刀切割还有一个缺点，即每次切割后的晶粒边缘粗糙。由于切割处理是研磨与切割类似的机械磨蚀过程，每个晶粒的边缘通常非常粗糙或容易产生毛边。
发明内容
鉴于上述现有技术中的问题，本发明提供了崭新的用于晶片尺寸封装的封装切割方法，本发明提供的半导体组件封装的切割方法可避免每个晶粒的边缘在经过切割刀切割后所产生的毛边。
根据本发明的切割方法可以避免切割刀成本过高，并且也能避免传统切割方法耗时过长的问题。
本发明提供一种用于分离晶片级尺寸封装的方法，包括：(a)在基板的第一表面涂上缓冲层，其中上述缓冲层中具有标示每个晶粒的纹路；(b)切割上述封装，由上述晶片尺寸封装的第二表面沿着一切割线以一机械力(例如刀)切割；(c)沿着上述纹路蚀刻上述晶片尺寸封装组件的基板。
其中上述缓冲层包括：光环氧物(photo epoxy)。其中上述纹路的厚度约与上述缓冲层的厚度相等。其中上述纹路的宽度是固定的。其中上述蚀刻步骤包括湿蚀刻步骤，其中所使用的蚀刻溶液包括：氯化铁、氯化铜以及硫酸铵。其中上述蚀刻步骤中基板的材料包括：硅、合金42、石英或陶瓷。
另外，本发明提供了一种半导体组件封装结构。上述结构包括：晶粒，在该晶粒的第一表面上具有多个电性连接；多个导电球耦合于该电性连接上；第一缓冲层附着在上述晶粒的第二表面；第一缓冲层形成在上述基板上紧邻的上述晶粒；以及第二缓冲层，其中上述第二缓冲层配置覆盖于上述基板，其中上述基板与上述第二缓冲层凹陷于上述第一缓冲层。其中上述第二缓冲层中的凹陷约为上述纹路宽度的一半。
上述缓冲层能够提供保护功能，用以避免当上述晶粒或基板的边缘部分碰撞一外部物体时所造成的损伤。
本发明的技术方案带来的有益效果是：
通过本发明提供的切割方法可避免每个晶粒在经过切割刀切割后边缘所产生的毛边。同时也可以避免切割刀成本过高，并且避免了传统切割方法耗时过长的问题。
附图说明
图1是现有技术中晶片级尺寸封装结构的侧视图；
图2A是本发明的半导体晶片结构的第一侧视图；
图2B是本发明的半导体晶片结构的第二侧视图；
图2C是本发明的半导体晶片结构的第三侧视图；
图2D是本发明的半导体晶片结构的第四侧视图；
图2E是本发明的半导体晶片结构的第五侧视图；
图2F是本发明的半导体晶片结构的第六侧视图；
图3A是本发明中单个半导体晶片结构的第一侧视图；
图3B是本发明中单个半导体晶片结构的第二侧视图；
图3C是本发明中单个半导体晶片结构的第三侧视图；
图3D是本发明中单个半导体晶片结构的第四侧视图。
附图中，各标号所代表的部件列表如下：
100    复晶
101    缓冲层
102    基板
104    黏着层
105    晶粒
106    金属垫
107    锡球
108    电性连接
109    保护层
110    虚线
200    晶片
201    第二缓冲层
202    基板
203    第一缓冲层
204    黏着层
205    晶粒
206    金属垫
207    锡球
208    电性连接
209    保护层
210    纹路
211    蚀刻道
212    切割线
213    核心材料
214    残留
215    凹陷
216    复晶
具体实施方式
下面结合附图和具体实施例对本发明作进一步说明，但不作为对本发明的限定。
在此，本发明将详细地叙述一些实施例。然而，除了明确的叙述外，本发明可以实施在一广泛范围内的其它实施例中，并且本发明的范围不受限于本发明提供的实施例，保护范围是专利申请中权利要求的范围。此外，组件的不同部分没有按照比例显示。相关部件的尺寸是放大的，并且没有意义的部分没有显示，以使所提供的技术方案更清楚，利于理解。
首先参考图2A，是本发明的半导体晶片结构的第一侧视图，如图所示为显示晶片200的一部分，包括多个晶粒205，它上面有金属垫206与锡球207，以电性连接一印刷电路板(未显示于图中)。保护层209覆盖电性连接208，并暴露电性连接208的一部分，该暴露的部分上允许形成接触金属球。
晶粒205的背面通过一黏着层204直接附着在基板202上，并且第一缓冲层203形成在基板202上紧邻晶粒205的位置。应当注意，基板202的尺寸远大于晶粒205的尺寸。电性连接208的材料为金属合金，例如：通过溅镀方式形成的钛/铜合金及/或以电镀方式形成的铜/镍/金合金。第一缓冲层203的材料包括核心(core)材料，它是一种弹性材料，例如：硅橡胶、硅树脂、弹性聚氨基甲酸酯(elastic PU)、多孔性聚氨基甲酸酯(porous PU)、丙烯酸橡胶(acrylic rubber)、蓝胶(blue tape)或UV胶。基板202包括但不限定为硅、玻璃、合金42、石英或陶瓷。
在本实施例中，本发明的切割方法的第一步骤是形成第二缓冲层201于基板202的背面。第二缓冲层201中有纹路210，位于每个晶粒间的位置，约对齐第一缓冲层203。每个纹路210间的距离基本上是固定的，并且根据每个封装组件切割后的尺寸而定。每个纹路210的深度约与第二缓冲层201的厚度相同。第二缓冲层201的材料包括光环氧物(photo epoxy)。
参考图2B，是本发明的半导体晶片结构的第二侧视图，本发明的切割方法的第二步骤为：沿第一缓冲层203中的切割线212切割晶片200。上述切割线212约在纹路210的中央。上述切割步骤可以实施在具有锡球207的一侧。第一缓冲层203的材料包括：硅橡胶，它可以用任何刀具例如切割用的美工刀来切割。
参考图2C，是本发明的半导体晶片结构的第三侧视图，第三步骤是蚀刻基板202，它是通过湿蚀刻处理并且沿着第二缓冲层201中的纹路210而完成。上述湿蚀刻所使用的溶液包括：氯化铁、氯化铜以及硫酸铵。基板202被蚀刻道211所分离。蚀刻道211从位于第二缓冲层201中的纹路延伸至第一缓冲层203。
其中蚀刻道211以及第一缓冲层203之间可留有一小部分基板202，如图2D所示，是本发明的半导体晶片结构的第四侧视图，在本实施例中，介于蚀刻道211与第一缓冲层203之间的残留214的厚度小于50μm。
需要说明的是，上述第二步骤与第三步骤可以互换，即：先蚀刻上述基板，然后再切割晶片200为多个分离的封装。在本实施例中，上述蚀割道211中可填满核心(core)材料，它是一种弹性材料，例如：硅橡胶、硅树脂、弹性聚氨基甲酸酯(elastic PU)、多孔性聚氨基甲酸酯(porous PU)、丙烯酸橡胶(acrylic rubber)、蓝胶(blue tape)或UV胶，如图2E所示，是本发明的半导体晶片结构的第五侧视图。上述切割可以实施于晶片200的任何一个面上。
本发明还有一个实施例如图2F所示，是本发明的半导体晶片结构的第六侧视图。在本实施例中，蚀刻步骤实施在切割步骤之前。基板202的残留约略小于50um，并且蚀刻道211中填满核心材料213。上述切割步骤可实施在晶片200的任何一个面上。
根据本发明，在切割处理之后，上述面板被分离为个别的封装，共有四种不同的封装组件的结构，分别显示在图3A、图B、图C、图D中。在图3A中，是本发明中单个半导体晶片结构的第一侧视图，基板202被完全蚀刻形成沿着基板202以及第二缓冲层201边缘的凹陷215。在图3B中，是本发明中单个半导体晶片结构的第二侧视图，上述凹陷215中填满核心材料。在图3C中，是本发明中单个半导体晶片结构的第三侧视图，基板202并未被完全蚀穿，因此其封装的边缘具有残留214。在图3D中，是本发明中单个半导体晶片结构的第四侧视图，上述封装具有残留214，并且其边缘上的凹陷215中填满核心材料213。
本发明还揭露了一种半导体组件封装结构，其中基板202与第二缓冲层201的边缘凹陷(recess)于第一缓冲层203的边缘。复晶216的结构与图1中通过现有技术的切割处理的复晶结构不同。由一般切割刀所切割的复晶100的每一层的宽度是基本上相同，并且复晶100的边缘可能因为现有的切割而粗糙或起毛边。
综上所述，根据本发明方法所切割的半导体组件封装结构与使用一般切刻方式切割的半导体组件结构不同。使用一般切割方法所切割的组件结构由于每一层结构是同时被切割的，所以每一层的厚度相同。而根据本发明的封装组件结构，其基板与缓冲层的边缘具有凹陷。而这种特殊结构可用来决定一个组件是否是根据本发明的方式作切割的。
本发明以较佳实施例说明如上，然而它并不是用以限定本发明所提供的专利权利范围。专利保护范围以申请专利范围及其等同领域而定。凡本领域的技术人员，在不脱离本专利提供的方案范围内所作的修改，均属于本发明提供的技术所完成的等效改变或设计，应包含在本申请专利范围内。

Claims (10)

1.一种用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，包括：
在该基板的第一表面形成一缓冲层于，其中该缓冲层具有纹路标示该每一IC封装；
蚀刻该晶片尺寸封装组件的该基板，沿着该纹路因此产生开口；以及
切割该IC封装，通过机械力由该第一表面或第二表面沿着一切割线切割。
2.如权利要求1所述的用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，其中该缓冲层包括光环氧物。
3.如权利要求1所述的用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，进一步包括在实施该切割之前填入核心材料于该开口中。
4.如权利要求1所述的用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，其中该蚀刻步骤包括湿蚀刻步骤，其中所使用的蚀刻溶液包括：氯化铁、氯化铜以及硫酸铵。
5.如权利要求1所述的用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，其中该蚀刻步骤中的基板层的材料包：硅、合金42、石英或陶瓷。
6.一种用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，包括：
形成一缓冲层于该基板的第一表面，其中该缓冲层具有纹路标示该每一IC封装；
切割该IC封装，通过机械力由该第一表面或第二表面沿着一切割线切割；以及
蚀刻该晶片尺寸封装组件的该基板，沿着该纹路因此产生开口。
7.如权利要求6所述的用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，其中该缓冲层包括光环氧物。
8.如权利要求6所述的用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，其中该蚀刻步骤包括湿蚀刻步骤，其中所使用的蚀刻溶液包括：氯化铁、氯化铜以及硫酸铵。
9.如权利要求6所述的用于自一晶片尺寸封装的基板上分离IC封装的方法，其特征在于，其中该蚀刻步骤中的基板的材料包括：硅、合金42、石英或陶瓷。
10.一种半导体组件封装结构，其特征在于，包括：
一晶粒具有多个电性连接于该晶粒的一第一表面上；
多个导电球耦合于该连接；
一第一缓冲层附着在该晶粒的第二表面；
一第一缓冲层形成于该基板上紧邻该晶粒；以及
一第二缓冲层，其中该第二缓冲层配置覆盖于该基板，其中该基板与该第二缓冲层凹陷于该第一缓冲层。
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