WO2019038906A1 - パワー半導体装置およびパワー半導体装置の製造方法 - Google Patents

パワー半導体装置およびパワー半導体装置の製造方法 Download PDF

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Publication number
WO2019038906A1
WO2019038906A1 PCT/JP2017/030495 JP2017030495W WO2019038906A1 WO 2019038906 A1 WO2019038906 A1 WO 2019038906A1 JP 2017030495 W JP2017030495 W JP 2017030495W WO 2019038906 A1 WO2019038906 A1 WO 2019038906A1
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Prior art keywords
sealing resin
semiconductor device
power semiconductor
terminal
linear expansion
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PCT/JP2017/030495
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English (en)
French (fr)
Inventor
太志 佐々木
佑毅 吉岡
啓行 原田
勇輔 梶
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201780094087.5A priority Critical patent/CN111066142B/zh
Priority to PCT/JP2017/030495 priority patent/WO2019038906A1/ja
Priority to US16/622,225 priority patent/US11482462B2/en
Priority to JP2019537521A priority patent/JP6827545B2/ja
Priority to DE112017007982.9T priority patent/DE112017007982B4/de
Publication of WO2019038906A1 publication Critical patent/WO2019038906A1/ja

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Definitions

  • the present invention relates to a power semiconductor device and a method of manufacturing the power semiconductor device.
  • the conventional power semiconductor device includes a base plate, a case provided on the base plate, and a sealing resin filled in the case.
  • the linear expansion coefficient of the base plate is reduced by embedding a reinforcing plate made of Cu or Fe as a material in the base plate made of Al alloy, and the warpage of convexing the back surface of the base plate is reduced. Power semiconductor devices are described.
  • the present invention has been made to solve the above-described problems, and it is an object of the present invention to suppress crack in a sealing resin and suppress warpage of a semiconductor device in a power semiconductor device.
  • a power semiconductor device comprises a semiconductor element, a terminal joined to the upper surface of the semiconductor element, a casing for containing the semiconductor element and the terminal, and a sealing resin for sealing the semiconductor element and the terminal in the casing. Equipped with The sealing resin has a first sealing resin covering at least the semiconductor element, and a second sealing resin formed above the first sealing resin. At the operating temperature of the semiconductor element, the first sealing resin has a smaller linear expansion coefficient than the second sealing resin, and the difference in the linear expansion coefficient between the first sealing resin and the terminal is the second sealing. It is smaller than the difference in coefficient of linear expansion between the resin and the terminal.
  • the sealing resin is constituted by the first sealing resin which at least covers the semiconductor element, and the second sealing resin formed above the first sealing resin. Then, at the operating temperature of the semiconductor element, the first sealing resin has a smaller linear expansion coefficient than the second sealing resin, and the difference in linear expansion coefficient between the first sealing resin and the terminal is the second It is set to be smaller than the difference in linear expansion coefficient between the sealing resin and the terminal.
  • the first sealing resin that easily affects the semiconductor element, since the stress caused by the difference from the linear expansion coefficient of the terminal is smaller than that of the second sealing resin, the crack caused by this stress should be suppressed. Can.
  • the curing temperature can be set low. Therefore, the amount of contraction at the time of thermosetting of the second sealing resin can be reduced, and warpage of the power semiconductor device can be suppressed.
  • FIG. 1 is a cross sectional view showing a configuration of a power semiconductor device of a first embodiment. It is sectional drawing which shows the structure of the power semiconductor device of a comparative example. It is a figure which shows the temperature dependence of the linear expansion coefficient of sealing resin according to hardening temperature of sealing resin.
  • FIG. 5 is a diagram for explaining a manufacturing process of the power semiconductor device of the first embodiment.
  • FIG. 7 is a cross sectional view showing a configuration of a power semiconductor device of a second embodiment.
  • FIG. 16 is a cross sectional view showing a configuration of a power semiconductor device of a third embodiment.
  • FIG. 1 is a cross-sectional view showing a configuration of a power semiconductor device 101 according to the present embodiment.
  • the power semiconductor device 101 is widely used, for example, for home appliances, industrial applications, automobiles, and trains.
  • the configuration of the power semiconductor device 101 will be described below with reference to FIG.
  • Power semiconductor device 101 includes insulating pattern 1, conductive pattern 2, IGBT chip 4, diode chip 6, inner frames 9 and 12, main terminal 10, aluminum wire 11, signal terminal 13, insert case 14 and heat dissipation pin fin 16. There is.
  • Two conductive patterns 2 are formed on the upper surface of the insulating pattern 1, and on the conductive patterns 2, an IGBT chip 4 and a diode chip 6 which are semiconductor elements are joined by solders 3 and 5 respectively.
  • the inner frame 9 is joined to the upper surface of the IGBT chip 4 by the solder 7 and to the upper surface of the diode chip 6 by the solder 8.
  • the inner frame 9 is made of, for example, copper and is the same member as the main terminal 10.
  • An aluminum wire 11 is bonded to the upper surface of the IGBT chip 4. One end of the aluminum wire 11 is joined to the upper surface of the IGBT chip 4, and the other end is joined to the inner frame 12.
  • the inner frame 12 is made of, for example, copper and is the same member as the signal terminal 13.
  • the heat radiation pin fin 16 is joined to the lower surface of the insulation pattern 1.
  • the insulating pattern 1 is provided between the conductive pattern 2 and the heat dissipation pin fin 16 to insulate both.
  • Insulating pattern 1, conductive pattern 2, IGBT chip 4, diode chip 6, inner frames 9, 12 and aluminum wire 11 are accommodated in insert case 14.
  • the insert case 14 is a housing that forms the outer shape of the power semiconductor device, and has an insulating function.
  • the heat dissipating pin fins 16 are exposed from the lower surface of the insert case 14 and serve to dissipate the heat of the power semiconductor device 101.
  • the inside of the insert case 14 is filled with a sealing resin 21 which is a first sealing resin and a sealing resin 22 which is a second sealing resin.
  • the sealing resin 21 is filled on the lower side inside the insert case 14 and covers the IGBT chip 4 and the diode chip 6.
  • the sealing resin 22 is filled on the upper side of the sealing resin 21, that is, on the upper side inside the insert case 14.
  • the sealing resin 21 has a linear expansion coefficient lower than that of the sealing resin 22 in a high temperature range of 125 ° C. or more and 200 ° C. or less. That is, assuming that the linear expansion coefficient of the sealing resin 21 is ⁇ 1 and the linear expansion coefficient of the sealing resin 22 is ⁇ 2, there is a relation of ⁇ 1 ⁇ 2 in the above-mentioned high temperature range.
  • FIG. 2 is a cross-sectional view showing a configuration of a power semiconductor device 101E of a comparative example of the present embodiment.
  • the power semiconductor device 101E only one type of sealing resin 23 is filled inside the insert case 14 instead of the sealing resins 21 and 22. This point is different from the power semiconductor device 101 only.
  • FIG. 3 is a graph showing the temperature dependence of the linear expansion coefficient of the sealing resin for each curing temperature of the sealing resin.
  • the vertical axis represents linear expansion coefficient ⁇ (ppm / ° C.), and the horizontal axis represents temperature (° C.).
  • the two-dot chain line indicates the curing temperature of 140 ° C.
  • the solid line indicates the curing temperature of 160 ° C.
  • the one-dot chain line indicates the curing temperature of 180 ° C.
  • the broken line indicates the characteristics of the sealing resin at the curing temperature of 200 ° C.
  • copper is generally used for the inner frame 9 sealed in the sealing resin 23 in the power semiconductor device 101E and joined to the IGBT chip 4 and the diode chip 6 by the solders 7 and 8. Copper has a low electrical resistance, thereby suppressing loss during energization of the power semiconductor device 101E.
  • the linear expansion coefficient ⁇ of copper is 16.5-18.3 (ppm / ° C.) and about 17 (ppm / ° C.).
  • the linear expansion coefficient of the sealing resin 23 having a curing temperature of 140 ° C. will be examined with reference to FIG.
  • the linear expansion coefficient of the sealing resin 23 is about 17-20 (ppm / ° C.), which is approximately equal to about 17 (ppm / ° C.) of the linear expansion coefficient of the inner frame 9 Become. Therefore, the stress generated at the contact portion between the sealing resin 23 and the inner frame 9 is small.
  • the linear expansion coefficient of the sealing resin 23 is 30 (ppm / ° C.) or more, and the linear expansion coefficient of the inner frame 9 is about 17 (ppm / ° C.). The value is 10 (ppm / ° C.) or more.
  • the sealing resin 23 generally employs a thermosetting resin, there is a positive correlation between the curing temperature and the amount of shrinkage upon thermosetting. For example, when the curing temperature of the sealing resin 23 is increased from 140 ° C. to 160 ° C., the amount of shrinkage at the time of heat curing also increases. As a result, there is a problem that the amount of warpage of the power semiconductor device 101E such as the heat radiation pin fin 16 is increased.
  • the power semiconductor device 101 shown in FIG. 1 simultaneously suppresses the crack of the sealing resin due to the difference in linear expansion coefficient and the warpage of the power semiconductor device due to the shrinkage at the time of heat curing of the sealing resin.
  • the linear expansion coefficient of the sealing resin 21 is set to about 17 (ppm / ° C.) in a high temperature range of 125 ° C. to 200 ° C.
  • the sealing resin 21 shrinks more than the sealing resin 22 at the time of heat curing.
  • the sealing resin 21 is provided below the central portion of the power semiconductor device 101, it is possible to suppress the warpage of the power semiconductor device 101 due to the contraction of the sealing resin 21.
  • the central portion in the height direction from the lower surface to the upper surface of the inner frame 9 is taken as the central portion of the power semiconductor device 101.
  • the sealing resin 22 is provided on the upper side of the central portion of the power semiconductor device 101, but since the curing temperature is lower than that of the sealing resin 21, the sealing resin 22 does not shrink as much as the sealing resin 21 during thermosetting. Therefore, the warpage of the power semiconductor device 101 as a whole is suppressed.
  • the linear expansion coefficient in the high temperature area of 125 degreeC or more and 200 degrees C or less is larger than the inner frame 9 for the sealing resin 22, the stress resulting from the difference of a linear expansion coefficient may arise.
  • the sealing resin 22 does not directly cover the IGBT chip 4 and the diode chip 6, even if a crack occurs in the sealing resin 22, the influence on the IGBT chip 4 and the diode chip 6 is small, and the reliability of the power semiconductor device 101 is Sex is maintained.
  • the conductive pattern 2 is formed on the upper surface of the insulating pattern 1, and the IGBT chip 4 and the diode chip 6 are joined on the conductive pattern 2 via the solder 3 and 5.
  • the inner frame 9 is joined to the upper surface of the IGBT chip 4 via the solders 7 and 8.
  • Heat dissipation pin fins 16 are joined to the lower surface of the insulating pattern 1.
  • the joined body of the heat dissipating pin fin 16, the insulating pattern 1, the conductive pattern 2, the IGBT chip 4, the diode chip 6, and the inner frame 9 is housed in the insert case 14. At this time, the lower surface of the heat radiation pin 16 is exposed from the insert case 14.
  • the inner frame 12 on the signal terminal side is formed in the insert case 14, and the upper surfaces of the inner frame 12 and the IGBT chip 4 are bonded by the aluminum wire 11.
  • the sealing resin 21 is potted in the insert case 14 using a resin injection device. At this time, the sealing resin 21 is filled so as to cover at least the IGBT chip 4 and the diode chip 6. Furthermore, by covering the edge of the lower surface of the inner frame 9 to which the stress due to the difference in linear expansion coefficient is particularly applied with the sealing resin 21, the generation of the crack due to the stress due to the difference in linear expansion coefficient is effectively suppressed. be able to.
  • the sealing resin 21 it is desirable that all the aluminum wires 11 be covered with the sealing resin 21. If the aluminum wire 11 is sealed across the sealing resin 21 and the sealing resin 22, stress due to the difference in linear expansion coefficient between the sealing resin 21 and the sealing resin 22 is applied to the aluminum wire 11. I will. However, when the sealing resin 21 covers the entire aluminum wire 11, the stress described above can be prevented from being applied to the aluminum wire 11.
  • the sealing resin 21 is cured by heating.
  • the first temperature which is the curing temperature of the sealing resin 21 here, is, for example, 140 ° C., and is set lower than the second temperature, which is the curing temperature of the sealing resin 22 described later.
  • the surface layer of the inner frame 9 is oxidized by heat at the time of curing of the sealing resin 21, and the adhesive strength with the insert case 14 is reduced. Therefore, after the sealing resin 21 is cured, UV irradiation is performed on the upper surface of the sealing resin 21 and the inner frame 9 as shown by the arrow 31 in FIG. 4. As a result, the adhesion strength between the inner frame 9 and the insert case 14 is increased, and the adhesion strength between the sealing resins 21 and 22 is also improved. As a result, a power semiconductor device 101 having high reliability can be obtained.
  • the sealing resin 22 is potted in the insert case 14 using a resin injection device, and the sealing resin 22 is filled above the sealing resin 21. Thereafter, the sealing resin 22 is cured by heating.
  • the second temperature which is the curing temperature of the sealing resin 22, is, for example, 180 ° C., and is set lower than the first temperature, which is the curing temperature of the sealing resin 21.
  • the power semiconductor device 101 of the first embodiment includes the IGBT chip 4 and the diode chip 6 which are semiconductor elements, the inner frame 9 which is a terminal joined to the upper surface of the semiconductor element, the semiconductor element and An insert case 14, which is a case for housing the inner frame 9, and a sealing resin for sealing the semiconductor element and the inner frame 9 in the insert case are provided.
  • the sealing resin is a sealing resin 21 which is a first sealing resin covering at least the semiconductor element, and a sealing resin 22 which is a second sealing resin formed above the sealing resin 21.
  • the sealing resin 21 has a smaller linear expansion coefficient than the sealing resin 22, and the difference between the linear expansion coefficients of the sealing resin 21 and the inner frame 9 is the difference between the sealing resin 22 and the inner frame It is smaller than the difference of the linear expansion coefficient with 9.
  • the stress caused by the difference in linear expansion coefficient with the inner frame 9 is strongly applied around the edge of the lower surface which is the surface on the semiconductor element side of the inner frame 9, and a crack is easily generated. Therefore, in the power semiconductor device 101, by covering the edge of the lower surface of the inner frame 9 with the sealing resin 21, a crack in the sealing resin 21 due to the stress caused by the difference in linear expansion coefficient with the inner frame 9 is effectively made. Can be suppressed.
  • the linear expansion coefficient of copper is about 17 (ppm / ° C.) in the temperature range of 20 ° C. or more and 227 ° C. or less. Therefore, by setting the curing temperature of the sealing resin 21 to 160 ° C. or higher, a linear expansion coefficient close to that of the inner frame 9 can be realized at an operating temperature of 150 ° C. Therefore, the crack to the sealing resin 21 resulting from the difference in linear expansion coefficient can be suppressed.
  • the power semiconductor device 101 is required to ensure high-temperature operation.
  • the linear expansion coefficient of the sealing resin 21 is smaller than that of the sealing resin 22, and the difference between the linear expansion coefficients of the sealing resin 21 and the inner frame 9 is equal to that of the sealing resin 22 and the inner frame 9.
  • the same material may be used for the sealing resin 21 and the sealing resin 22.
  • the resin injection device can be shared by the sealing resin 21 and the sealing resin 22, and the introduction cost and arrangement area of the resin injection device can be reduced. Therefore, the manufacturing cost of the power semiconductor device 101 can be reduced.
  • the inner frame 9 is joined to the upper surfaces of the IGBT chip 4 and the diode chip 6, and the IGBT chip 4, the diode chip 6 and the inner frame 9 are accommodated by the insert case 14.
  • the IGBT chip 4 and the diode chip 6 in the insert case 14 are covered with the sealing resin 21 so that the upper surface of the inner frame 9 is exposed, and the sealing resin 21 is cured at a first temperature and sealed in the insert case 14
  • a sealing resin 22 is formed on the resin 21, and the sealing resin 22 is cured at a second temperature lower than the first temperature.
  • UV is applied to the upper surface of sealing resin 21 and the upper surface of inner frame 9. Irradiate. Therefore, the adhesion strength between the inner frame 9 and the insert case 14 is increased, and the adhesion strength between the sealing resins 21 and 22 is improved, so that the power semiconductor device 101 having high reliability can be obtained.
  • FIG. 5 is a cross-sectional view showing the configuration of the power semiconductor device 102 of the second embodiment.
  • the inner side surface of the insert case 14 has a recess 15. Except for this point, the configuration of the power semiconductor device 102 is the same as that of the power semiconductor device 101 of the first embodiment.
  • the recess 15 is formed at a position crossing the boundary between the sealing resin 21 and the sealing resin 22, and both the sealing resin 21 and the sealing resin 22 enter the recess 15 and are formed. Thereby, the sealing resin 21 and the sealing resin 22 are firmly joined to the insert case 14 by the anchor effect. As a result, even when a stress caused by the difference in linear expansion coefficient between the sealing resins 21 and 22 occurs at high temperature, the interface between the sealing resins 21 and 22 can be prevented from peeling off.
  • either one of the sealing resin 21 and the sealing resin 22 may be formed in the recess 15. Even in this case, since the bonding between the sealing resin in the recess 15 and the insert case 14 becomes strong, as a result, the sealing resins 21 and 22 are caused by the stress caused by the difference in linear expansion coefficient between the sealing resins 21 and 22. Interface peeling can be suppressed.
  • the power semiconductor device 102 of the second embodiment has a recess 15 on the inner side surface of the insert case 14 which is a housing. Therefore, bonding between the sealing resin that has entered the recess 15 and the insert case 14 becomes strong, and interfacial peeling of the sealing resins 21 and 22 is suppressed.
  • FIG. 6 is a cross-sectional view showing the configuration of a power semiconductor device 103 according to the third embodiment.
  • the power semiconductor device 103 has a polyimide layer 17 between the sealing resin 21 and the sealing resin 22. Except for this point, the configuration of power semiconductor device 103 is the same as that of power semiconductor device 102 of the second embodiment.
  • the polyimide layer 17 absorbs the stress between the sealing resins 21 and 22 because the Vickers hardness is lower than the cured sealing resins 21 and 22. Therefore, the adhesion between the sealing resin 21 and the polyimide layer 17 and between the polyimide layer 17 and the sealing resin 22 can be enhanced. Thus, a highly reliable power semiconductor device 103 can be obtained.
  • the power semiconductor device 103 according to the third embodiment includes the polyimide layer 17 between the sealing resin 21 and the sealing resin 22, so the sealing resin 21 and the polyimide layer 17, and the polyimide layer 17 and the sealing resin 22. The adhesion between them is high, and high reliability is obtained.
  • each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

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Abstract

本発明は、パワー半導体装置において封止樹脂のクラック抑制と半導体装置の反り抑制とを目的とする。本発明のパワー半導体装置は、半導体素子（４，６）と、前記半導体素子（４，６）の上面に接合された端子（９）と、半導体素子（４，６）および端子（９）を収納する筐体（１４）と、筐体（１４）内で半導体素子（４，６）および端子（９）を封止する封止樹脂と、を備え、封止樹脂は、少なくとも半導体素子（４，６）を覆う第１の封止樹脂（２１）と、第１の封止樹脂（２１）の上方に形成された第２の封止樹脂（２２）と、を有し、半導体素子（４，６）の動作温度において、第１の封止樹脂（２１）は第２の封止樹脂（２２）よりも線膨張係数が小さく、第１の封止樹脂（２１）と端子（９）との線膨張係数の差は、第２の封止樹脂（２２）と端子（９）との線膨張係数の差よりも小さい。

Description

パワー半導体装置およびパワー半導体装置の製造方法
　本発明は、パワー半導体装置およびパワー半導体装置の製造方法に関する。
　従来のパワー半導体装置は、ベース板と、ベース板上に設けられたケースと、ケース内に充填された封止樹脂とを備えている。特許文献１には、Ａｌ合金からなるベース板の中にＣｕまたはＦｅを材料とする補強板を埋め込むことによって、ベース板の線膨張係数を小さくし、ベース板の裏面を凸とする反りを低減するパワー半導体装置が記載されている。
　しかし、特許文献１のパワー半導体装置では、ベース板に異なる材料を入れることによりコストが増加することと、異なる材料間の接触部で熱抵抗が悪化するという問題がある。
特開２００６－１００３２０号公報
　近年、パワー半導体装置に対し高温での動作保証が求められているが、封止樹脂と封止樹脂により封止されるインナー材との線膨張係数の差により、高温時に封止樹脂に応力が加わり、クラックが発生することがあった。
　封止樹脂の線膨張係数をインナー材の線膨張係数に近づけて応力を減らす方法として、封止樹脂の硬化温度を上げることが考えられる。しかし、封止樹脂の硬化温度を上げると硬化収縮量が大きくなるため、パワー半導体装置が大きく反ってしまうという問題がある。このように、封止樹脂のクラック抑制とパワー半導体装置の反り抑制とはトレードオフの関係にあった。
　本発明は上記のような問題点を解消するためになされたもので、パワー半導体装置において封止樹脂のクラック抑制と半導体装置の反り抑制とを目的とする。
　本発明のパワー半導体装置は、半導体素子と、半導体素子の上面に接合された端子と、半導体素子および端子を収納する筐体と、筐体内で半導体素子および端子を封止する封止樹脂と、を備える。封止樹脂は、少なくとも半導体素子を覆う第１の封止樹脂と、第１の封止樹脂の上方に形成された第２の封止樹脂と、を有する。半導体素子の動作温度において、第１の封止樹脂は第２の封止樹脂よりも線膨張係数が小さく、第１の封止樹脂と端子との線膨張係数の差は、第２の封止樹脂と端子との線膨張係数の差よりも小さい。
　本発明のパワー半導体装置では、封止樹脂を、少なくとも半導体素子を覆う第１の封止樹脂と、第１の封止樹脂の上方に形成された第２の封止樹脂とで構成する。そして、半導体素子の動作温度において、第１の封止樹脂は第２の封止樹脂よりも線膨張係数が小さく、第１の封止樹脂と端子との線膨張係数の差が、第２の封止樹脂と端子との線膨張係数の差よりも小さくなるよう設定する。半導体素子に影響を及ぼしやすい第１の封止樹脂では、端子の線膨張係数との差に起因する応力が第２の封止樹脂に比べて小さいため、この応力に起因するクラックを抑制することができる。また、第２の封止樹脂は第１の封止樹脂よりも線膨張係数が大きいため、硬化温度を低く設定できる。そのため、第２の封止樹脂の熱硬化時の収縮量を小さくし、パワー半導体装置の反りを抑制できる。
実施の形態１のパワー半導体装置の構成を示す断面図である。 比較例のパワー半導体装置の構成を示す断面図である。 封止樹脂の線膨張係数の温度依存性を封止樹脂の硬化温度別に示す図である。 実施の形態１のパワー半導体装置の製造工程を説明する図である。 実施の形態２のパワー半導体装置の構成を示す断面図である。 実施の形態３のパワー半導体装置の構成を示す断面図である。
　＜Ａ．実施の形態１＞
　＜Ａ－１．構成＞
　図１は、本実施の形態のパワー半導体装置１０１の構成を示す断面図である。パワー半導体装置１０１は、例えば家電用、産業用、自動車用、電車用などに広く用いられる。以下、図１を参照してパワー半導体装置１０１の構成を説明する。
　パワー半導体装置１０１は、絶縁パターン１、導電パターン２、ＩＧＢＴチップ４、ダイオードチップ６、インナーフレーム９，１２、主端子１０、アルミワイヤ１１、信号端子１３、インサートケース１４および放熱ピンフィン１６を備えている。絶縁パターン１の上面に２つの導電パターン２が形成され、これらの導電パターン２上には、はんだ３，５により半導体素子であるＩＧＢＴチップ４およびダイオードチップ６が、それぞれ接合している。
　インナーフレーム９は、はんだ７によりＩＧＢＴチップ４の上面に、はんだ８によりダイオードチップ６の上面に、それぞれ接合している。インナーフレーム９は例えば銅で形成され、主端子１０と同一部材である。
　ＩＧＢＴチップ４の上面にはアルミワイヤ１１が接合されている。アルミワイヤ１１の一端はＩＧＢＴチップ４の上面に接合され、他端はインナーフレーム１２に接合される。インナーフレーム１２は例えば銅で形成され、信号端子１３と同一部材である。
　絶縁パターン１の下面には放熱ピンフィン１６が接合されている。言い換えれば、絶縁パターン１は導電パターン２と放熱ピンフィン１６との間に設けられ、両者を絶縁している。絶縁パターン１、導電パターン２、ＩＧＢＴチップ４、ダイオードチップ６、インナーフレーム９，１２およびアルミワイヤ１１は、インサートケース１４に収容される。インサートケース１４は、パワー半導体装置の外形を形成する筐体であり、絶縁機能を有する。放熱ピンフィン１６は、インサートケース１４の下面から露出し、パワー半導体装置１０１の放熱に供する。
　インサートケース１４の内部には、第１の封止樹脂である封止樹脂２１と第２の封止樹脂である封止樹脂２２とが充填される。封止樹脂２１はインサートケース１４の内部の下側に充填され、ＩＧＢＴチップ４とダイオードチップ６を覆う。封止樹脂２２は、封止樹脂２１の上側、すなわちインサートケース１４の内部の上側に充填される。また、封止樹脂２１は、１２５℃以上２００℃以下の高温域において、封止樹脂２２よりも低い線膨張係数を有する。つまり、封止樹脂２１の線膨張係数をα１、封止樹脂２２の線膨張係数をα２とすると、上記の高温域においてα１＜α２の関係にある。
　図２は、本実施の形態の比較例のパワー半導体装置１０１Ｅの構成を示す断面図である。パワー半導体装置１０１Ｅでは、インサートケース１４の内部に封止樹脂２１，２２に代えて一種類の封止樹脂２３のみが充填されており、この点のみでパワー半導体装置１０１と異なる。
　図３は、封止樹脂の線膨張係数の温度依存性を、封止樹脂の硬化温度別に示したグラフである。縦軸が線膨張係数α（ｐｐｍ／℃）、横軸が温度（℃）を表している。そして、二点鎖線は硬化温度が１４０℃、実線は硬化温度が１６０℃、一点鎖線は硬化温度が１８０℃、破線は硬化温度が２００℃の封止樹脂の特性を示している。
　ところで、パワー半導体装置１０１Ｅにおいて封止樹脂２３に封止され、はんだ７，８によりＩＧＢＴチップ４およびダイオードチップ６と接合するインナーフレーム９には、一般的に銅が用いられる。銅は電気抵抗が低く、これによりパワー半導体装置１０１Ｅの通電時ロスを抑制するためである。２０℃以上２２７℃以下の温度範囲において、銅の線膨張係数αは１６．５－１８．３（ｐｐｍ／℃）であり、約１７（ｐｐｍ／℃）である。
　図３を参照して、硬化温度が１４０℃の封止樹脂２３の線膨張係数について検討する。パワー半導体装置の動作温度が１２５℃のとき、封止樹脂２３の線膨張係数は約１７－２０（ｐｐｍ／℃）となり、インナーフレーム９の線膨張係数の約１７（ｐｐｍ／℃）にほぼ等しくなる。従って、封止樹脂２３とインナーフレーム９との接触部で発生する応力は少ない。
　しかし、現在は半導体素子にＳｉＣを採用すること等から、パワー半導体装置には高温動作保証が求められており、動作保証範囲の上限を従来の１２５℃から１５０℃に２５℃上昇させることが求められている。そこで、パワー半導体装置１０１Ｅの動作温度が１５０℃のときについて検討すると、封止樹脂２３の線膨張係数は３０（ｐｐｍ／℃）以上となり、インナーフレーム９の線膨張係数の約１７（ｐｐｍ／℃）に対して１０（ｐｐｍ／℃）以上も大きい値となる。このように線膨張係数が異なる２つの部材が接触すると応力が発生し、結果として封止樹脂２３にクラックが発生し得る。
　この問題への対策として、封止樹脂２３の硬化温度を例えば１４０℃から１６０℃に上げることにより、封止樹脂２３とインナーフレーム９との線膨張係数の差を抑制することが有効である。パワー半導体装置１０１Ｅの動作温度が１５０℃のとき、硬化温度が１６０℃の封止樹脂２３の線膨張係数は１７（ｐｐｍ／℃）前後であり、インナーフレーム９の線膨張係数の約１７（ｐｐｍ／℃）とほぼ等しい。これにより、線膨張係数の差により発生する応力を抑制する事が可能となる。
　しかしながら、封止樹脂２３は一般的に熱硬化性樹脂を採用しているため、硬化温度と熱硬化時の収縮量とに正の相関がある。例えば、封止樹脂２３の硬化温度を１４０℃から１６０℃に高くすると、熱硬化時の収縮量も大きくなる。その結果、放熱ピンフィン１６などパワー半導体装置１０１Ｅの反り量が大きくなるという問題があった。
　図１に示したパワー半導体装置１０１は、線膨張係数の差に起因する封止樹脂のクラックと、封止樹脂の熱硬化時の収縮によるパワー半導体装置の反りとを同時に抑制するものである。
　まず、封止樹脂２１の硬化温度を封止樹脂２２より高くすることにより、１２５℃以上２００℃以下の高温域において封止樹脂２１の線膨張係数を約１７（ｐｐｍ／℃）とする。このように、封止樹脂２１の線膨張係数をインナーフレーム９に近づけることで、線膨張係数の差による封止樹脂２１のクラックを抑制できる。
　封止樹脂２１は封止樹脂２２よりも硬化温度が高いため、熱硬化時に封止樹脂２１は封止樹脂２２よりも大きく収縮する。しかし、封止樹脂２１はパワー半導体装置１０１の中央部より下側に設けられるため、封止樹脂２１の収縮によるパワー半導体装置１０１の反りを抑制することが可能である。なお、ここではインナーフレーム９の下面から上面への高さ方向の中央部を、パワー半導体装置１０１の中央部としている。
　封止樹脂２２はパワー半導体装置１０１の中央部より上側に設けられるが、封止樹脂２１よりも硬化温度が低いため、熱硬化時に封止樹脂２１ほど収縮しない。従って、パワー半導体装置１０１全体としての反りは抑制される。
　なお、封止樹脂２２は１２５℃以上２００℃以下の高温域における線膨張係数がインナーフレーム９よりも大きいため、線膨張係数の差に起因する応力が生じ得る。しかし、封止樹脂２２はＩＧＢＴチップ４およびダイオードチップ６を直接覆わないため、封止樹脂２２にクラックが生じたとしても、ＩＧＢＴチップ４およびダイオードチップ６に対する影響は少なく、パワー半導体装置１０１の信頼性は保たれる。
　＜Ａ－２．製造方法＞
　パワー半導体装置１０１の製造方法について説明する。
　まず、絶縁パターン１の上面に導電パターン２を形成し、導電パターン２上にはんだ３，５を介してＩＧＢＴチップ４とダイオードチップ６を接合する。
　次に、ＩＧＢＴチップ４の上面にはんだ７，８を介してインナーフレーム９を接合する。
　絶縁パターン１の下面には放熱ピンフィン１６を接合する。
　次に、放熱ピンフィン１６、絶縁パターン１、導電パターン２、ＩＧＢＴチップ４、ダイオードチップ６、およびインナーフレーム９の接合体を、インサートケース１４に収納する。このとき、放熱ピンフィン１６の下面はインサートケース１４から露出させる。
　次に、インサートケース１４に信号端子側のインナーフレーム１２を形成し、インナーフレーム１２とＩＧＢＴチップ４の上面をアルミワイヤ１１でボンディングする。
　その後、樹脂注入装置を用いてインサートケース１４内に封止樹脂２１をポッティングする。このとき、封止樹脂２１は少なくともＩＧＢＴチップ４およびダイオードチップ６を覆うように充填される。さらに、線膨張係数の差に起因する応力が特に加わるインナーフレーム９の下面のエッジを封止樹脂２１で覆うことにより、線膨張係数の差に起因する応力によるクラックの発生を効果的に抑制することができる。
　また、図１に示すように、アルミワイヤ１１が全て封止樹脂２１で覆われることが望ましい。仮に、アルミワイヤ１１が封止樹脂２１と封止樹脂２２に跨って封止されると、封止樹脂２１と封止樹脂２２の線膨張係数の差に起因する応力がアルミワイヤ１１に加わってしまう。しかし、封止樹脂２１がアルミワイヤ１１の全体を覆うことにより、上記の応力がアルミワイヤ１１に加わることを防ぐことができる。
　次に、加熱により封止樹脂２１を硬化させる。ここでの封止樹脂２１の硬化温度である第１の温度は、例えば１４０℃とし、後述する封止樹脂２２の硬化温度である第２の温度よりも低く設定する。
　インナーフレーム９に銅を用いている場合、封止樹脂２１の硬化時の熱により、インナーフレーム９の表層が酸化し、インサートケース１４との接着強度が低下してしまう。そこで、封止樹脂２１の硬化後、図４の矢印３１に示すように、封止樹脂２１およびインナーフレーム９の上面にＵＶ照射を行う。これにより、インナーフレーム９とインサートケース１４との接着強度が増加する他、封止樹脂２１，２２間の接着強度も向上する。その結果、高い信頼性を有するパワー半導体装置１０１を得ることができる。
　その後、樹脂注入装置を用いてインサートケース１４内に封止樹脂２２をポッティングし、封止樹脂２１の上方に封止樹脂２２を充填する。その後、加熱により封止樹脂２２を硬化させる。封止樹脂２２の硬化温度である第２の温度は、例えば１８０℃とし、封止樹脂２１の硬化温度である第１の温度よりも低く設定する。以上で、パワー半導体装置１０１が完成する。
　＜Ａ－３．効果＞
　以上で説明したように、実施の形態１のパワー半導体装置１０１は、半導体素子であるＩＧＢＴチップ４およびダイオードチップ６と、半導体素子の上面に接合された端子であるインナーフレーム９と、半導体素子およびインナーフレーム９を収納する筐体であるインサートケース１４と、インサートケース内で半導体素子およびインナーフレーム９を封止する封止樹脂と、を備える。そして、封止樹脂は、少なくとも半導体素子を覆う第１の封止樹脂である封止樹脂２１と、封止樹脂２１の上方に形成された第２の封止樹脂である封止樹脂２２とを有する。また、半導体素子の動作温度において、封止樹脂２１は封止樹脂２２よりも線膨張係数が小さく、封止樹脂２１とインナーフレーム９との線膨張係数の差は、封止樹脂２２とインナーフレーム９との線膨張係数の差よりも小さい。
　このように、半導体素子を覆う封止樹脂２１の線膨張係数をインナーフレーム９に近づけることによって、インナーフレーム９との線膨張係数の差に起因して封止樹脂２１に印加される応力を緩和することができる。そのため、封止樹脂２１のクラックが抑制される。また、封止樹脂２１の上方に、より線膨張係数の大きい封止樹脂２２を設けることで、封止樹脂２２の硬化温度を封止樹脂２１よりも小さくすることができる。従って、封止樹脂２２の熱硬化時の収縮量が封止樹脂２１よりも小さくなる。その結果、インサートケース１４内を封止樹脂２１のみで封止する場合と比較して、パワー半導体装置１０１の反りを２割抑制することが可能である。
　インナーフレーム９の半導体素子側の面である下面のエッジの周辺には、インナーフレーム９との線膨張係数の差に起因する応力が強く加わり、クラックが発生しやすい。そのため、パワー半導体装置１０１では、インナーフレーム９の下面のエッジを封止樹脂２１で覆うことにより、インナーフレーム９との線膨張係数の差に起因する応力による封止樹脂２１へのクラックを効果的に抑制することができる。
　パワー半導体装置１０１で、インナーフレーム９に銅を用いる場合。銅の線膨張係数は２０℃以上２２７℃以下の温度範囲において約１７（ｐｐｍ／℃）である。そこで、封止樹脂２１の硬化温度を１６０℃以上とすることにより、１５０℃の動作温度において、インナーフレーム９と近い線膨張係数を実現することができる。従って、線膨張係数の差に起因する封止樹脂２１へのクラックを抑制することができる。
　ＩＧＢＴチップ４またはダイオードチップ６といった半導体素子がＳｉＣ半導体素子である場合、パワー半導体装置１０１は高温動作保証を求められる。しかし、高温動作領域において、封止樹脂２１の線膨張係数を封止樹脂２２よりも小さくし、封止樹脂２１とインナーフレーム９との線膨張係数の差が、封止樹脂２２とインナーフレーム９との線膨張係数の差よりも小さくなるようにすることで、封止樹脂２１に印加される応力を緩和しつつ、パワー半導体装置１０１の全体の反りを抑制することができる。
　封止樹脂２１と封止樹脂２２には、同一の材料を用いても良い。同一の材料を用いることにより、樹脂注入装置を封止樹脂２１と封止樹脂２２で共用することができ、樹脂注入装置の導入費用、および配置エリアを削減することができる。従って、パワー半導体装置１０１の製造コストを低減することができる。
　実施の形態１のパワー半導体装置１０１の製造方法は、ＩＧＢＴチップ４およびダイオードチップ６の上面にインナーフレーム９を接合し、ＩＧＢＴチップ４、ダイオードチップ６およびインナーフレーム９をインサートケース１４で収納し、インナーフレーム９の上面が露出するようにインサートケース１４内のＩＧＢＴチップ４およびダイオードチップ６を封止樹脂２１で覆い、封止樹脂２１を第１の温度で硬化させ、インサートケース１４内で封止樹脂２１の上に封止樹脂２２を形成し、封止樹脂２２を第１の温度より低い第２の温度で硬化させる。
　また、実施の形態１のパワー半導体装置１０１の製造方法によれば、封止樹脂２１の硬化後、封止樹脂２２の形成前に、封止樹脂２１の上面およびインナーフレーム９の上面にＵＶを照射する。従って、インナーフレーム９とインサートケース１４との接着強度が増加する他、封止樹脂２１，２２間の接着強度が向上し、高い信頼性を有するパワー半導体装置１０１を得ることができる。
　＜Ｂ．実施の形態２＞
　＜Ｂ－１．構成＞
　図５は、実施の形態２のパワー半導体装置１０２の構成を示す断面図である。パワー半導体装置１０２において、インサートケース１４の内側面は凹部１５を有している。これ以外の点で、パワー半導体装置１０２の構成は実施の形態１のパワー半導体装置１０１と同様である。
　図５において、凹部１５は封止樹脂２１と封止樹脂２２の境界を跨ぐ位置に形成され、封止樹脂２１と封止樹脂２２の両方が、凹部１５に入り込んで形成される。これにより、封止樹脂２１と封止樹脂２２は、アンカー効果によりインサートケース１４と強固に接合される。その結果、高温時に封止樹脂２１，２２の線膨張係数差に起因する応力が発生した場合でも、封止樹脂２１，２２の界面が剥離することを抑制することができる。
　なお、封止樹脂２１と封止樹脂２２のいずれか一方が、凹部１５に入り込んで形成されていても良い。この場合でも、凹部１５に入り込んだ封止樹脂とインサートケース１４との接合が強固になるため、結果として、封止樹脂２１，２２の線膨張係数差に起因する応力により封止樹脂２１，２２の界面剥離を抑制することができる。
　＜Ｂ－２．効果＞
　実施の形態２のパワー半導体装置１０２は、筐体であるインサートケース１４の内側面に凹部１５を有する。そのため、凹部１５に入り込んだ封止樹脂とインサートケース１４との接合が強固になり、封止樹脂２１，２２の界面剥離が抑制される。
　また、この凹部１５に封止樹脂２１，２２の両方が入り込んで形成される場合には、封止樹脂２１，２２の両方にアンカー効果が働きインサートケース１４と強固に接合されるため、より一層封止樹脂２１，２２の界面剥離が抑制される。
　＜Ｃ．実施の形態３＞
　＜Ｃ－１．構成＞
　図６は、実施の形態３のパワー半導体装置１０３の構成を示す断面図である。パワー半導体装置１０３は、封止樹脂２１と封止樹脂２２の間にポリイミド層１７を有している。これ以外の点で、パワー半導体装置１０３の構成は実施の形態２のパワー半導体装置１０２と同様である。
　ポリイミド層１７は、硬化した封止樹脂２１，２２に比べてビッカース硬さが低いため、封止樹脂２１，２２間の応力を吸収する。そのため、封止樹脂２１とポリイミド層１７、およびポリイミド層１７と封止樹脂２２との間の密着性を高くすることができる。これにより、信頼性の高いパワー半導体装置１０３が得られる。
　＜Ｃ－２．効果＞
　実施の形態３のパワー半導体装置１０３は、封止樹脂２１と封止樹脂２２との間にポリイミド層１７を備えるため、封止樹脂２１とポリイミド層１７、およびポリイミド層１７と封止樹脂２２との間の密着性が高くなり、高い信頼性が得られる。
　なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。
　この発明は詳細に説明されたが、上記した説明は、すべての態様において、例示であって、この発明がそれに限定されるものではない。例示されていない無数の変形例が、この発明の範囲から外れることなく想定され得るものと解される。
　１　絶縁パターン、２　導電パターン、３，５，７，８　はんだ、４　ＩＧＢＴチップ、６　ダイオードチップ、９，１２　インナーフレーム、１０　主端子、１１　アルミワイヤ、１３　信号端子、１４　インサートケース、１５　凹部、１６　放熱ピンフィン、１７　ポリイミド層、２１，２２，２３　封止樹脂、１０１，１０１Ｅ，１０２，１０３　パワー半導体装置。

Claims (11)

  1. 　半導体素子（４，６）と、
    　前記半導体素子（４，６）の上面に接合された端子（９）と、
    　前記半導体素子（４，６）および前記端子（９）を収納する筐体（１４）と、
    　前記筐体（１４）内で前記半導体素子（４，６）および前記端子（９）を封止する封止樹脂と、
    を備え、
    　前記封止樹脂は、
    　少なくとも前記半導体素子（４，６）を覆う第１の封止樹脂（２１）と、
    　前記第１の封止樹脂（２１）の上方に形成された第２の封止樹脂（２２）と、を有し、
    　前記半導体素子（４，６）の動作温度において、前記第１の封止樹脂（２１）は前記第２の封止樹脂（２２）よりも線膨張係数が小さく、前記第１の封止樹脂（２１）と前記端子（９）との線膨張係数の差は、前記第２の封止樹脂（２２）と前記端子（９）との線膨張係数の差よりも小さい、
    パワー半導体装置（１０１）。
  2. 　前記第１の封止樹脂（２１）は、前記端子（９）の前記半導体素子（４，６）側のエッジを覆う、
    請求項１に記載のパワー半導体装置（１０１）。
  3. 　前記端子（９）は銅である、
    請求項１又は２に記載のパワー半導体装置（１０１）。
  4. 　前記半導体素子（４，６）はＳｉＣ半導体素子（４，６）である、
    請求項１から３のいずれか１項に記載のパワー半導体装置（１０１）。
  5. 　前記第１の封止樹脂（２１）と前記第２の封止樹脂（２２）は同一の材料からなる、
    請求項１から４のいずれか１項に記載のパワー半導体装置（１０１）。
  6. 　前記半導体素子（４，６）に接続されたアルミワイヤ（１１）をさらに備え、
    　前記アルミワイヤ（１１）は、前記第２の封止樹脂（２２）と接触せず、前記第１の封止樹脂（２１）により覆われる、
    請求項１から５のいずれか１項に記載のパワー半導体装置（１０１）。
  7. 　前記筐体（１４）の内側面は凹部（１５）を有する、
    請求項１から６のいずれか１項に記載のパワー半導体装置（１０２）。
  8. 　前記第１の封止樹脂（２１）および前記第２の封止樹脂（２２）は、前記凹部（１５）に入り込んで形成される、
    請求項７に記載のパワー半導体装置（１０２）。
  9. 　前記第１の封止樹脂（２１）と前記第２の封止樹脂（２２）との間にポリイミド層（１７）をさらに備える、
    請求項１から８のいずれか１項に記載のパワー半導体装置（１０３）。
  10. 　半導体素子（４，６）の上面に端子（９）を接合し、
    　前記半導体素子（４，６）および前記端子（９）を筐体（１４）で収納し、
    　前記端子（９）の上面が露出するように前記筐体（１４）内の前記半導体素子（４，６）を第１の封止樹脂（２１）で覆い、
    　前記第１の封止樹脂（２１）を第１の温度で硬化させ、
    　前記筐体（１４）内で前記第１の封止樹脂（２１）の上に第２の封止樹脂（２２）を形成し、
    　前記第２の封止樹脂（２２）を前記第１の温度より低い第２の温度で硬化させる、
    パワー半導体装置の製造方法。
  11. 　前記第１の封止樹脂（２１）の硬化後、前記第２の封止樹脂（２２）の形成前に、前記第１の封止樹脂（２１）および前記端子（９）の上面にＵＶを照射する、
    請求項１０に記載のパワー半導体装置の製造方法。
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