WO2018090622A1 - 芯片封装结构和方法 - Google Patents

芯片封装结构和方法 Download PDF

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Publication number
WO2018090622A1
WO2018090622A1 PCT/CN2017/089188 CN2017089188W WO2018090622A1 WO 2018090622 A1 WO2018090622 A1 WO 2018090622A1 CN 2017089188 W CN2017089188 W CN 2017089188W WO 2018090622 A1 WO2018090622 A1 WO 2018090622A1
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Prior art keywords
chip
rdl
substrate
target
package structure
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PCT/CN2017/089188
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English (en)
French (fr)
Inventor
符会利
李珩
张晓东
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华为技术有限公司
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Priority to EP17871770.8A priority Critical patent/EP3537476A4/en
Publication of WO2018090622A1 publication Critical patent/WO2018090622A1/zh
Priority to US16/415,587 priority patent/US20190273044A1/en

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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
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    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • This application relates to the field of chip packaging and, more particularly, to chip package structures and methods.
  • PCBs printed circuit boards
  • a package structure which uses a package on package (POP) technology to package a chip between two upper and lower substrates.
  • the lower substrate can be used to carry the target chip
  • the upper substrate can be used to carry the top chip.
  • the support of the upper and lower substrates can realize the stacking of the multilayer chip packaging structure in the vertical direction, thereby realizing the three-dimensional packaging.
  • the upper substrate may be an interposer substrate
  • the lower substrate may be a common organic substrate
  • the die and the substrate may be filled with a molding compound (MC)
  • the MC has a vertical interconnect system (Vertical Interconnects System, VIS) to achieve electrical interconnection between the upper and lower substrates.
  • VIS vertical Interconnect system
  • packaging the chip through the two-layer substrate makes the entire package structure (including the upper substrate, the MC, the target chip, and the lower substrate) thicker (for example, about 490 micrometers ( ⁇ m)), and does not satisfy the semiconductor package of the prior art.
  • the need to become smaller and thinner is also not conducive to the heat dissipation of the chip. Therefore, there is a need to provide a technique that can reduce the thickness of a package structure.
  • the present application provides a chip package structure and method for replacing the underlying substrate by a redistribution layer (RDL), thereby reducing the thickness of the package structure and increasing the density of the pins, while increasing the density of the interconnect channels and improving the top layer. Chip bandwidth.
  • RDL redistribution layer
  • a chip package structure including:
  • a target chip including an active surface and a back surface, the active surface of the target chip being connected to the first surface of the RDL;
  • the first surface of the substrate being opposite to a back surface of the target chip
  • An interconnecting channel is disposed around the target chip, one end of the interconnecting channel is connected to the first surface of the RDL, and the other end of the interconnecting channel is connected to the first surface of the substrate.
  • the chip package structure of the embodiment of the present application replaces the lower substrate by RDL, which reduces the limitation of the substrate processing process on the package structure compared with the prior art.
  • the processing process of the substrate makes the size (eg, thickness) of the substrate larger on the one hand, and the thickness of the entire chip package structure is limited by the thickness of the substrate processing, so that the chip package structure is not It is suitable for products with higher thickness requirements, and in the embodiment of the present application, the RDL is prepared by using a wafer-level process. In order to control the thickness of the RDL well, the effect of reducing the overall thickness is achieved, so that the chip package structure can be more applied to terminal devices with higher thickness requirements.
  • the processing technology of the substrate also makes the pitch for connecting the chip pins larger, that is, the pin density is small, and if the pin is to be increased, the area of the target chip (or the package area) needs to be increased, and
  • the RDL is prepared by using a wafer level process, and the distance between the pins can be made smaller, thereby increasing the pin density.
  • the interconnecting channel adopts a hot-pressed ball.
  • the hot-pressed ball is compressed by a high temperature, the solder ball expands laterally, which limits the minimum spacing of the VIS channel, thereby making the VIS channel The number is limited, thereby limiting the bandwidth of the top chip.
  • the limitation of the minimum spacing of the interconnecting channels is avoided, thereby increasing mutual Connect the density of the channel to increase the bandwidth of the top chip.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • the interconnecting channel comprises a first copper pillar pre-planted on a first surface of the substrate.
  • the interconnecting channel includes an abrasive solder ball and a first connector, one end of the abrasive solder ball being coupled to the RDL, the grinding The other end of the solder ball is connected to the first surface of the substrate through the first connecting member,
  • the abrasive solder ball includes a solder ball
  • the first connecting member includes any one of the following: a second copper post, a pre-coated solder paste or a solder ball.
  • the interconnecting channel includes a first copper pillar and a first connecting member, and one end of the first copper pillar is connected to the RDL, The other end of the first copper pillar is connected to the first surface of the substrate through the first connecting member,
  • the first connector includes a pre-coated solder paste or solder ball.
  • the thickness can be further reduced by using the above-listed vertical interconnection channels instead of the thermocompression bonding balls to achieve electrical interconnection.
  • the RDL includes a metal wiring
  • an active surface of the target chip includes a pad
  • the pad A metal wiring exposed on the first surface of the RDL is connected.
  • the chip package structure further includes a second connecting member, one end of the second connecting member is connected to the pad, and the other end of the second connecting member is exposed to the first surface of the RDL Metal wiring connection.
  • the second connecting member being connected to the first surface of the RDL, stress damage caused by grinding can be reduced.
  • the chip package structure further includes a molding compound MC, wherein the MC is filled in the RDL and the substrate And surrounding the target chip from around the target chip, the interconnection channel penetrating the MC in a first direction, the first direction being substantially perpendicular to a first surface of the RDL;
  • the MC is an abradable material. That is, the MC has a property of being grindable, and the thickness of the MC can be thinned by grinding, thereby further reducing the overall thickness of the chip package structure.
  • the first direction is substantially perpendicular to the first surface of the RDL, and it can be understood that the angle between the first direction and the first surface of the RDL is approximately 90 degrees. That is to say, the angle between the first direction and the first surface of the RDL may have a certain error range during the preparation process, but this is negligible or allowed.
  • the angle between the first direction and the RDL may be approximately 90 degrees, or may have a certain inclination angle (for example, less than 90 degrees), as long as the interconnection channel can pass through the first surface and the second surface of the MC.
  • the surface should fall within the scope of protection of this application.
  • the first surface of the substrate and the back surface of the target chip are coated with an adhesive material
  • the adhesive material includes at least one of the following: a hot-pressed non-conductive paste, a hot-pressed non-conductive film, a die-bonding film, or a silver paste.
  • the adhesive material may be applied between the back surface of the target chip and the first surface of the substrate, or may be simultaneously applied between the edge of the target chip, the first surface of the MC and the first surface of the substrate to interconnect
  • the channel is wrapped to achieve the effect of protecting the back side of the target chip and improving the reliability of the interconnect channel.
  • a three-dimensional chip package structure including the chip package structure in the first aspect or any one of the possible implementations of the first aspect.
  • the three-dimensional chip package structure of the embodiment of the present application can reduce the overall thickness of the three-dimensional chip package structure by using the chip package structure of the embodiment of the present application.
  • the three-dimensional chip package structure of the embodiment of the present application is not limited to the chip package structure of the embodiment of the present application.
  • the chip package structure of the embodiment of the present application can also be used for stacking three-dimensional with other forms of the chip package structure. Chip package structure.
  • a chip packaging method including:
  • a redistribution layer RDL is prepared, the RDL being connected to the other end of the interconnect channel, the first surface of the RDL being coupled to the active surface of the target chip.
  • the chip package structure of the embodiment of the present application reduces the limitation of the package structure by the substrate process by replacing the lower substrate by the RDL.
  • the overall thickness can be reduced, so that the chip package structure can be more applied to the thickness.
  • Higher terminal equipment is required; at the same time, the density of the pins can be increased; on the other hand, the number of vertical interconnection channels is increased under the condition of the same package area, thereby increasing the bandwidth of the top chip.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • the interconnecting channel includes a first copper pillar
  • the connecting the interconnecting channels on the first surface of the substrate comprises:
  • the first copper pillar is plated on a first surface of the substrate.
  • the thickness can be further reduced by using the first copper post instead of the thermocompression bonding ball to achieve electrical interconnection.
  • the chip packaging method before the preparing the RDL, the chip packaging method further includes:
  • the active surface of the target chip includes a pad, and the pad is pre-connected to one end of the second connecting member.
  • the other end of the second connecting member is exposed on the first surface of the MC, and the interconnecting passage penetrates the MC in a first direction, the first direction being substantially perpendicular to the first surface of the RDL.
  • the overall thickness of the chip package structure can be further reduced by grinding the MC.
  • the first direction is substantially perpendicular to the first surface of the RDL, and it can be understood that the angle between the first direction and the first surface of the RDL is approximately 90 degrees. That is to say, the angle between the first direction and the first surface of the RDL may have a certain error range during the preparation process, but this is negligible or allowed.
  • the angle between the first direction and the RDL may be approximately 90 degrees, or may have a certain inclination angle (for example, less than 90 degrees), as long as the interconnection channel can pass through the first surface and the second surface of the MC.
  • the surface should fall within the scope of protection of this application.
  • the chip packaging method further includes:
  • the first surface of the MC is ground according to a predetermined thickness of the chip package structure.
  • the RDL includes a metal wiring
  • an active surface of the target chip includes a pad
  • the pad is pre- Connecting one end of the second connecting component
  • the chip packaging method further includes:
  • the other end of the second connector is connected to a metal wiring exposed on the first surface of the RDL such that the metal wiring is connected to the active surface of the target chip.
  • the second connecting member being connected to the first surface of the RDL, stress damage caused by grinding can be reduced.
  • a chip packaging method including:
  • a substrate is placed on a back side of the target chip, and a first surface of the substrate is connected to the other end of the interconnecting channel.
  • the chip package structure of the embodiment of the present application reduces the limitation of the package structure by the substrate process by replacing the lower substrate by the RDL.
  • the overall thickness can be reduced, so that the chip package structure can be more applied to the thickness.
  • Higher terminal equipment is required; at the same time, the density of the pins can be increased; on the other hand, the number of vertical interconnection channels is increased under the condition of the same package area, thereby increasing the bandwidth of the top chip.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • the interconnection channel includes an abrasive solder ball and a first connector
  • the abrasive solder ball includes a solder ball
  • the first connector Includes: second copper post, pre-coated solder paste or solder balls,
  • the connecting the interconnecting channels on the first surface of the RDL includes:
  • the chip packaging method further includes:
  • the other end of the abrasive solder ball is connected to the first surface of the substrate through the first connecting member.
  • the interconnecting channel includes a first copper pillar and a first connecting member, and the first connecting component includes a pre-coated solder paste or a solder ball.
  • the connecting the interconnecting channels on the first surface of the RDL includes:
  • the chip packaging method further includes:
  • the other end of the first connecting member is connected to the first surface of the substrate.
  • the thickness can be further reduced by using the above-listed vertical interconnection channels instead of the thermocompression bonding balls to achieve electrical interconnection.
  • the RDL includes a metal wiring
  • an active surface of the target chip includes a pad
  • the pad is pre- Connecting one end of the second connecting component
  • the chip packaging method further includes:
  • the other end of the second connector is connected to a metal wiring exposed on the first surface of the RDL such that the metal wiring is connected to the active surface of the target chip.
  • the second connecting member being connected to the first surface of the RDL, stress damage caused by grinding can be reduced.
  • the chip packaging method before the substrate is disposed on the back side of the target chip, the chip packaging method further includes:
  • An interconnect channel extends through the MC in a first direction that is substantially perpendicular to a first surface of the RDL.
  • the overall thickness of the chip package structure can be further reduced by grinding the MC.
  • the chip packaging method further includes:
  • a second surface of the MC is ground according to a predetermined thickness of the chip package structure.
  • a chip packaging method including:
  • a redistribution layer RDL on an active surface of the target chip, a first surface of the RDL being connected to another end of the interconnect channel, and a first surface of the RDL and an active source of the target chip The surface is at least partially in contact.
  • the chip package structure of the embodiment of the present application reduces the limitation of the package structure by the substrate process by replacing the lower substrate by the RDL.
  • the overall thickness can be reduced, so that the chip package structure can be more applied to the thickness.
  • Higher terminal equipment is required; at the same time, the density of the pins can be increased; on the other hand, the number of vertical interconnection channels is increased under the condition of the same package area, thereby increasing the bandwidth of the top chip.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • the interconnection channel includes an abrasive solder ball and a first connector
  • the abrasive solder ball includes a solder ball
  • the first connector Includes: second copper pillar, pre-coated tin Paste or solder ball
  • the chip packaging method further includes:
  • the other end of the abrasive solder ball is connected to the first surface of the RDL.
  • the interconnecting channel includes a first copper pillar and a first connecting member, and the first connecting component includes a pre-coated solder paste or a solder ball.
  • the chip packaging method further includes:
  • the other end of the first copper pillar is connected to the first surface of the RDL.
  • the thickness can be further reduced by using the above-listed vertical interconnection channels instead of the thermocompression bonding balls to achieve electrical interconnection.
  • the RDL includes a metal wiring
  • an active surface of the target chip includes a pad
  • the chip packaging method also includes:
  • the pad is soldered to a metal wiring exposed on the first surface of the RDL such that the metal wiring is connected to an active surface of the target chip.
  • the chip packaging method of the embodiment of the present application can directly connect the pads of the substrate to the surface of the RDL without using a connector, thereby reducing the use of the connector and simplifying the process.
  • the chip packaging method before the substrate is disposed on the back side of the target chip, the chip packaging method further includes:
  • the interconnection channel penetrating in the first direction In the MC the first direction is perpendicular to a first surface of the RDL.
  • the chip packaging method further includes:
  • a first surface of the MC is ground according to a predetermined thickness of the chip package structure, and a first surface of the MC is opposite to a first surface of the substrate.
  • the first copper pillar has a diameter greater than or equal to 100 micrometers ⁇ m and a height greater than or equal to 100 ⁇ m.
  • the second copper pillar has a diameter of less than 100 ⁇ m
  • the second copper pillar has a height of less than 100 ⁇ m
  • the solder ball has a diameter greater than 40 ⁇ m.
  • the diameter of the solder ball is greater than 40 ⁇ m
  • the diameter of the first copper pillar is greater than or equal to 100 micrometers ⁇ m
  • the height is greater than or equal to 100 ⁇ m.
  • the chip package structure and method of the embodiment of the present application replaces the underlying substrate by a redistribution layer to reduce the thickness of the package structure and increase the density of the pin, and at the same time increase the density of the interconnect channel and increase the bandwidth of the top chip.
  • FIG. 1 is a schematic diagram of a scenario of a chip package structure suitable for use in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a chip package structure according to an embodiment of the present application.
  • 3 and 4 are schematic views of the interconnection channel and the substrate connected by the first connecting member.
  • FIG. 5 is a schematic structural diagram of a chip package structure according to an embodiment of the present application.
  • FIG. 6 to FIG. 12 are schematic diagrams of packaging a chip package structure according to an embodiment of the present application by a chip packaging method Figure.
  • FIG. 13 is a schematic structural diagram of a chip package structure according to another embodiment of the present application.
  • 14 to 25 are schematic diagrams of packaging a chip package structure of another embodiment of the present application by another chip packaging method.
  • FIG. 26 is a schematic structural diagram of a chip package structure according to still another embodiment of the present application.
  • 27 to 30 are schematic diagrams of packaging a chip package structure according to still another embodiment of the present application by another chip packaging method.
  • FIG. 31 is a schematic structural diagram of a chip package structure according to still another embodiment of the present application.
  • FIG. 32 is a schematic structural diagram of a three-dimensional chip package structure according to an embodiment of the present application.
  • FIG. 33 is a schematic flowchart of a chip packaging method according to an embodiment of the present application.
  • FIG. 34 is a schematic flowchart of a chip packaging method according to another embodiment of the present application.
  • FIG. 35 is a schematic flowchart of a chip packaging method according to still another embodiment of the present application.
  • FIG. 1 is a schematic diagram of a scenario of a chip package structure suitable for use in an embodiment of the present application.
  • the chip package structure 12 can be connected to the top chip 11 through a connector 14 (for example, a solder ball, in particular, a solder ball, etc.), and the chip package structure 12 can be connected.
  • a piece 15 (for example, a solder ball, specifically may be a solder ball, etc.) is connected to a lower printed circuit board (PCB) 13.
  • the top layer chip 11 may be a structure or a package such as a memory, an integrated passive device (IPD), a micro-electro-mechanical system (MEMS), an interposer, or the like. It should be understood that the top-level chips listed herein are merely exemplary descriptions, which are not limited in this application.
  • the height, diameter or thickness of various structural members in the embodiments of the present application shown below, and the overall thickness of the chip package structure are merely illustrative, and are compared by exemplary thicknesses to embody the present application.
  • the chip package structure of the embodiment has a thinning effect on the overall thickness, and should not be construed as limiting the application. As long as the use of RDL instead of one of the two substrate layers for chip packaging is used, it should fall within the scope of the present application.
  • FIG. 2 is a schematic structural diagram of a chip package structure 20 according to an embodiment of the present application.
  • the chip package structure 20 includes a substrate 31, a target chip 37, an interconnection channel 33, and a redistribution layer RDL 34.
  • FIG. 2 is only for facilitating understanding of the connection relationship between the chip package structure 20 and the outside, and the connector (corresponding to the connector 14 and the connector 15 in FIG. 1) is shown in the figure.
  • this application should not be construed as limiting, and the application should not be limited thereto.
  • the target chip has been prepared with an aluminum pad (AP, hereinafter referred to as pad, as shown in FIG. 2) 36 on its surface before leaving the factory (ie, before entering the packaging factory).
  • the pad is used for packaging to fix the target chip to other structures (for example, the RDL shown in the embodiment of the present application) and has a conductive effect.
  • the target chip may include an active surface (ie, a surface on which the surface is prepared with an AP) and a back surface.
  • the active side and the back side are substantially parallel.
  • the active surface and the back surface are substantially parallel, and it can be understood that the angle between the active surface and the back surface is approximately 0 degrees. That is to say, the angle between the active surface and the back surface may have a certain error range during the preparation process, but this is negligible or, to be permissible.
  • an active surface can be understood as a component (or circuit) that internally contains a power source to achieve the intended function, and is passive relative to the active, that is, does not require a power supply.
  • the active surface of the target chip is prepared with an AP for realizing electrical connection with the outside world (specifically, with metal wiring in the RDL).
  • the surface opposite to the active surface of the target chip is referred to as the first surface of the RDL
  • the surface opposite to the back surface of the target chip is referred to as the first surface of the substrate.
  • the active surface of the target chip is connected to the first surface of the RDL.
  • the interconnecting channel is located around the target chip, and one end is directly or indirectly connected to the first surface of the RDL, and the other end is directly or indirectly connected to the first surface of the substrate for realizing electrical interconnection between the RDL and the substrate. It should be noted that the number of interconnection channels in the present application is not particularly limited.
  • the RDL may include a dielectric layer and a metal wiring
  • the metal wiring may be one or more layers distributed in the dielectric layer and exposed on the first surface and the second surface of the dielectric layer, as shown in FIG. 2 .
  • the solid black line part is shown.
  • the number of layers of the metal wiring is not particularly limited as long as it can be exposed on the first surface and the second surface of the dielectric layer to achieve connection with the external conductive structure, and should fall within the protection scope of the present application.
  • the first surface of the RDL is on the same plane as the first surface of the dielectric layer
  • the second surface of the RDL is on the same plane as the second surface of the dielectric layer. That is, the first surface exposed to the dielectric layer can be understood as being exposed on the first surface of the RDL.
  • the description of the same or similar cases will be omitted hereinafter.
  • the target chip may be located above the first surface of the RDL, in direct contact with the metal wiring exposed on the first surface of the RDL or by a connector (for example, the connector 35 described later).
  • a connector for example, the connector 35 described later.
  • the case where the target chip is in contact with the metal wiring in the RDL through the connection member is not shown in FIG. 2, and will be described in detail later in conjunction with other embodiments (for example, the package method 1 and the package method 2).
  • the active face of the target chip includes a pad 36, which can be understood as a pin to which the target chip is connected to the outside. At least a portion of the pins of the target chip may be interconnected with metal wiring exposed on the first surface of the RDL, and part of the pins of the target chip may also be extracted to the chip by a Fan Out Wafer Level Package (FOWLP) technology.
  • the periphery is connected to the metal wiring exposed on the first surface of the RDL.
  • the contact point of the target chip with the RDL may be the metal wiring of the first surface of the RDL.
  • the RDL may further include a second surface (generally, the second surface of the RDL is parallel to the first surface of the RDL), and the metal wiring exposed on the second surface of the RDL may be connected through the connector Electrical interconnection between the PCBs is achieved.
  • the substrate may also include a second surface (typically, the second surface of the substrate is parallel to the first surface of the substrate), and the second surface of the substrate may be electrically interconnected with the connected top chip by solder balls .
  • the active surface and the back surface of the target chip are parallel to each other, and the first surface of the RDL opposite to the active surface of the target chip is parallel to the active surface, and the surface area of the first surface of the RDL is greater than or equal to the surface.
  • a surface area of the active surface; a first surface of the substrate opposite the back surface of the target chip and a back surface of the target chip are parallel to each other, and a surface area of the first surface of the substrate is greater than or equal to a surface area of the back surface.
  • the target chip is wrapped in the middle by the RDL and the substrate, and if the target chip is regarded as a two-dimensional plane, for example, it is referred to as a first plane (which may correspond to the YOZ plane in FIG. 2).
  • the projection of the target chip in the first plane falls within the range of projection of the RDL in the first plane, and the projection of the target chip in the first plane falls within the range of projection of the substrate in the first plane. That is, both the substrate and the RDL are distributed to completely cover the target chip, either from the top down or from the bottom up.
  • the first plane is parallel to the horizontal plane, and the first direction is a direction perpendicular to the horizontal plane (ie, the vertical direction), and the chip packaging process may be based on the horizontal plane.
  • Different layers such as the RDL, target chip, substrate, etc. described above
  • the vertical direction is stacked in the vertical direction to obtain a chip package structure (for example, as shown in FIG. 2).
  • this application should not be construed as limiting, as long as the contact faces between the layers are parallel to the first plane, and the layers are stacked from bottom to top along the first direction, and all fall within the scope of the present application.
  • the first plane is parallel to the horizontal plane, and the first direction is a direction perpendicular to the horizontal plane.
  • the description of the same or similar cases will be omitted hereinafter.
  • interconnect channels are used to implement electrical interconnections between layers.
  • the interconnecting channel is located around the target chip, one end is connected to the first surface of the substrate, and the other end is connected to the first surface of the RDL. More specifically, pads are prepared on the first surface and the second surface of the substrate, one end of which is connected to the pads of the first surface of the substrate. The other end of the interconnection channel is connected to the metal wiring exposed on the first surface of the RDL, that is, the interconnection of the interconnection channel and the pin of the target chip is realized by the metal wiring.
  • the interconnecting channel is in turn connected to the substrate, and the conductive structure in the substrate (ie, the solid black portion perpendicular to the substrate shown in FIG. 2) is connected to the connecting member connected to the second surface of the substrate, thereby Connected to the top chip above the substrate (wherein the horizontal black solid line on the second surface of the substrate can be understood as the point of contact of the connector with the second surface of the substrate). That is, electrical interconnection of the target chip and the top chip is achieved.
  • the metal wiring exposed on the second surface of the RDL is connected to the connecting member, and then connected to the underlying PCB to realize electrical interconnection between the target chip, the top chip and the PCB.
  • the interconnect channels enable electrical interconnection between the layers.
  • the thickness of the substrate may be 170 ⁇ m to 560 ⁇ m, and the thickness of the RDL may be 30 to 50 ⁇ m, whereby the thickness of the entire chip package structure can be greatly reduced by replacing the substrate by RDL. Therefore, the chip package structure of the embodiment of the present application replaces the lower substrate by RDL, thereby reducing the limitation of the substrate structure on the package structure.
  • the overall thickness can be reduced, so that the chip package structure can be more applied to terminal devices with higher thickness requirements; at the same time, the pin density can be increased; on the other hand, when the package area is constant, the increase is made.
  • the number of vertical interconnect channels increases the bandwidth.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • the chip package structure further includes a molding compound (MC) 32.
  • MC molding compound
  • the MC is filled between the substrate and the RDL, and surrounds the target chip from the periphery of the target chip to isolate the target chip from the outside, thereby preventing moisture, dust, and buffer, and avoiding between the target chip and the substrate. Relative movement.
  • the MC can surround the side and back of the target chip, or surround the side of the target chip to reduce the influence of the outside on the target chip.
  • an adhesive material 38 may be coated between the back surface of the target chip and the first surface of the substrate to fix the target chip on the first surface of the substrate.
  • the adhesive material 38 may include at least one of the following: Thermal Compression Non-Conductive Paste (TCNCP), Thermal Compression Non-Conductive Film (TCNCF), Die Attach Film (DAF) or Silver (Epoxy).
  • TCNCP Thermal Compression Non-Conductive Paste
  • TNCF Thermal Compression Non-Conductive Film
  • DAF Die Attach Film
  • Silver Epoxy
  • the adhesive material may be any one of the above examples, or a combination of any of the above examples.
  • the adherent material may be uniformly coated on all or a portion of the first surface of the MC.
  • the DAF may be attached to the back surface of the target chip while the first surface of the MC (ie, the surface opposite to the first surface of the substrate) corresponds to the periphery of the target chip. Paint Cover other adhesive materials, such as silver glue.
  • the adhesive material can be deformed by hot pressing to evenly wrap the interconnecting channels (see FIGS. 8 and 22 for details), thereby protecting the back surface of the target chip and improving the reliability of the interconnecting channel. effect.
  • the adhesive material in the case where the adhesive material is TCNCP/TCNCF, the adhesive material can be deformed by hot pressing when the substrate is soldered to uniformly wrap the interconnecting channel (refer to FIG. 8 and FIG. 22), thereby achieving the effect of protecting the back side of the target chip and improving the reliability of the interconnect channel.
  • the adhesive materials of the above examples are merely illustrative and should not be construed as limiting the application, and the application should not be limited thereto.
  • the adhesive material can also be other materials that can achieve the same function.
  • MC is prepared from an abradable material.
  • MC can be made from a resin material, and some hard-filled particles (eg, silica) can be added to improve its properties. That is, the MC can be thinned by grinding.
  • the MC may be ground according to a preset thickness of the chip package structure.
  • the thickness of the chip package structure can be determined, and the effect of further reducing the chip package structure can be achieved by grinding the MC.
  • the interconnection channel penetrates through the MC, and both ends of the interconnection channel are respectively exposed on the two surfaces of the MC opposite to the substrate and the RDL.
  • the filling height of the MC in the first direction may be higher than the highest point of the surface of the target chip and higher than the interconnecting channel (it may be understood that the height of the interconnecting channel in the first direction is greater than or equal to the target chip). Height in the first direction).
  • the filling height of the MC may be higher than the highest point of the surface of the target chip when the MC is filled.
  • the highest point of the surface of the target chip can be understood as: a point at a higher position in the active surface and the back surface of the target chip with reference to the first plane.
  • the highest point of the surface of the target chip can be understood as a surface at a higher position in the upper surface and the lower surface of the target chip when the MC is filled.
  • the highest point of the surface of the target chip when filling MC refers to a point at a higher position in the active surface or the back surface of the target chip during the special period of filling MC, but this does not mean that the point is always The highest point on the surface of the target chip.
  • the thickness of the MC may be adjusted according to a preset thickness of the chip package structure.
  • the MC can be thinned by grinding. Specifically, after the MC is filled, the MC may be ground as needed, so that the interconnection channel is exposed on the surface of the MC, or the interconnect channel and the back surface of the target chip are simultaneously exposed on the surface of the MC (corresponding to the following description). Encapsulation methods two and three), or, such that the interconnect channel and the back side of the target chip are simultaneously exposed on the surface of the MC (corresponding to the packaging method one described later), while making the exposed surface of the MC flat and The effect of thinning the overall thickness of the chip package structure.
  • the thickness of the MC is about 100 ⁇ m to 200 ⁇ m.
  • the manner of grinding the MC shown in the embodiments of the present application is merely illustrative, and should not be construed as limiting the application.
  • the interconnecting channel may be exposed to the MC opening by means of laser opening, or the interconnecting channel may be exposed to the MC by grinding and re-lasering as needed.
  • the laser drilling method it is possible to see whether it is necessary to grind first according to the situation. If the MC covers the back of the target chip, it can be ground to the back of the target chip, and then the laser is used to open the MC. Open the hole.
  • the first copper post or abrasive ball used in the interconnecting channel can be of a smaller size, for example, using a smaller first copper post or a smaller diameter abrasive ball. This method can reduce the contamination of the target chip during the grinding process.
  • the interconnecting channel extends through the MC in a first direction that is substantially perpendicular to the first surface of the RDL.
  • the interconnecting channel may extend through the MC perpendicular to the first plane, that is, may correspond to the OX direction in FIG. 2 (referred to as the first direction for convenience of explanation).
  • an interconnection channel vertically penetrating through the MC may be referred to as a vertical interconnection channel or a Vertical Interconnects System (VIS).
  • VIS Vertical Interconnects System
  • the first direction is substantially perpendicular to the first surface of the RDL, and it can be understood that the angle between the first direction and the first surface of the RDL is approximately 90 degrees. That is to say, the angle between the first direction and the first surface of the RDL may have a certain error range during the preparation process, but this is negligible or allowed.
  • the interconnecting channel can include a first copper post; or the interconnecting channel can include a first copper post and a first connector, or an abrasive solder ball and a first connector.
  • the thickness of the chip package structure can be further reduced.
  • the first copper pillar may be pre-plated on the first surface of the substrate.
  • the first copper pillar has a diameter greater than or equal to 100 micrometers ⁇ m and a height greater than or equal to 100 ⁇ m.
  • the first connecting member may be any one of the following: pre-coated solder paste or solder ball.
  • the diameter d 1 of the solder ball satisfies 40 ⁇ m ⁇ d 1 ⁇ 100 ⁇ m, and the solder ball may be: for example, Solder ball, solder bump, Cu-core solder ball (CCSB) or Controlled Collapse Chip Connection (C4), etc.
  • the specific material or form of the solder ball is not limited.
  • the diameter of the first copper pillar is greater than or equal to 100 micrometers ⁇ m, and the height is greater than or equal to 100 ⁇ m, and the height of the pre-coated solder paste is about 20 ⁇ m.
  • the height of the first connecting member and the first copper post can be selected according to actual needs. The calculation shows that the thickness of the chip package structure can be as small as 320 ⁇ m.
  • the interconnecting channel is an abrasive solder ball and a first connecting member (as shown in FIGS. 3 and 4), one end of the abrasive solder ball may be connected to the metal wiring exposed on the first surface of the RDL, and the other end may pass the first The connector is attached to the first surface of the substrate.
  • the abrasive solder ball may be a solder ball having a diameter of 200 ⁇ m, and after grinding, a hemisphere having a height of only 100 ⁇ m may be obtained.
  • the first connecting member may be any one of the following: a second copper pillar, a pre-coated solder paste or a solder ball.
  • the second copper pillar may have a diameter of less than 100 ⁇ m and a height of less than 100 ⁇ m.
  • the second copper pillar may have a diameter of 40 ⁇ m and a height of 5 ⁇ m to 50 ⁇ m.
  • the diameter of the solder ball may be greater than or equal to 40 ⁇ m, and the height of the pre-coated solder paste may be 20 ⁇ m. It can be seen from the calculation that the thickness of the chip package structure can be as small as 305 ⁇ m (the first connector is a second copper pillar having a height of 5 ⁇ m) or 320 ⁇ m (the first connector is a pre-coated solder paste having a height of 20 ⁇ m).
  • the thickness can be reduced without increasing the occupation of the package area compared to the prior art compression solder ball.
  • the compression solder ball is reduced in thickness by a hot pressing method, and the hot pressing causes the size of the solder ball to decrease in the longitudinal direction (ie, the first direction) while being horizontal.
  • the size toward (ie, the direction perpendicular to the first direction) increases.
  • the embodiment of the present application uses the grinding technique to grind the solder ball, and does not affect the lateral dimension while reducing the longitudinal dimension. Therefore, it has a larger advantage than the compression solder balls in the prior art.
  • the vertical interconnect channel can also be a Printed Circuit Board (PCB Bar) or a Through Silicon Via (TSV) Module.
  • PCB Bar is a module with PCB through holes made by PCB technology.
  • the TSV Module uses TSV technology to fabricate TSVs on wafers and then diced the wafers into small modules with TSVs.
  • Each PCB Bar or TSV Module contains one or more vertical interconnect channels.
  • the PCB Bar or TSV Module can be integrated with the target chip through fan-out wafer level packaging technology through wafer reconstitution and wafer wiring, or integrated in the interconnection area between the peripheral and target chips. PCB Bar or TSV Module.
  • the chip package structure of the embodiment of the present invention replaces the lower substrate by the RDL, which reduces the limitation of the substrate processing process on the package structure, thereby achieving the effect of reducing the overall thickness, so that the chip package structure It can be more applied to terminal devices with higher thickness requirements.
  • the pin density is increased.
  • the vertical interconnect channel used in the embodiments of the present application can avoid the limitation of the minimum pitch of the interconnect channel, thereby increasing the density of the interconnect channel and thereby increasing the bandwidth of the top chip.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • the chip package structure according to the embodiment of the present application is described in detail above with reference to FIG. 2 .
  • the structure shown in FIG. 2 is only one possible implementation of the embodiment of the present application, and should not be construed as limiting the application.
  • the chip package structure can replace two substrate layers with two RDLs, and the overall thickness of the structure can be reduced by using RDL, and the pin density can be increased; or the chip package structure can also replace the upper substrate with RDL while retaining The lower substrate can also achieve the effect of reducing the overall thickness of the structure.
  • chip package structure of the embodiment of the present application is described in detail in conjunction with the chip package method, including the package method, the package method 2, and the package method 3.
  • the chip package method shown below is only A possible implementation of the chip package structure of the embodiment of the present invention is not limited to the present application, and the embodiment of the present application is not limited thereto.
  • FIG. 5 shows a schematic structural diagram of a chip package structure 30 in accordance with an embodiment of the present application.
  • the chip package structure 30 includes a substrate 31, an MC 32, a vertical interconnect via 33, an RDL 34, a target chip 37, and an adhesion material 38.
  • the pad 36 of the target chip 37 is connected to the metal wiring exposed on the first surface of the RDL 34 (or more specifically, the dielectric layer) through the second connection member 35, specifically, the pad 36 of the target chip 37.
  • Electrical connection to the metal wiring exposed on the first surface of the RDL 34 may be through the second connector 35 to achieve electrical interconnection with the pins of the target chip.
  • the chip package structure 30 will be described in detail below with reference to FIGS. 6 through 12.
  • 6 through 12 illustrate schematic diagrams of packaging a chip package structure 30 of an embodiment of the present application by a chip packaging method.
  • step 1a is performed: as shown in FIG. 6, the substrate 31 is mounted on a carrier 91.
  • the substrate 31 is mounted on a carrier 91.
  • multiple substrates can be mounted on the carrier at a predetermined pitch.
  • the carrier may be glass, ceramic, metal or other material having a similar function and compatible wafer-level packaging process.
  • the carrier film can be selectively coated with a structural film or a functional film, for example, an adhesive layer, a sacrificial layer, a buffer layer, and a dielectric film. (dielectric layer) and so on.
  • the adhesive layer film and the sacrificial layer film may both be UV-curable (Ultra-Violet, UV) glue, light-to-heat conversion (LTHC) film, or have similar functions and are wafer level. Process compatible materials.
  • the dielectric layer film may be polyimide (PI), polybenzoxazole (PBO), Benzocyclobutene (BCB), an epoxy resin supplied by Ajinomoto Co., Ltd. Ajinomoto Buildup Film (ABF), Solder Resist Film (SR), or other materials that have similar functions and are compatible with wafer-level processes.
  • the carrier board and the substrate have different functions, and the carrier board can be understood as a carrier that plays a supporting role in the chip packaging process, which does not belong to the chip package structure, is only used for the packaging process, and is completed correspondingly.
  • the carrier can be removed after the step.
  • a substrate can be understood as part of the chip package structure in which circuits are distributed for electrical interconnection. For the sake of brevity, the description of the same or similar parts will be omitted hereinafter.
  • the vertical interconnection channel 33 is pre-implanted in the substrate 31.
  • the vertical interconnection channel may be previously connected to the first surface pad of the substrate 31 by electroplating.
  • the substrate or called interposer
  • the interconnect channel can be a first copper pillar. It should be understood that the use of a copper post as a vertical interconnect channel is only one possible implementation, and the vertical interconnect channel can also be aluminum or other structure having equivalent electrical interconnect functionality.
  • first surface and the second surface of the substrate 31 may be provided with pads, and the substrate may be connected to the carrier through the pads of the second surface, and connected to the vertical interconnection channel through the pads of the first surface.
  • the pads may be disposed on the first surface and the second surface of the substrate in the form of a surrounding array or an array of faces.
  • step 1b is performed: as shown in FIGS. 7 and 8, an adhesive material 38 is applied on the first surface of the substrate 31, and the target chip 37 is attached to the first surface of the substrate 31.
  • the target chip By coating the adhesive material, the target chip can be fixed on the substrate while being able to perform stress buffering.
  • FIG. 7 shows schematic views in the case where different adhesive materials are selected.
  • the adhesive material 38 shown in FIG. 7 may be silver glue, DAF glue, PI, or the like. That is, an adhesive material is applied to the back surface of the target chip before the substrate 31 is attached.
  • the adhesive material shown in Fig. 8 may be TCNCP/TCNCF. That is, before the substrate 31 is attached, the adhesion material 38 may be applied on the first surface of the substrate 31 or the surface of the MD. When the substrate 31 is soldered, the TCNCP/TCNCF may be used to protect the back surface of the chip and wrap the connection by hot pressing.
  • a member 33 (shown in FIG. 8) serves to improve the reliability of the connector 33.
  • the target chip 33 is completely attached to the substrate 31.
  • the projection of the target chip in the first plane falls within the projection range of the substrate in the first plane.
  • the active surface of the target chip 37 includes a plurality of pads 36, which may be uniformly or unevenly distributed on the active surface of the target chip.
  • the pad can be understood as the pin of the target chip, which realizes the electrical interconnection between the target chip and the outside world.
  • the pad 36 may solder a second connector 35 for connecting the pad 36 to the metal wiring in the RDL 34.
  • the second connecting member may be: C4, a third copper pillar, a Cu post or other structure having an equivalent electrical interconnection function.
  • the second connector can be prepared by ball placement, electroplating, printing, or the like.
  • the size (including diameter and height) of the third copper column listed here is selected above.
  • the second copper pillar size mentioned may be selected in the same range. However, this should not be construed as limiting, that is, the size of the second copper pillar and the size of the second copper pillar may be the same or different.
  • a buffer material may be filled between each of the second connectors.
  • the buffer material may be an underfill (UF) or a dielectric layer material having a buffering effect.
  • the buffer material is a dielectric layer material
  • the dielectric layer material can be selected by referring to the selection range of the dielectric layer film coated on the carrier described above.
  • single or multiple target chips can be integrated.
  • a single or multiple target chips (or original wafers) may be attached to the first surface of the substrate.
  • the plurality of chips may be chips prepared by different sizes, different types, and different processes, and the specific size may be determined according to product requirements and process processes, and the chips may be ground and reduced as needed. thin. Therefore, the type, size, and process of the target chip are not particularly limited in the present application.
  • the vertical interconnect channels may be distributed in the MC and located at the periphery of the target chip; when the number of target chips is multiple, the vertical interconnect channels may be distributed In the MC, and located in an area between adjacent target chips or a peripheral area of the target chip.
  • step 1c is performed: as shown in FIG. 9, the MC 32 is filled, and the first surface of the MC 32 is ground.
  • the MC 32 is filled on the first surface of the substrate 31 and surrounds the side surface of the target chip 37 so that the back surface and the side surface of the target chip are both isolated from the outside, and the active surface is bonded to the RDL through the step 1d described later.
  • the filling height of the MC is at least higher than the active surface of the target chip (ie, the upper surface shown in FIG. 8).
  • the MC can then be ground as needed to thin the MC such that the second connector 35 and the vertical interconnect channel 33 can be exposed from the MC.
  • Grinding the MC can flatten the first surface of the MC while further reducing the thickness of the chip package structure.
  • the MC may be ground according to a preset thickness of the chip package structure.
  • the thickness of the chip package structure can be determined, and the effect of further reducing the chip package structure can be achieved by grinding the MC.
  • the second connecting member 35 not only functions to connect the pads of the target chip and the RDL, but also protects the target chip during the process of grinding the MC, and reduces stress damage to the target chip during the grinding process.
  • a buffer material eg, UF may be filled between the second connectors 35 to increase the strength and reliability of the structure.
  • step 1d is performed: as shown in FIG. 10, the RDL 34 is created.
  • the surface of the structure obtained in step 1c is coated with a dielectric layer, and a metal wiring is prepared inside and on the surface of the dielectric layer.
  • the selection of the dielectric layer material can be referred to the selection range of the dielectric layer film coated on the carrier board described above.
  • RDL can be prepared by processes such as coating, exposure, development, curing, sputtering, electroplating, etching, and the like.
  • the material of the metal wiring may be a conductive material such as copper or aluminum.
  • the RDL may be a single layer or a plurality of wiring layers.
  • the RDL 34 covers the target chip 33 and the MC 32 area around the target chip 33.
  • the projection of the target chip in the first plane falls within the projection range of the RDL in the first plane.
  • the pin of the target chip can be fan-outd to the area of the target chip and the peripheral area, and connected to the metal wiring.
  • the interconnection between the chip and the chip can be realized by fan-outing the metal wiring, and the metal wiring in the RDL can realize electrical interconnection with the chip pins.
  • step 1e is performed: as shown in FIG. 11, a fourth connecting member 41 is prepared on the surface of the RDL 34.
  • a fourth connector can be prepared on the lower surface of the RDL to facilitate connection with the PCB.
  • the fourth connecting member may be a solder ball, a CCSB, or an equivalent structure having a similar electrical connection function, and may be prepared by plating, printing, balling, or the like.
  • an under bump metallization (UBM) structure may be selectively formed in a region in contact with the organic dielectric layer under the fourth connecting member according to actual requirements. Improve bonding strength and enhance mechanical reliability. . This application does not limit the materials, structure and process of UBM.
  • a structure as shown in FIG. 11 is obtained, which may be referred to as a reconstructed wafer.
  • step 1f is performed: as shown in FIG. 12, the top chip 80 is connected to the second surface of the substrate 31 through the third connecting member 42.
  • connection process of the top chip may be Surface Mount Technology (SMT) (method 1) or pre stack (method 2).
  • SMT Surface Mount Technology
  • pre stack method 2
  • the reconstructed wafer obtained in step 1e can be diced into a single packaged particle.
  • the SMT process is applied to the PCB, and is attached to the PCB, and then the top chip is attached to the substrate of the packaged particles by solder paste or the like. Finally, after a reflow, the top chip and the reconstituted wafer are simultaneously integrated on the PCB.
  • the reconstructed wafer obtained in the above step 1e may be flipped in the vertical direction to reconstitute the wafer.
  • the other side is attached to the carrier 92 while the carrier 91 can be removed.
  • the film material selected for bonding the reconstructed wafer to the carrier 92 can be referred to the relevant description in step 1a.
  • the carrier 92 shown in FIG. 12 is different from the carrier 91 shown in FIGS. 6 to 11, or is not the same carrier. That is to say, in the embodiment of the present application, two carrier plates are used.
  • the top chip 80 is attached to the second surface of the substrate 31 through the third connection member 42.
  • the third connector 42 is pre-set on the top chip 50.
  • a third connector 42 may be prepared on the second surface of the substrate 31 and then soldered to the top chip 50.
  • the third connecting member 42 may be interconnected with the pads of the second surface of the substrate, and may be interconnected by: Mass Reflow, Thermo Compression Bonding, or other equivalent. Welding method.
  • the carrier 92 is removed and the resulting chip package structure is diced to obtain a single package of particles.
  • the singulated single packaged particles can be attached to the PCB via SMT and reflowed for soldering.
  • a buffer material may be filled between the PCB and the RDL to increase the reliability of the structure.
  • the chip package structure of the embodiment of the present application reduces the limitation of the package structure by the substrate process by replacing the lower substrate by the RDL.
  • the overall thickness can be reduced, so that the chip package structure can be more applied to the thickness.
  • Higher terminal equipment is required; at the same time, the density of the pins can be increased; on the other hand, the number of vertical interconnection channels is increased under the condition of the same package area, thereby increasing the bandwidth of the top chip.
  • the thickness can be further reduced by using a vertical interconnection channel instead of a thermocompression bonding ball to achieve electrical interconnection, and a method of grinding the MC.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • FIG. 13 shows a schematic structural diagram of a chip package structure 60 in accordance with another embodiment of the present application. It should be noted that, in order to facilitate understanding, in the embodiments shown below, the same structures are still given the same reference numerals in the structures shown in the different embodiments, and the details of the same structures are omitted for brevity. Description.
  • the chip package structure 50 includes: a substrate 31, an MC 32, a vertical interconnection channel 33 (including a first copper pillar (or abrasive solder ball) 51 and a first connection member 52), an RDL 34, and a target chip. 37.
  • the pad 36 of the target chip 37 is connected to the metal wiring exposed on the first surface of the RDL 34 through the second connection member 35.
  • the pad 36 of the target chip 37 can be exposed through the connector 35 and exposed on the RDL 34.
  • the metal wiring of the first surface is soldered to achieve electrical interconnection with the pins of the target chip.
  • the target chip and the first surface of the substrate 31 are coated with an adhesive material 38, such as DAF glue, PI, or the like.
  • the adhesive material also has a stress buffering effect.
  • the vertical interconnection channel 33 is connected to the substrate 31 through the first copper pillar (or abrasive solder ball) 51 and the first connection member 52. This is due to the different packaging process of the chip package structure 50.
  • the chip package structure 50 will be described in detail below with reference to FIGS. 14 to 25. 14 through 23 illustrate schematic views of a chip package structure 50 encapsulating another embodiment of the present application by another chip packaging method.
  • step 2a is performed: as shown in FIG. 14, the RDL is mounted on the carrier 91.
  • the film material is selectively coated on the upper surface of the carrier 91, and may be, for example, an adhesive layer film, a sacrificial layer film, or a buffer layer film.
  • a single or multiple layer RDL 34 is then prepared on the film.
  • the main steps include a step of sputtering a seed layer, coating a dielectric layer, photolithography, development, high temperature curing, electroplating, seed removal, and the like.
  • the first surface of the RDL can be selectively prepared for UBM.
  • the material of the carrier 91 and the upper surface thereof, the material of the dielectric layer, the metal wiring, and the preparation method thereof can be referred to the packaging method one.
  • step 2b is performed: as shown in FIGS. 15 and 16, a vertical interconnection via 33 is prepared on the first surface of the RDL 34.
  • the vertical interconnection channel 33 may include a first copper pillar (or abrasive solder ball) 51 and a first connecting member 52.
  • a first copper pillar (or abrasive solder ball) 51 is first prepared.
  • the vertical interconnect channel can be prepared by a sputtering seed layer, dry film lamination lithography, development, curing, electroplating, degumming, seed removal layer, plastic sealing, and the like. That is, the vertical interconnection channel can be plated at a position where the first surface metal wiring of the RDL is exposed.
  • the structure and process of the vertical interconnection channel are not limited in the embodiment of the present application.
  • the vertical interconnect channel can also be used to form a vertical interconnect mold via (TMV) in a molding compound by means of laser drilling or Deep Reactive Ion Etching (DRIE).
  • TSV vertical interconnect mold via
  • DRIE Deep Reactive Ion Etching
  • the conductive material fills the vias to achieve vertical interconnect channels.
  • the conductive material in the through hole may be a metal such as copper, aluminum or tin, or a conductive adhesive, and the filling method may be electroplating, electroless plating or dispensing.
  • execution 2c as shown in FIG. 17, the target chip 37 is fixed on the RDL 34.
  • the second connector 35 Before the target chip 37 is fixed, the second connector 35 may be prepared on the pad 36 of the target chip 37, and then the target chip 37 with the second connector 35 is fixed on the first surface of the RDL 34, and The interconnection between the second connector 35 and the metal wiring in the RDL 34 is achieved by reflow.
  • a buffer material such as UnderFill
  • a film material like a dielectric layer may be applied between the second connectors 35.
  • the material selection and preparation method of the target chip, the second connecting member and the buffer material can refer to the embodiments described above.
  • the second connecting member is a second copper post
  • the top of the second copper post needs to have a solder-lead material such as a solder tip/cap to improve the interconnection of the second connecting member and the RDL. Reliability.
  • nickel (Ni), titanium (Ti) or other barrier metal may be added to the top of the copper pillar to achieve isolation of Cu and tin (Sn).
  • step 2d is performed: as shown in FIGS. 18 to 20, the MC 32 is filled, and the upper surface of the MC 32 is ground.
  • the specific method of filling the MC 32 can refer to the packaging method one.
  • MC fill height is higher than filled MC The highest point of the surface of the target chip (i.e., the upper surface shown in Fig. 18).
  • the filling height of the MC can also be thinned by grinding.
  • the grinding thickness of the MC may be such that only the first copper pillar (or abrasive solder ball) 51 is exposed to the first surface of the MC 32 (as shown in FIG. 19) by grinding as needed, or may be based on product thickness or heat dissipation requirements.
  • Formed as an exposed chip that is, by grinding the first surface of the MC until the back surface of the target chip is exposed on the first surface of the MC (as shown in FIG. 20), or continuing to polish the back surface of the MC and the target chip to realize MC Simultaneous thinning with the target chip.
  • the structure obtained by the above steps may be referred to as a reconstructed wafer.
  • step 2e is performed: as shown in FIG. 21, the substrate 31 is attached.
  • the stress buffer layer 38 (for example, DAS, PI, etc.) may be coated on the first surface of the substrate 31, and then the substrate 31 is soldered through the first connecting member 52 in FIG. 19 or FIG.
  • the upper surface of the structure i.e., the position of the back side of the target chip
  • the first connector 52 is interconnected with the first copper pillar (or abrasive solder ball) 51 through the pad of the first surface of the substrate to form a vertical interconnection channel 33.
  • the first connecting member may be a second copper pillar (as shown in FIG. 3) or a pre-solder (FIG. 4). Shown in it).
  • the first connector may be first prepared on the pad of the first surface of the substrate 31, or a surface in contact with the substrate in the vertical interconnection channel may be prepared first.
  • the pre-coated solder paste can be prepared by a printing process, and the second copper pillar can be prepared by electroplating.
  • the first connector is a pre-coated solder paste or solder ball (as shown in FIG. 20).
  • the solder balls may be soldered to the pads on the lower surface of the substrate in advance, or may be soldered to the second copper pillars in advance.
  • the solder ball may be a solder ball, a solder bump, a CCSB, a C4, or other equivalent structure having an electrical interconnection function.
  • the soldering sequence of the substrate can be adjusted accordingly. If the first connector is pre-attached to the first surface of the substrate, the first connector may be directly soldered to the reconstituted wafer; if the first connector is pre-connected in the vertical interconnect channel (or pre-prepared in the reconstruction) On the wafer, the first connector can be soldered to the pad on the first surface of the substrate.
  • a stress buffer layer may be filled between the substrate and the MC to enhance the reliability of the structure.
  • 21 and 22 show schematic views in the case where different adhesive materials are selected.
  • 21 shows a schematic view of the adhesive material not wrapping the interconnecting channels.
  • the adhesive material 38 shown in FIG. 21 may be one or more of silver paste, DAF gel, PI, and the like. That is, an adhesive material is applied to the back surface of the target chip before the substrate 31 is attached.
  • Figure 22 shows a schematic view of an adhesive material wrapping interconnecting channels.
  • the adhesive material may be one or more of silver glue, DAF glue, PI, TCNCP, TCNCF, and the like.
  • the DAF may be first attached to the back side of the target chip 37 while other adhesive materials such as silver paste are applied to the area of the first surface of the MC 32 corresponding to the periphery of the target chip 37.
  • the first connecting member 52 can be soldered to the first surface of the substrate 31.
  • the first connecting member 52 can be connected to the interconnecting passage 51. The soldering is completed by reflow; at the same time, the adhesive material 38 can be deformed by hot pressing to uniformly wrap the first connecting member 52 (as shown in FIG. 22) to protect the back surface of the target chip and improve the reliability of the first connecting member 52. effect.
  • the TCNCP or TCNCF may be coated on the first surface of the substrate 31 or the surface of the MD before the substrate 31 is attached.
  • the first connecting member 52 may be soldered to the first surface of the substrate 31 in advance; when the substrate 31 is soldered, the first connecting member 52 is connected to the interconnecting passage 51 by hot pressing.
  • the TCNCP/TCNCF is deformed, and the first connecting member 52 (shown in FIG. 22) is wrapped to realize the protection.
  • step 2f is performed: preparing a fourth connecting member 41 on the second surface of the RDL 34, and then connecting the top chip 80; or
  • Step 2g The top chip 80 is connected to the second surface of the substrate 31 through the third connecting member 42, and then the fourth connecting member 41 is prepared on the second surface of the RDL 34.
  • Steps 2f and 2g can be implemented using pre-stacking techniques or SMT.
  • the fourth connector 41 may be first prepared on the second surface of the RDL, and then the top chip 80 may be mounted (method a); or the top chip 80 may be first mounted on the second surface of the substrate, and then A fourth connector 41 (method b) is prepared on the second surface of the RDL.
  • the structure obtained by the above step 2e may be first inverted onto the carrier 92 such that the second surface of the RDL faces upward, and then the fourth connecting member 41 is prepared on the second surface of the RDL (as shown in the figure). 23)).
  • the material and preparation method of the fourth connecting member can be referred to the packaging method one.
  • the structure is then flipped over to the carrier 93 with the second surface of the substrate layer facing up, with the top chip mounted (as shown in Figure 24).
  • the specific process can refer to the packaging method one.
  • the top chip 80 may be first mounted on the second surface of the substrate.
  • the packaging method 1 The structure on which the top chip is mounted is then flipped over the carrier 92 with the second surface of the RDL facing up, and a fourth connector 41 (shown in Figure 25) is prepared on the second surface of the RDL.
  • the material and preparation method of the fourth connecting member can be referred to the packaging method one.
  • the structure obtained in the above step 2e may be flipped onto the carrier 92, and the second surface of the RDL 34 faces upward to prepare a fourth connecting member 41 (refer to FIG. 23), and then diced into a single package. Particles. Finally, the dicing package particles are fixed on the PCB by SMT technology on the PCB, and then the top chip 80 is fixed on the second surface of the substrate 31, and the package particles and the top chip are soldered on the PCB by one reflow. on.
  • top-level chips of the above examples are merely illustrative and should not be construed as limiting the application.
  • present application does not exclude packaging of the top-level chips by other existing or future technologies.
  • the chip package structure of the embodiment of the present application reduces the limitation of the package structure by the substrate process by replacing the lower substrate by the RDL.
  • the overall thickness can be reduced, so that the chip package structure can be more applied to the thickness.
  • Higher terminal equipment is required; at the same time, the density of the pins can be increased; on the other hand, the number of vertical interconnection channels is increased under the condition of the same package area, thereby increasing the bandwidth of the top chip.
  • the thickness can be further reduced by using a vertical interconnection channel instead of a thermocompression bonding ball to achieve electrical interconnection, and a method of grinding the MC and the target chip.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • FIG. 26 shows a schematic structural diagram of a chip package structure 60 in accordance with still another embodiment of the present application.
  • the chip package structure 60 includes: a substrate 31, an MC 32, a vertical interconnection channel 33 (including a first copper pillar (or abrasive solder ball) 51 and a first connector 52), an RDL 34, and a target chip. 37.
  • the pad 36 of the target chip 37 is connected to the metal wiring exposed on the upper surface of the RDL 34.
  • the pads 36 of the target chip 37 can be directly soldered to the metal wires exposed on the upper surface of the RDL 34 to achieve the target chip. Electrical interconnection between the pins. This is due to the different packaging process of the chip package structure 60.
  • the target chip and the first surface of the substrate 31 are coated with an adhesive material 38, such as DAF glue, PI, or the like.
  • the adhesive material simultaneously acts as a stress buffer.
  • the chip package structure 60 will be described in detail below with reference to FIGS. 27 to 30.
  • 27 through 30 illustrate schematic diagrams of packaging a chip package structure 60 of yet another embodiment of the present application by yet another chip packaging method.
  • step 3a is performed: as shown in Fig. 27, a vertical interconnection channel 33 is prepared.
  • the vertical interconnection channel 33 may include a first copper pillar (or abrasive solder ball) 51 and a first connecting member 52.
  • a first copper pillar (or abrasive solder ball) 51 is first prepared.
  • the vertical interconnection channel 33 in the embodiment of the present application may be the same material selected for the vertical interconnection channel 33 of the package method 2.
  • the first copper pillar (or abrasive solder ball) 51 may be directly prepared on the carrier 91. Specifically, an adhesion layer, a buffer layer, a seed layer, and the like are first prepared on the carrier 91. The first copper pillar (or abrasive solder ball) 51 is then prepared by a dry film lithography-electroplating-de-gelling-de-seed layer or the like.
  • step 3b is performed: as shown in FIG. 28, the target chip 37 is fixed on the carrier 91.
  • a single or a plurality of target chips 37 are directly attached to the upper surface of the carrier 91, and an active surface of the target chip 37 faces downward with respect to the upper surface of the carrier 91, that is, a pin of the target chip. Lead out through the pad.
  • the MC 32 is then filled to isolate the target chip from the outside, and the MC, or MC and the target chip are ground as needed to thin the chip package structure, or the back side of the target chip 37 is leaked out of the surface (ie, Exposed Die). .
  • the filling height and package height of the MC can be referred to the packaging method one.
  • the structure obtained in the above steps may be referred to as a reconstructed wafer.
  • step 3c is performed: as shown in FIG. 29, the substrate 31 is fixed on the second surface of the MC 32.
  • the reconstructed wafer and the substrate 31 may be interconnected by a first connection member 52 (ie, a portion of the vertical interconnection channel 33).
  • a buffer material may be filled between the substrate 31 and the MC 32.
  • the package method 2 please refer to the package method 2.
  • step 3d is performed: as shown in FIG. 30, the RDL 34 is prepared.
  • the structure obtained in the above step 3c may be inverted to the carrier 92 to remove the structure of the adhesion layer, the buffer layer, and the like between the carrier 91 and the MC 32.
  • the inverted structure of the target chip faces upward and is flush with the second surface of the MC.
  • a dielectric layer is coated on the surface and a single layer or layers of RDL is prepared, and then a fourth connector 41 is prepared on the second surface of the RDL.
  • step 3e the top chip 80 is fixed.
  • the chip package structure of the embodiment of the present application reduces the limitation of the package structure by the substrate process by replacing the lower substrate by the RDL.
  • the overall thickness can be reduced, so that the chip package structure can be more applied to the thickness.
  • Higher terminal equipment is required; at the same time, the density of the pins can be increased; on the other hand, the number of vertical interconnection channels is increased under the condition of the same package area, thereby increasing the bandwidth of the top chip.
  • the thickness can be further reduced by using a vertical interconnection channel instead of a thermocompression bonding ball to achieve electrical interconnection, and a method of grinding the MC.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • FIG. 31 is a schematic structural diagram of a chip package structure 70 according to still another embodiment of the present application.
  • the chip package structure 70 includes a first substrate 31, a second substrate 43, an MC 32, a vertical interconnection via 33, a target chip 37, and an adhesion material 38.
  • the pad 36 of the target chip 37 is soldered to the first surface of the second substrate 43 through the second connecting member 35 to realize electrical interconnection between the pin of the target chip and the second substrate.
  • the vertical interconnection channel comprises an abrasive solder ball and a first connecting member, the abrasive solder ball being connected to the first surface of the second substrate through the first connecting member;
  • the interconnecting channel is in soldered contact with the upper surface of the first substrate.
  • the specific structure of the chip package structure 70, the packaging method, and the connection manner between the interconnection channel and the substrate can be referred to
  • the substrate-level process in the prior art is examined, and for brevity, it will not be repeated here.
  • the chip package structure of the embodiment of the present application realizes electrical interconnection by using a vertical interconnection channel instead of the thermocompression bonding ball, which can reduce the thickness of the chip package structure, and increase the vertical direction when the package area is constant.
  • the number of interconnected channels increases the bandwidth of the top-level chip while providing good control over warpage.
  • chip package structure of the embodiment of the present application is described in detail above with reference to FIG. 2 to FIG. 31. It should be understood that the above chip package structure may be used alone or in a stacked three-dimensional chip package structure.
  • FIG. 32 shows a schematic structural diagram of a three-dimensional chip package structure 100 according to an embodiment of the present application.
  • the three-dimensional chip package structure 100 includes an upper package layer 200 and a lower package layer 300.
  • the upper encapsulation layer 200 may include the top layer chip 80 and the third connection member 42 described above
  • the lower encapsulation layer 300 may include any one of the chip package structures 30, 50, 60 or 70 described above or
  • the lower package layer 200 may also include other forms of chip package structures, which are not specifically limited in this application.
  • the three-dimensional chip package structure may include N chip package structures. Referring to the first plane, the N chip package structures are vertically stacked in a bottom-up order, and the target chip of the i-th chip package structure and the target chip of the i+1th chip package structure are electrically interconnected.
  • N is the total number of layers of the chip package structure included in the three-dimensional chip package structure
  • N is a natural number greater than 1, i ⁇ [1, N - 1], and i is a natural number.
  • the three-dimensional chip package structure of the embodiment of the present application can reduce the overall thickness of the three-dimensional chip package structure by using the chip package structure of the embodiment of the present application.
  • chip package structure and the three-dimensional chip package structure of the embodiments of the present application are described in detail above with reference to FIG. 2 to FIG.
  • chip packaging method of the embodiment of the present application will be described in detail with reference to FIGS. 33 to 35.
  • FIG. 33 is a schematic flowchart of a chip packaging method 400 according to an embodiment of the present application. As shown in FIG. 33, the method 400 includes:
  • chip packaging method 400 of the embodiment of the present application has been described in detail in conjunction with FIG. 5 to FIG. 12 in the packaging method one described above, and is not described herein again for brevity.
  • FIG. 34 is a schematic flowchart of a chip packaging method according to another embodiment of the present application. As shown in FIG. 34, the method 500 includes:
  • chip encapsulation method 500 of the embodiment of the present application has been described in detail in FIG. 13 to FIG. 25 in the encapsulation method 2 described above. For brevity, details are not described herein again.
  • FIG. 35 is a schematic flowchart of a chip packaging method according to still another embodiment of the present application. As shown in FIG. 35, the method 600 includes:
  • the first carrier may correspond to the carrier 91 in the second method of packaging, and the first surface of the first carrier may correspond to the upper surface of the carrier 91 in the second method of packaging.
  • the chip packaging method of the embodiment of the present application reduces the limitation of the package structure by the substrate process by replacing the lower substrate by RDL.
  • the overall thickness can be reduced, so that the chip package structure can be more applied to the thickness.
  • Higher terminal equipment is required; at the same time, the density of the pins can be increased; on the other hand, the number of vertical interconnection channels is increased under the condition of the same package area, thereby increasing the bandwidth of the top chip.
  • the thickness can be further reduced by using a vertical interconnection channel instead of a thermocompression bonding ball to achieve electrical interconnection, and a method of grinding the MC.
  • the upper substrate remains, and the degree of warpage of the chip package structure can be well controlled within an acceptable range.
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • chip packaging method may be performed by a robot or a numerically controlled processing method, and the device software or process for executing the chip packaging method may perform the above by executing computer program code stored in the memory. Chip packaging method.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple On the network unit. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

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Abstract

一种芯片封装结构和方法，能够减小封装结构厚度，提高管脚密度，增加互连通道数量，增大顶层芯片的带宽。该芯片封装结构包括：重布线层RDL（34）；目标芯片（37），包括有源面和背面，该目标芯片（37）的有源面与该RDL（34）的第一表面连接；基板（31），该基板（31）的第一表面与该目标芯片（37）的背面相对；互连通道（33），位于该目标芯片（37）的四周，该互连通道（33）的一端与该RDL（34）的第一表面相连，该互连通道（33）的另一端与该基板（31）的第一表面相连。

Description

芯片封装结构和方法
本申请要求于2016年11月18日提交中国专利局、申请号为201611028571.1、发明名称为“芯片封装结构和方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片封装领域，并且更具体地，涉及芯片封装结构和方法。
背景技术
随着便携式电子产品的飞速增长，电子器件中安装在印刷电路板(Printed Circuit Broad，PCB)上的半导体封装也逐渐变小变薄。因此，封装在产业链中的地位也变得更加重要。
目前，已知一种封装结构，采用堆叠封装(Package on Package，POP)技术，将芯片封装于上、下两层基板之间。具体地，下层基板可用于承载目标芯片，上层基板可用于承载顶层芯片，通过上、下两层基板的支撑作用，可以实现多层芯片封装结构在垂直方向的堆叠，从而实现三维封装。其中，上层基板可以为转接板(interposer)基板，下层基板可以为普通有机基板，芯片与基板之间可以填充模塑料(Molding Compound，MC)，MC中具有垂直互连系统(Vertical Interconnects System，VIS)，以实现上、下层基板之间的电气互连。
然而，通过两层基板封装芯片使得整个封装结构(包括：上层基板、MC、目标芯片和下层基板)的厚度较大(例如，约为490微米(μm))，并不能满足当前技术中半导体封装变小变薄的需求，同时也不利于芯片的散热。因此，需要提供一种技术，能够减小封装结构的厚度。
发明内容
本申请提供了一种芯片封装结构和方法，以通过重布线层(Redistribution Layer，RDL)代替下层基板，达到减小封装结构厚度、提高管脚密度的效果，同时提高互连通道密度，提高顶层芯片带宽。
第一方面，提供了一种芯片封装结构，包括：
重布线层RDL；
目标芯片，包括有源面和背面，所述目标芯片的有源面与所述RDL的第一表面连接；
基板，所述基板的第一表面与所述目标芯片的背面相对；
互连通道，位于所述目标芯片的四周，所述互连通道的一端与所述RDL的第一表面相连，所述互连通道的另一端与所述基板的第一表面相连。
因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，与现有技术相比，减小了基板加工工艺对封装结构的限制。
具体地，一方面，基板的加工工艺(即，基板级工艺)一方面使得基板的尺寸(例如，厚度)较大，整个芯片封装结构的厚度受限于基板加工厚度，使得该芯片封装结构不适用于对厚度要求较高的产品，而本申请实施例中通过采用圆片级工艺制备RDL，可 以很好地控制RDL厚度，从而达到减小整体厚度的效果，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备。同时，基板的加工工艺也使得用于连接芯片管脚的间距较大，即，管脚密度较小，若要增加管脚，就需要增大目标芯片的面积(或者说，封装面积)，而本申请实施例中通过采用圆片级工艺制备RDL，其管脚间距离可以做的更小，从而增加了管脚密度。
另一方面，现有技术中的互连通道采用热压焊球，热压焊球在通过高温压缩高度的同时，焊球横向发生了膨胀，限制了VIS通道的最小间距，从而使得VIS的通道数量受限，从而限制了顶层芯片的带宽，而本申请实施例中，通过使用铜柱、研磨焊球等代替热压焊球，避免了对互连通道的最小间距的限制，从而可以增加互连通道的密度，进而提高顶层芯片的带宽。
再一方面，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
结合第一方面，在第一方面的第一种可能的实现方式中，所述互连通道包括预植于所述基板的第一表面的第一铜柱。
结合第一方面，在第一方面的第二种可能的实现方式中，所述互连通道包括研磨焊球和第一连接件，所述研磨焊球的一端与所述RDL连接，所述研磨焊球的另一端通过所述第一连接件与所述基板的第一表面连接，
所述研磨焊球包括钎料球，所述第一连接件包括以下任意一种：第二铜柱、预涂锡膏或焊球。
结合第一方面，在第一方面的第三种可能的实现方式中，所述互连通道包括第一铜柱和第一连接件，所述第一铜柱的一端与所述RDL连接，所述第一铜柱的另一端通过所述第一连接件与所述基板的第一表面连接，
所述第一连接件包括预涂锡膏或焊球。
因此，通过使用以上列举的垂直互连通道代替热压焊球来实现电气互连，可以进一步减小厚度。
结合第一方面或其上述可能的实现方式，在第一方面的第四种可能的实现方式中，所述RDL包括金属布线，所述目标芯片的有源面包括焊盘，所述焊盘与露出于所述RDL的第一表面的金属布线连接。
可选地，所述芯片封装结构还包括第二连接件，所述第二连接件的一端与所述焊盘连接，所述第二连接件的另一端与露出于所述RDL的第一表面的金属布线连接。
因此，通过第二连接件与RDL的第一表面连接，可以减小研磨造成的应力损伤。
结合第一方面或其上述可能的实现方式，在第一方面的第五种可能的实现方式中，所述芯片封装结构还包括模塑料MC，所述MC填充于所述RDL与所述基板之间，并从所述目标芯片的四周包围所述目标芯片，所述互连通道沿第一方向贯穿于所述MC，所述第一方向与所述RDL的第一表面基本垂直；
其中，所述MC为可研磨材料。即，该MC具有可被研磨的特性，通过研磨可以减薄MC的厚度，从而进一步减小该芯片封装结构的整体厚度。
这里，所述第一方向与所述RDL的第一表面基本垂直，可以理解为所述第一方向与所述RDL的第一表面的夹角为近似90度。也就是说，第一方向与RDL的第一表面的夹角在制备过程中可能存在一定的误差范围，但这是可以忽略的，或者说，是允许的。
应理解，这里示出的互连通道沿第一方向贯穿MC的情况仅为一种可能的实现方式，而不应对本申请构成任何限定。在实际的制备过程中，第一方向与RDL的夹角可以为近似90度，也可以具有一定的倾角(例如，小于90度)，只要保证互连通道能够贯穿MC的第一表面和第二表面，均应落入本申请的保护范围内。
结合第一方面或其上述可能的实现方式，在第一方面的第六种可能的实现方式中，所述基板的第一表面与所述目标芯片的背面之间涂覆有粘附材料，所述粘附材料包括以下至少一种：热压非导电胶、热压非导电膜、芯片粘接薄膜或银胶。
粘附材料可以涂覆于目标芯片的背面与基板的第一表面之间，也可以同时涂覆于目标芯片的边缘处、MC的第一表面和基板的第一表面之间，以将互连通道包裹住，从而达到保护目标芯片背面，提高互连通道的可靠性的效果。
第二方面，提供了一种三维芯片封装结构，包括第一方面或第一方面的任意一种可能的实现方式中的芯片封装结构。
因此，本申请实施例的三维芯片封装结构，通过使用本申请实施例的芯片封装结构，可以在总体上减小三维芯片封装结构的整体厚度。
需要说明的是，本申请实施例的三维芯片封装结构，并不限于使用本申请实施例的芯片封装结构，本申请实施例的芯片封装结构也可以与其他形式的芯片封装结构共同用于堆叠三维芯片封装结构。
第三方面，提供了一种芯片封装方法，包括：
在基板的第一表面上连接互连通道，所述互连通道的一端与所述基板的第一表面相连；
在所述基板的第一表面上连接目标芯片，所述目标芯片的背面与所述基板的第一表面相对；
制备重布线层RDL，所述RDL与所述互连通道的另一端相连，所述RDL的第一表面与所述目标芯片的有源面连接。
因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，减小了基板工艺对封装结构的限制，一方面，可以减小整体厚度，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备；同时可以增加管脚密度；另一方面，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了顶层芯片的带宽。同时，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
结合第三方面，在第三方面的第一种可能的实现方式中，所述互连通道包括第一铜柱，以及，
所述在基板的第一表面上连接互连通道，包括：
在所述基板的第一表面电镀所述第一铜柱。
因此，通过使用第一铜柱代替热压焊球来实现电气互连，可以进一步减小厚度。
结合第三方面或其上述可能的实现方式，在第三方面的第二种可能的实现方式中，在所述制备RDL之前，所述芯片封装方法还包括：
在所述基板的第一表面上填充模塑料MC，以使所述MC从所述目标芯片的四周包围所述目标芯片，
其中，所述目标芯片的有源面包括焊盘，所述焊盘预先连接第二连接件的一端，所 述第二连接件的另一端露出于所述MC的第一表面，所述互连通道沿第一方向贯穿于所述MC，所述第一方向与所述RDL的第一表面基本垂直。
因此，通过研磨MC可以进一步减小该芯片封装结构的整体厚度。
这里，所述第一方向与所述RDL的第一表面基本垂直，可以理解为所述第一方向与所述RDL的第一表面的夹角为近似90度。也就是说，第一方向与RDL的第一表面的夹角在制备过程中可能存在一定的误差范围，但这是可以忽略的，或者说，是允许的。
应理解，这里示出的互连通道沿第一方向贯穿MC的情况仅为一种可能的实现方式，而不应对本申请构成任何限定。在实际的制备过程中，第一方向与RDL的夹角可以为近似90度，也可以具有一定的倾角(例如，小于90度)，只要保证互连通道能够贯穿MC的第一表面和第二表面，均应落入本申请的保护范围内。
可选地，所述芯片封装方法还包括：
根据所述芯片封装结构的预设厚度，研磨所述MC的第一表面。
结合第三方面或其上述可能的实现方式，在第三方面的第三种可能的实现方式中，所述RDL包括金属布线，所述目标芯片的有源面包括焊盘，所述焊盘预先连接第二连接件的一端，所述芯片封装方法还包括：
将所述第二连接件的另一端与露出于所述RDL的第一表面的金属布线连接，以使所述金属布线与所述目标芯片的有源面连接。
因此，通过第二连接件与RDL的第一表面连接，可以减小研磨造成的应力损伤。
第四方面，提供了一种芯片封装方法，包括：
制备重布线层RDL；
在所述RDL的第一表面连接互连通道，所述互连通道的一端与所述RDL的第一表面相连；
在所述RDL的第一表面上连接目标芯片，所述目标芯片的有源面与所述RDL的第一表面连接；
在所述目标芯片的背面放置基板，所述基板的第一表面与所述互连通道的另一端相连。
因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，减小了基板工艺对封装结构的限制，一方面，可以减小整体厚度，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备；同时可以增加管脚密度；另一方面，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了顶层芯片的带宽。同时，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
结合第四方面，在第四方面的第一种可能的实现方式中，所述互连通道包括研磨焊球和第一连接件，所述研磨焊球包括钎料球，所述第一连接件包括：第二铜柱、预涂锡膏或焊球，
所述在所述RDL的第一表面连接互连通道，包括：
通过所述研磨焊球的一端与所述RDL的第一表面连接；
通过所述研磨焊球的另一端与所述第一连接件的一端连接；
所述芯片封装方法还包括：
通过所述研磨焊球的另一端通过所述第一连接件与所述基板的第一表面连接。
结合第四方面，在第四方面的第二种可能的实现方式中，所述互连通道包括第一铜柱和第一连接件，所述第一连接件包括预涂锡膏或焊球，
所述在所述RDL的第一表面连接互连通道，包括：
通过所述第一铜柱的一端与所述RDL的第一表面连接；
通过所述第一铜柱的另一端与所述第一连接件的一端连接；
所述芯片封装方法还包括：
通过所述第一连接件的另一端与所述基板的第一表面连接。
因此，通过使用以上列举的垂直互连通道代替热压焊球来实现电气互连，可以进一步减小厚度。
结合第四方面或其上述可能的实现方式，在第四方面的第三种可能的实现方式中，所述RDL包括金属布线，所述目标芯片的有源面包括焊盘，所述焊盘预先连接第二连接件的一端，所述芯片封装方法还包括：
将所述第二连接件的另一端与露出于所述RDL的第一表面的金属布线连接，以使所述金属布线与所述目标芯片的有源面连接。
因此，通过第二连接件与RDL的第一表面连接，可以减小研磨造成的应力损伤。
结合第四方面或其上述可能的实现方式，在第四方面的第四种可能的实现方式中，在所述目标芯片的背面放置基板之前，所述芯片封装方法还包括：
在所述RDL的第一表面上填充模塑料MC，以使所述MC从所述目标芯片的四周包围所述目标芯片，所述目标芯片的背面露出于所述MC的第二表面，所述互连通道沿第一方向贯穿于所述MC，所述第一方向与所述RDL的第一表面基本垂直。
因此，通过研磨MC可以进一步减小该芯片封装结构的整体厚度。
可选地，所述芯片封装方法还包括：
根据所述芯片封装结构的预设厚度，研磨所述MC的第二表面。
第五方面，提供了一种芯片封装方法，包括：
在第一载板的第一表面连接互连通道；
在所述第一载板的第一表面上连接目标芯片，所述目标芯片的有源面与所述第一载板的第一表面至少部分接触；
在所述目标芯片的背面放置基板，所述基板的第一表面与所述互连通道的一端相连，其中，所述目标芯片的背面为所述目标芯片上与所述有源面相平行的面；
移除所述第一载板，以露出所述目标芯片的有源面；
在所述目标芯片的有源面上制备重布线层RDL，所述RDL的第一表面与所述互连通道的另一端相连，且所述RDL的第一表面与所述目标芯片的有源面至少部分接触。
因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，减小了基板工艺对封装结构的限制，一方面，可以减小整体厚度，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备；同时可以增加管脚密度；另一方面，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了顶层芯片的带宽。同时，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
结合第五方面，在第五方面的第一种可能的实现方式中，所述互连通道包括研磨焊球和第一连接件，所述研磨焊球包括钎料球，所述第一连接件包括：第二铜柱、预涂锡 膏或焊球，所述芯片封装方法还包括：
通过所述第一连接件的一端与所述基板的第一表面连接；
通过所述第一连接件的另一端与所述研磨焊球的一端连接；
通过所述研磨焊球的另一端与所述RDL的第一表面连接。
结合第五方面，在第五方面的第二种可能的实现方式中，所述互连通道包括第一铜柱和第一连接件，所述第一连接件包括预涂锡膏或焊球，所述芯片封装方法还包括：
通过所述第一连接件的一端与所述基板的第一表面连接；
通过所述第一连接件的另一端与所述第一铜柱的一端连接；
通过所述第一铜柱的另一端与所述RDL的第一表面连接。
因此，通过使用以上列举的垂直互连通道代替热压焊球来实现电气互连，可以进一步减小厚度。
结合第五方面或其上述可能的实现方式，在第五方面的第三种可能的实现方式中，所述RDL包括金属布线，所述目标芯片的有源面包括焊盘，所述芯片封装方法还包括：
将所述焊盘与露出于所述RDL的第一表面的金属布线焊接，以使所述金属布线与所述目标芯片的有源面连接。
因此，本申请实施例的芯片封装方法可以将基板的焊盘与RDL的表面直接连接，无需使用连接件，从而减少连接件的使用，简化工艺。
结合第五方面或其上述可能的实现方式，在第五方面的第四种可能的实现方式中，在所述目标芯片的背面放置基板之前，所述芯片封装方法还包括：
在所述载板的第一表面上填充模塑料MC，以使所述MC从所述目标芯片的四周包围所述目标芯片和所述目标芯片的背面，所述互连通道沿第一方向贯穿于所述MC，所述第一方向与所述RDL的第一表面垂直。
可选地，所述芯片封装方法还包括：
根据所述芯片封装结构的预设厚度，研磨所述MC的第一表面，所述MC的第一表面与所述基板的第一表面相对。
在上述某些可能的实现方式中，作为一个实施例，所述第一铜柱的直径大于或等于100微米μm，且高度大于或等于100μm。
在上述某些可能的实现方式中，作为一个实施例，所述第二铜柱的直径小于100μm，所述第二铜柱的高度小于100μm，所述焊球的直径大于40μm。
在上述某些可能的实现方式中，作为一个实施例，所述焊球的直径大于40μm，所述第一铜柱的直径大于或等于100微米μm，高度大于或等于100μm。
本申请实施例的芯片封装结构和方法，通过重布线层代替下层基板，达到减小封装结构厚度、提高管脚密度的效果，同时提高互连通道密度，提高顶层芯片带宽。
附图说明
图1是适用于本申请实施例的芯片封装结构的场景的示意图。
图2是根据本申请实施例的芯片封装结构的示意性结构图。
图3和图4是互连通道与基板通过第一连接件连接的示意图。
图5是根据本申请一实施例的芯片封装结构的示意性结构图。
图6至图12是通过一种芯片封装方法封装本申请一实施例的芯片封装结构的示意 图。
图13是根据本申请另一实施例的芯片封装结构的示意性结构图。
图14至图25是通过另一种芯片封装方法封装本申请另一实施例的芯片封装结构的示意图。
图26是根据本申请又一实施例的芯片封装结构的示意性结构图。
图27至图30是通过又一种芯片封装方法封装本申请又一实施例的芯片封装结构的示意图。
图31是根据本申请再一实施例的芯片封装结构的示意性结构图。
图32是根据本申请一实施例的三维芯片封装结构的示意性结构图。
图33是根据本申请一实施例的芯片封装方法的示意性流程图。
图34是根据本申请另一实施例的芯片封装方法的示意性流程图。
图35是根据本申请再一实施例的芯片封装方法的示意性流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述。
为便于理解，首先结合图1简单说明适用于本申请实施例的芯片封装结构的场景。
图1是适用于本申请实施例的芯片封装结构的场景的示意图。如图1所示，该芯片封装结构12可以通过连接件14(例如，焊球，具体地，可以为钎料球(solder ball)等)与顶层芯片11连接，该芯片封装结构12可以通过连接件15(例如，焊球，具体地可以为solder ball等)和下层的印刷电路板(Printed Circuit Board，PCB)13连接。其中，顶层芯片11可以为存储器(Memory)、集成无源器件(Integrated Passive Devices，IPD)、微机电系统(Micro-Electro-Mechanical System，MEMS)、转接板(interposer)等结构或者封装体。应理解，这里所列举的顶层芯片仅为示例性说明，本申请对此不作限定。
以下，结合图2至图32详细说明本申请实施例的芯片封装结构。
应理解，在以下示出的本申请实施例中的各种结构件的高度、直径或厚度，以及芯片封装结构的整体厚度仅为示例性说明，通过示例性的厚度进行对比，以体现本申请实施例的芯片封装结构对整体厚度的减薄效果，而不应对本申请构成任何限定。只要使用了通过RDL代替两层基板层中的一层进行芯片封装，均应落入本申请的保护范围内。
图2是根据本申请一实施例的芯片封装结构20的示意性结构图。如图2所示，该芯片封装结构20包括：基板31、目标芯片37、互连通道33和重布线层RDL 34。
需要说明的是，图2仅为便于理解该芯片封装结构20与外部的连接关系，在图中示出了连接件(可对应于图1中的连接件14和连接件15)。但这不应对本申请构成任何限定，本申请也不应限于此。
还需要说明的是，目标芯片在出厂之前(即，进入封装厂之前)已经在其一表面制备有铝制焊盘(Aluminum Pad，AP，以下简称焊盘，如图2中示出)36，该焊盘用于封装时将目标芯片固定于其他结构(例如，本申请实施例中所示的RDL)上，并且具有导电作用。目标芯片可以包括有源面(即，表面制备有AP的面)和背面。
通常情况下，有源面和背面基本平行。这里，有源面和背面基本平行，可以理解为所述有源面和背面的夹角为近似0度。也就是说，有源面和背面的夹角在制备过程中可能存在一定的误差范围，但这是可以忽略的，或者说，是允许的。
本领域技术人员可以理解，有源面可以理解为内部含有需要电源才能实现预期功能的元器件(或电路)，与有源相对的为无源，即，不需要电源供电。在本申请实施例中，目标芯片的有源面制备有AP，用于实现与外界(具体地，与RDL中的金属布线)的电气连接。
在本申请实施例中，为方便说明，将与目标芯片的有源面相对的面记作RDL的第一表面，与目标芯片的背面相对的面记作基板的第一表面。其中，目标芯片的有源面与RDL的第一表面连接。互连通道位于目标芯片的四周，一端与RDL的第一表面直接或间接相连，另一端与基板的第一表面直接或间接相连，用于实现RDL与基板之间的电气互连。应注意，本申请对互连通道的数量并未特别限定。
具体地，RDL可以包括介电层和金属布线，该金属布线可以为一层或多层，分布于介电层中，并且露出于该介电层的第一表面和第二表面，如图2中黑色实线部分示出。应注意，本申请对于金属布线的层数并未特别限定，只要能够露出于介电层的第一表面和第二表面，以实现与外部导电结构的连接，均应落入本申请的保护范围内。可以理解的是，该RDL的第一表面与介电层的第一表面在同一平面上，该RDL的第二表面与介电层的第二表面在同一平面上。也就是说，露出于介电层的第一表面，即可以理解为露出于RDL的第一表面。为了简洁，后文省略对相同或者相似情况的说明。
目标芯片可以位于RDL第一表面的上方，与露出于RDL第一表面的金属布线直接接触或通过连接件(例如，后文中所述的连接件35)接触。其中，目标芯片与RDL中的金属布线通过连接件接触的情形未在图2中示出，后文中会结合其他实施例(例如，封装方法一和封装方法二)详细说明。
如图2中所示，目标芯片的有源面包括焊盘36，该焊盘即可以理解为目标芯片与外部连接的管脚。目标芯片的至少部分管脚可以与露出在RDL第一表面的金属布线互连，目标芯片的部分管脚还可以通过扇出型晶圆级封装(Fan Out Wafer Level Package，FOWLP)技术引出至芯片的外围，并与露出在RDL第一表面的金属布线连接。换句话说，目标芯片与RDL的接触点可以为RDL第一表面的金属布线。
本领域技术人员可以理解，RDL还可以包括第二表面(通常情况下，RDL的第二表面与RDL的第一表面平行)，露出于RDL的第二表面的金属布线可以通过连接件与所连接的PCB之间实现电气互连。
相似地，基板也可以包括第二表面(通常情况下，基板的第二表面与基板的第一表面平行)，基板的第二表面可以通过焊球与所连接的顶层芯片之间实现电气互连。
需要说明的是，目标芯片的有源面与背面相互平行，与目标芯片的有源面相对的RDL的第一表面与该有源面平行，且该RDL的第一表面的表面积大于或等于该有源面的表面积；与目标芯片的背面相对的基板的第一表面与目标芯片的背面相互平行，且该基板的第一表面的表面积大于或等于该背面的表面积。也就是说，该目标芯片被RDL和基板包裹在中间，若将该目标芯片看作一个二维平面，例如，记作第一平面(可以对应于图2中YOZ平面)。该目标芯片在第一平面的投影落入RDL在第一平面的投影的范围内，且该目标芯片在第一平面的投影落入基板在第一平面的投影的范围内。即，不管是从上往下看，或者从下往上看，基板和RDL均分布将该目标芯片完全覆盖。
应理解，本申请实施例中仅为方便理解和说明，假设第一平面平行于水平面，第一方向为垂直于水平面的方向(即，竖直方向)，芯片封装工艺可以以水平面为基准，在 垂直方向上堆叠不同的层(如前文中所述的RDL、目标芯片、基板等)，得到芯片封装结构(例如，如图2所示)。但这不应对本申请构成任何限定，只要各层之间的接触面分别平行于第一平面，各层沿着第一方向由下至上堆叠，均应落入本申请保护范围内。以下，为便于理解，均以第一平面平行于水平面，第一方向为垂直于水平面的方向为例进行说明，为了简洁，后文中省略对相同或相似情况的说明。
在本申请实施例中，互连通道用于实现各层之间的电气互连。
具体地，互连通道位于目标芯片的四周，一端与基板的第一表面相连接，另一端与RDL的第一表面相连接。更具体地说，在基板的第一表面和第二表面分布都制备焊盘，互连通道的一端与基板第一表面的焊盘相连接。互连通道的另一端与露出于RDL的第一表面的金属布线相连，即，通过金属布线实现了互连通道和目标芯片的管脚的互连。
另一方面，互连通道又与基板相连，通过基板中的导电结构(即，图2中所示出的与基板垂直的黑色实线部分)与连接于基板第二表面的连接件相连，进而与基板上方的顶层芯片相连(其中，基板第二表面上的水平黑色实线可以理解为连接件与基板第二表面的接触点)。即，实现了目标芯片与顶层芯片的电气互连。
再一方面，露出于RDL第二表面的金属布线又与连接件相连，进而与下方的PCB连接，实现目标芯片、顶层芯片与PCB的电气互连。
由此，互连通道实现了各层之间的电气互连。
一般而言，基板的厚度可以为170μm～560μm，RDL的厚度可以为30至50μm，由此，通过RDL代替基板，可以大大减小整个芯片封装结构的厚度。因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，减小了基板工艺对封装结构的限制。一方面，可以减小整体厚度，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备；同时可以增加管脚密度；另一方面，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了带宽。同时，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
可选地，如图2所示，该芯片封装结构还包括模塑料(Molding Compound，MC)32。
MC填充于基板与RDL之间，并从该目标芯片的四周包围该目标芯片，以将目标芯片与外界隔离，起到防潮、防尘、缓冲的作用，同时可以避免目标芯片与基板之间的相对移动。
该MC可以将目标芯片的侧面和背面包围起来，或者，将目标芯片的侧面包围起来，以减少外界对目标芯片的影响。其中，在目标芯片仅侧面被MC包围的情况下，目标芯片的背面与基板的第一表面之间可以涂覆粘附材料38，将目标芯片固定在基板的第一表面上。
作为示例而非限定，该粘附材料38可以包括以下至少一种：热压非导电胶(Thermal Compression Non-Conductive Paste，TCNCP)、热压非导电膜(Thermal Compression Non-Conductive Film，TCNCF)、芯片粘接薄膜(Die Attach Film，DAF)或银胶(Epoxy)。
也就是说，该粘附材料可以为上述示例的任意一种，或者，上述示例的任意多种的组合。
在本申请实施例中，可以将粘附材料均匀涂覆在MC的第一表面的全部或部分区域。
作为一个实施例，在集成基板之前，可以先将DAF贴于目标芯片的背面，同时在MC的第一表面(即，与基板的第一表面相对的面)与目标芯片的四周相对应的区域涂 覆其他粘附材料，例如，银胶。在集成基板时，通过热压可以使粘附材料变形，以均匀地包裹互连通道(具体可参看图8和图22所示)，从而达到保护目标芯片背面，提高互连通道的可靠性的效果。
作为另一个实施例，在该粘附材料为TCNCP/TCNCF的情况下，可以在焊接基板时，通过热压可以使粘附材料变形，以均匀地包裹互连通道(具体可参看图8和图22所示)，从而达到保护保护目标芯片背面，提高互连通道的可靠性的效果。应理解，以上示例的粘附材料仅为示例性说明，不应对本申请构成任何限定，本申请也不应限于此。例如，该粘附材料还可以为其他能够实现相同功能的材料。
在本申请实施例中，MC由可研磨材料制备。示例性地，MC可以由树脂材料制备，并可以添加一些硬着填充颗粒(例如，二氧化硅)改善其性能。也就是，该MC可以通过研磨减薄厚度。
在本申请实施例中，可以根据芯片封装结构的预设厚度，研磨该MC。
即，根据该芯片封装结构所应用于的设备对该芯片封装结构的厚度要求，可以确定该芯片封装结构的厚度，进而通过研磨MC达到进一步减小芯片封装结构的效果。
在本申请实施例中，互连通道贯穿于MC，互连通道的两端分别露出于MC与基板和RDL相对的两个表面。具体地，在填充过程中，MC在第一方向的填充高度可以高于目标芯片的表面最高点，并且高于互连通道(可以理解，互连通道在第一方向的高度大于或等于目标芯片在第一方向的高度)。
在芯片封装过程中，不论该目标芯片是否倒置(后文中会结合芯片封装方法详细说明)，该MC的填充高度可以高于在填充该MC时目标芯片的表面最高点。其中，目标芯片的表面最高点，可以理解为：以第一平面为参照，目标芯片的有源面和背面中处于较高位置的点。通常情况下，芯片在出厂时，表面已经经过处理，通常情况下是比较平整的。因此，目标芯片的表面最高点，即可以理解为：在填充MC时，目标芯片的上表面和下表面中处于较高位置的面。
另外，本领域技术人员可以理解，由于芯片封装方法的不同，在芯片封装的过程中，可能存在芯片倒置的情况。这里所说的填充MC时目标芯片的表面最高点是指在填充MC这一特殊的时段目标芯片的有源面或背面中处于较高位置的点，但这并不意味着该点一直是该目标芯片的表面最高点。
在本申请实施例中，MC的厚度可以根据芯片封装结构的预设厚度调节。在一种可能的实现方式中，MC可通过研磨减薄厚度。具体地，在填充完MC后，可以根据需要，对MC进行研磨，使得互连通道露出于MC的表面，或者，互连通道和目标芯片的背面同时露出于MC的表面(对应于后文描述的封装方法二和三)，或者，使得互连通道和目标芯片的背面同时露出于MC的表面(对应于后文描述的封装方法一)，同时使得MC露出的表面变得平整，并且起到减薄芯片封装结构的整体厚度的效果。
在本申请实施例中，该MC的厚度约为100μm至200μm。
应理解，本申请实施例中示出的对MC进行研磨的方式仅为示例性说明，而不应对本申请构成任何限定。在本申请实施例中，可以通过激光开孔的方式对MC开口使互连通道露出，或者根据需要先研磨采用再激光开孔的方式使互连通道露出MC。
具体地，若采用激光开孔方式，可以根据情况看是否需要先研磨。若MC覆盖于目标芯片的背面上方，则可以研磨至该目标芯片的背面露出，然后采用激光开孔方式对MC 开孔。这种情况下，互连通道所采用的第一铜柱或研磨焊球则可以采用更小的尺寸，例如，采用高度更小的第一铜柱，或者直径更小的研磨焊球。这种方式可以减少研磨过程中对目标芯片的污染。
可选地，该互连通道沿第一方向贯穿该MC，该第一方向与RDL的第一表面基本垂直。
以第一平面为参照，该互连通道可以垂直于该第一平面贯穿MC，即，可以对应于图2中的OX方向(为方便说明，记作第一方向)。
在本申请实施例中，可以将垂直地贯穿于MC中的互连通道称为垂直互连通道，或者，垂直互连系统(Vertical Interconnects System，VIS)。
这里，第一方向与RDL的第一表面基本垂直，可以理解为第一方向与RDL的第一表面的夹角为近似90度。也就是说，第一方向与RDL的第一表面的夹角在制备过程中可能存在一定的误差范围，但这是可以忽略的，或者说，是允许的。
作为示例而非限定，该互连通道可以包括第一铜柱；或者，该互连通道可以包括第一铜柱和第一连接件，或者，研磨焊球和第一连接件。在本申请实施例中，由于采用了新的互连通道作为基板与RDL之间的导电通道，可以进一步地减小芯片封装结构的厚度。
具体地，若该互连通道为第一铜柱，该第一铜柱可以预先电镀在基板的第一表面。在一个实施例中，该第一铜柱的直径大于或等于100微米μm，且高度大于或等于100μm。此时，该芯片封装结构的厚度最小可以达到：300(170+30+100＝300)μm至400(170+30+200＝400)μm。
若该互连通道为第一铜柱和第一连接件，该第一铜柱的一端可以与露出于RDL的第一表面的金属布线相连，另一端可以通过第一连接件连接在基板的第一表面。其中，该第一连接件可以为以下任意一种：预涂锡膏或焊球，在一个实施例中，焊球的直径d1满足40μm＜d1≤100μm，该焊球可以为：例如，钎料球(solder ball)、钎料凸点(solder bump)、铜核钎料球(Cu-core solder ball，CCSB)或者可控坍塌芯片连接凸块(Controlled Collapse Chip Connection，C4)等，本申请对焊球的具体材料或形式不作限定。该第一铜柱的直径大于或等于100微米μm，且高度大于或等于100μm，该预涂锡膏的高度约为20μm。第一连接件和第一铜柱的高度可以根据实际需要来选择。计算可知，该芯片封装结构的厚度最小可以达到320μm。
若该互连通道为研磨焊球和第一连接件(如图3和4所示)，该研磨焊球的一端可以与露出于RDL的第一表面的金属布线相连，另一端可以通过第一连接件连接在基板的第一表面。在一个实施例中，该研磨焊球可以为直径为200μm的焊球，经过研磨，可以得到高度仅为100μm的半球形。其中，第一连接件可以为以下任意一种：第二铜柱、预涂锡膏或焊球。该第二铜柱的直径可以小于100μm，高度可以小于100μm，典型地，该第二铜柱的直径可以为40μm，高度可以为5μm～50μm。该焊球的直径可以大于或等于40μm，该预涂锡膏的高度可以为20μm。计算可知，该芯片封装结构的厚度最小可以达到305μm(第一连接件为高度为5μm的第二铜柱)或320μm(第一连接件为高度为20μm的预涂锡膏)。
当采用研磨焊球作为互连通道时，相比于现有技术中的压缩焊球而言，可以在减小厚度的同时，不增加对封装面积的占用。可以理解，在现有技术中，压缩焊球是通过热压方式来降低厚度的，热压造成焊球在纵向(即，第一方向)的尺寸减小的同时，在横 向(即，与第一方向垂直的方向)的尺寸增加。而本申请实施例采用研磨技术对焊球进行研磨，在减小纵向尺寸的同时并不会对横向尺寸造成影响。因此，相比于现有技术中的压缩焊球具有较大的优势。
应理解，以上列举的互连通道的具体材料和形式仅为示例性说明，不应对本申请构成任何限定，该互连通道也可以为其他等效的具有电气互连功能的结构。例如，垂直互连通道也可以是印制电路板块(PCB Bar)或硅通孔(Through Silicon Via，TSV)模块(Module)。PCB Bar为采用PCB技术制作的具有PCB通孔的模块。TSV Module为采用TSV技术在晶圆上制作TSV，再把晶圆切割成具有TSV的小模块。每个PCB Bar或TSV Module内包含一个或多个垂直互连通道。PCB Bar或TSV Module与目标芯片同样可以采用扇出型晶圆级封装技术经过晶圆重构与晶圆布线等工序整合封装在一起，也可以在外围和目标芯片之间的互连区域集成多颗PCB Bar或TSV Module。
因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，与现有技术相比，减小了基板加工工艺对封装结构的限制，从而达到减小整体厚度的效果，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备。同时，增大了管脚密度较小。另一方面，本申请实施例所使用的垂直互连通道可以避免了对互连通道的最小间距的限制，从而可以增加互连通道的密度，进而提高顶层芯片的带宽。再一方面，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
应理解，上文中结合图2详细说明了根据本申请实施例的芯片封装结构。但图2示出的结构仅为本申请实施例的一种可能的实现方式，而不应对本申请构成任何限定。例如，该芯片封装结构可以用两个RDL代替两个基板层，通过使用RDL可以减小结构的整体厚度，并提高管脚密度；或者，该芯片封装结构也可以用RDL代替上层基板，同时保留下层基板，同样可以达到减小结构的整体厚度的效果。
以下，为便于理解，结合芯片封装方法(包括封装方法一、封装方法二和封装方法三)来详细描述本申请实施例的芯片封装结构，但应理解，以下所示出的芯片封装方法仅为用于实现本申请实施例的芯片封装结构的一种可能的实现方式，而不应对本申请构成任何限定，本申请实施例也不应限于此。
封装方法一：
图5示出了根据本申请一实施例的芯片封装结构30的示意性结构图。如图5所示，该芯片封装结构30包括：基板31、MC 32、垂直互连通道33、RDL 34、目标芯片37和粘附材料38。其中，目标芯片37的焊盘36通过第二连接件35与露出在RDL 34(或者更具体地说，介电层)的第一表面的金属布线连接，具体地，目标芯片37的焊盘36可以通过第二连接件35与露出在RDL 34第一表面的金属布线连接，以实现与目标芯片的管脚之间的电气互连。
下面结合图6至图12详细说明该芯片封装结构30。图6至图12示出了通过一种芯片封装方法封装本申请一实施例的芯片封装结构30的示意图。
首先执行步骤1a：如图6所示，在载板(carrier)91上贴装基板31。在实际执行过程中，可以将多个基板按预设的间距贴装在载板上。
其中，载板可以是玻璃、陶瓷、金属或者其他具有相似功能且兼容圆片级封装工艺的材料。
可选地，载板上可以选择性涂覆结构薄膜或功能性薄膜，例如，粘附层薄膜(adhesive layer)、牺牲层薄膜(sacrificial layer)、缓冲层薄膜(buffer layer)、介电层薄膜(dielectric layer)等。更具体地，粘附层薄膜和牺牲层薄膜均可以是紫外线固化(Ultra-Violet，UV)胶，光热转换(light-to-heat conversion，LTHC)薄膜，或者具有相似功能且与圆片级工艺兼容的材料。介电层薄膜可以是聚酰亚胺(polyimide，PI)、聚苯并噁唑(PolyBenzoxazole，PBO)、苯并环丁烯(BenzoCycloButene，BCB)、日本味之素公司供应的一种环氧树脂绝缘膜(Ajinomoto Buildup Film，ABF)、抗阻焊剂薄膜(Solder Resist film，SR)，或者其他具有相似功能且与圆片级工艺兼容的材料。
本领域技术人员可以理解，载板与基板具有不同的功能，载板可以理解为在芯片封装过程中起支撑作用的载体，它不属于芯片封装结构，仅用于封装过程，并且，在完成相应的步骤后可以移除该载板。基板可以理解为该芯片封装结构的一部分，其中分布有电路，用于电气互连。为了简洁，后文中省略对相同或相似部分的说明。
在本申请实施例中，该基板31中预先植入了垂直互连通道33。具体地，垂直互连通道可以通过电镀的方式预先连接在基板31的第一表面焊盘上。其中，该基板(或者称为interposer)可以根据信号数目以及应用需求，选择为有机基板或者硅基基板。该互连通道可以是第一铜柱。应理解，使用铜柱作为垂直互连通道仅为一种可能的实现方式，该垂直互连通道还可以为铝或者其他具有等效电气互连功能的结构。
需要说明的是，基板31的第一表面、第二表面可以设置焊盘，基板可以通过第二表面的焊盘与载板连接，通过第一表面的焊盘与垂直互连通道连接。其中，焊盘可以以四周阵列或者面阵列的形式设置在基板的第一表面和第二表面。
其后，执行步骤1b：如图7和图8所示，在基板31的第一表面涂覆粘附材料38，并将目标芯片37贴合到基板31的第一表面。
通过涂覆粘附材料，使目标芯片能够固定在基板上，同时能够起到应力缓冲作用。
图7和图8示出的是选用不同的粘附材料的情况下的示意图。其中，图7示出的粘附材料38可以为银胶、DAF胶、PI等。即，在贴基板31之前，在目标芯片的背面涂覆粘附材料。
图8示出的粘附材料可以为TCNCP/TCNCF。即，在贴基板31之前，可以在基板31的第一表面或者MD的表面涂覆粘附材料38，在焊接基板31时，通过热压，TCNCP/TCNCF可以在实现保护芯片背面，并包裹连接件33(如图8所示)，以提高连接件33的可靠性的作用。
由图可以看到，目标芯片33完全贴合在基板31上。换句话说，目标芯片在第一平面的投影落入基板在第一平面的投影范围内。
在本申请实施例中，该目标芯片37的有源面包括多个焊盘36，焊盘36可以均匀地或者不均匀地分布在目标芯片的有源面。焊盘可以理解为目标芯片的管脚，实现目标芯片与外界的电气互连。
焊盘36可以焊接第二连接件35，该第二连接件35用于连接焊盘36与RDL 34中的金属布线。其中，该第二连接件可以为：C4、第三铜柱(Cu pillar)、铜凸垫(Cu post)或者其他具有等效电气互连功能的结构。该第二连接件可以通过植球、电镀、印刷等方式制备。
需要说明的是，这里所列举的第三铜柱的尺寸(包括直径和高度)的选取与上文中 所提及的第二铜柱尺寸的选取可以选用相同的范围。但这并不应构成限定，即，第二铜柱的尺寸与第二铜柱的尺寸可以是相同或者不同的。
可选地，各第二连接件之间可以填充缓冲材料。
具体地，该缓冲材料可以为底填料(Under Fill，UF)，或者是具有缓冲效果的介电层材料。当缓冲材料为介电层材料，该介电层材料可以的选取可以参考上文中所描述的载板上所涂覆的介电层薄膜的选取范围。
需要说明的是，在一个封装体中，可以集成单颗或多颗目标芯片。在实际执行过程中，可以将单颗或者多颗目标芯片(或者说，原始晶圆)贴合在基板的第一表面。当目标芯片的数量为多颗时，该多颗芯片可以是不同尺寸、不同类型、不同工艺制备的芯片，其具体的尺寸可以根据产品需要和工艺制程来决定，并根据需要对芯片进行研磨减薄。因此，本申请对于目标芯片的种类、尺寸、工艺并未特别限定。
还需要说明的是，在目标芯片的数量为单颗时，垂直互连通道可以分布在MC中，且位于目标芯片的外围；在目标芯片的数量为多颗时，垂直互连通道可以分布在MC中，且位于相邻的目标芯片之间的区域或者目标芯片的外围区域。
其后，执行步骤1c：如图9所示，填充MC 32，并研磨MC 32的第一表面。
将MC 32填充在基板31的第一表面，并包围目标芯片37的侧面，使得目标芯片的背面和侧面均与外界隔离，有源面则通过后文所述的步骤1d与RDL贴合。
其中，MC的填充高度至少高于目标芯片的有源面(即，图8中示出的位于上方的表面)。然后可以根据需要，对MC进行研磨以减薄MC，使得第二连接件35和垂直互连通道33能够从MC中露出。
对MC进行研磨可以使MC的第一表面变得平整，同时可以进一步减小芯片封装结构的厚度。
在本申请实施例中，可以根据芯片封装结构的预设厚度，研磨该MC。
即，根据该芯片封装结构所应用于的设备对该芯片封装结构的厚度要求，可以确定该芯片封装结构的厚度，进而通过研磨MC达到进一步减小芯片封装结构的效果。
在本申请实施例中，第二连接件35不仅起到连接目标芯片的焊盘与RDL的作用，还能够在研磨MC的过程中保护目标芯片、减小研磨过程对目标芯片的应力损伤。
可选地，第二连接件35之间可以填充缓冲材料(例如，UF)，以增加结构的强度和可靠性。
其后，执行步骤1d：如图10所示，制作RDL 34。
在步骤1c中得到的结构的表面涂覆介电层，在介电层的内部和表面，制备金属布线。其中，介电层材料的选取可以参考上文所述的载板上所涂覆的介电层薄膜的选取范围。RDL可以通过涂覆、曝光、显影、固化、溅射、电镀、刻蚀等工艺制备。金属布线的材料可以为铜、铝等导电材料。RDL可以为单层或多层布线层。
由图可以看到，RDL 34覆盖在目标芯片33以及目标芯片33周围的MC 32区域。换句话说，目标芯片在第一平面的投影落入RDL在第一平面的投影范围内。
在本申请实施例中，由于采用了扇出型工艺，可以将目标芯片的管脚扇出布线到目标芯片的区域以及外围区域，与金属布线相连。并且，对于多颗目标芯片的结构，通过扇出金属布线可以实现芯片与芯片之间的互连，RDL中的金属布线可实现与芯片管脚的电气互连。
其后，执行步骤1e：如图11所示，在RDL 34的表面制备第四连接件41。
由于该芯片封装结构用于安装在PCB上，因此可以在RDL的下表面制备第四连接件，以便于与PCB连接。具体地，该第四连接件可以为钎料球(solder ball)、CCSB，或者具有相似的电气连接功能的等效结构，并可以通过电镀、印刷、植球等方式制备。
可选地，在制备第四连接件之前，可以根据实际需求，选择性在第四连接件的下方与有机介电层接触的区域制备凸点下金属层(under bump metallization，UBM)结构，以提高结合强度，增强机械可靠性。。本申请对UBM的材料、结构、工艺不作限定。
通过上述步骤1a至步骤1e，得到如图11所示的结构，可以称为重构晶圆。
最后，执行步骤1f：如图12所示，将顶层芯片80通过第三连接件42连接在基板31的第二表面。
在本申请实施例中，顶层芯片的连接工艺可以为表面贴装技术(Surface Mount Technology，SMT)(方法一)，也可以为预堆叠技术(pre stack)(方法二)。
在方法一中，可以将步骤1e得到的重构晶圆(如图11所示)划片为单颗封装颗粒。在PCB上板时采用SMT工艺，将其贴在PCB上，然后将顶层芯片通过焊膏等方式贴在上述封装颗粒的基板上。最后经过一次回流，同时将顶层芯片和重构晶圆集成到PCB上。
在方法二中，在基板31的第二表面制备第三连接件42之前，可以先将上述步骤1e得到的重构晶圆(如图11所示)在垂直方向翻转，将重构晶圆的另一面贴合在载板92上，同时可以移除载板91。将重构晶圆贴合在载板92上所选取的薄膜材料可以参考步骤1a中的相关说明。
应理解，图12中所示的载板92与图6至图11中所示的载板91为不同的载板，或者说，不为同一个载板。也就是说，在本申请实施例中，使用到了两块载板。
然后，将顶层芯片80通过第三连接件42连接在基板31的第二表面。通常第三连接件42是预置在顶层芯片50上的。对于未预置连接件42的顶层芯片50，亦可先在基板31的第二表面制备第三连接件42，然后与顶层芯片50焊接。此时，该第三连接件42可以与基板的第二表面的焊盘互连，互连方式可以为：热风重熔(Mass Reflow)、热压键合(Thermo Compression Bonding)或者其他等效的焊接方式。
最后，移除载板92，并对得到的芯片封装结构进行划片得到单颗封装颗粒。划片后的单颗封装颗粒可以通过SMT贴合在PCB上，并回流实现焊接。
可选地，PCB与RDL之间可以填充缓冲材料，以增加结构的可靠性。
因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，减小了基板工艺对封装结构的限制，一方面，可以减小整体厚度，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备；同时可以增加管脚密度；另一方面，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了顶层芯片的带宽。并且，通过使用垂直互连通道代替热压焊球来实现电气互连，以及对MC进行研磨的方法，可以进一步减小厚度。同时，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
封装方法二：
图13示出了根据本申请另一实施例的芯片封装结构60的示意性结构图。需要说明的是，为便于理解，在以下示出的实施例中，对于不同实施例中示出的结构中，相同的结构仍采用相同的附图标记，并且为了简洁，省略对相同结构的详细说明。
如图13所示，该芯片封装结构50包括：基板31、MC 32、垂直互连通道33(包括第一铜柱(或研磨焊球)51和第一连接件52)、RDL 34、目标芯片37。其中，目标芯片37的焊盘36通过第二连接件35与露出在RDL 34的第一表面的金属布线连接，具体地，目标芯片37的焊盘36可以通过连接件35与露出在RDL 34的第一表面的金属布线焊接连接，以实现与目标芯片的管脚之间的电气互连。可选地，目标芯片与基板31的第一表面涂覆有粘附材料38，例如，DAF胶、PI等。该粘附材料同时具有应力缓冲作用。
与图5中示出的芯片封装结构30不同的是，在该芯片封装结构50中，垂直互连通道33通过第一铜柱(或研磨焊球)51、第一连接件52与基板31连接，这是由于该芯片封装结构50的封装工艺不同造成的。
下面结合图14至图25详细说明该芯片封装结构50。图14至图23示出了通过另一种芯片封装方法封装本申请另一实施例的芯片封装结构50的示意图。
首先执行步骤2a：如图14所示，在载板91上贴装RDL。
具体地，在载板91的上表面选择性涂覆薄膜材料，例如，可以为粘附层薄膜、牺牲层薄膜或者缓冲层薄膜。然后在薄膜上制备单层或多层RDL 34。其主要步骤包括溅射种子层、涂覆介电层、光刻、显影、高温固化、电镀、去种子层等步骤。RDL的第一表面可选择性制备UBM。载板91及其上表面的薄膜材料、介电层、金属布线的材料选取及其制备方法可以参考封装方法一。
其后，执行步骤2b：如图15和图16所示，在RDL 34的第一表面上制备垂直互连通道33。
在本申请实施例中，该垂直互连通道33可以包括第一铜柱(或者研磨焊球)51和第一连接件52。在该步骤中，首先制备第一铜柱(或者研磨焊球)51。
该垂直互连通道可以采用溅射种子层、干膜(dry film lamination)光刻、显影、固化、电镀、去胶、去种子层、塑封等工艺方法制备。也就是说，该垂直互连通道可以电镀在RDL的第一表面金属布线露出的位置。本申请实施例对垂直互连通道的结构和工艺不作限定。例如，垂直互连通道也可以采用激光钻孔或深反应离子刻蚀(Deep Reactive Ion Etching，DRIE)等方法在模塑料中制作垂直互连模封通孔(Through Molding Via，TMV)，然后用导电材料填充通孔实现垂直互连通道。通孔内导电材料可以是铜、铝、锡等金属，或者是导电胶，填充方式可以采用电镀，化学镀，点胶等方式。
其后，执行2c：如图17所示，在RDL 34上固定目标芯片37。
在固定目标芯片37之前，可以先在目标芯片37的焊盘36上制备好第二连接件35，然后将带有第二连接件35的目标芯片37上固定在RDL 34的第一表面，并通过回流实现第二连接件35与RDL 34中的金属布线之间的互连。可选地，第二连接件35之间可以涂覆缓冲材料(如UnderFill)或者类似介电层的薄膜材料。
其中，目标芯片、第二连接件及缓冲材料的材料选择及制备方法可以参考上文所述的实施例。需要注意的是，若第二连接件选用第二铜柱，则第二铜柱顶端需要含有锡基凸点(solder tip/cap)等易于焊接的材料，以提高第二连接件与RDL互连的可靠性。可选地，铜柱顶端可以添加镍(Ni)、钛(Ti)或者其它阻挡层金属以实现Cu和锡(Sn)的隔离。
其后，执行步骤2d：如图18至图20所示，填充MC 32，并研磨MC 32的上表面。
具体地，填充MC 32的具体方法可参考封装方法一。MC的填充高度高于填充MC 时目标芯片的表面最高点(即，图18中示出的位于上方的表面)。MC的填充高度也可以通过研磨减薄。MC的研磨厚度可以根据需要，通过研磨仅使第一铜柱(或研磨焊球)51露出MC 32的第一表面(如图19所示)，或者，也可以基于产品厚度或散热的需求可做成外露芯片(Exposed Die)，即，通过研磨MC的第一表面直至目标芯片的背面露出在MC的第一表面(如图20所示)，或者继续研磨MC和目标芯片的背面以实现MC和目标芯片同时减薄。
通过上述步骤得到的结构，可以称为重构晶圆。
其后，执行步骤2e：如图21所示，贴基板31。
具体地，在贴基板31之前，可以在基板31的第一表面涂覆应力缓冲层38(例如，DAS、PI等)，然后将基板31通过第一连接件52焊接在图19或图20所示结构的上表面(即，目标芯片背面的位置)，第一连接件52通过基板第一表面的焊盘与第一铜柱(或者研磨焊球)51互连，构成垂直互连通道33。
具体地，在垂直互连通道51采用研磨焊球的情况下，该第一连接件可以为第二铜柱(如图3中所示)或者预涂锡膏(pre-solder)(如图4中所示)。第一连接件可以先制备在基板31的第一表面的焊盘上，或者先制备在垂直互连通道的与基板接触的表面。其中预涂锡膏可以采用印刷的工艺制备，第二铜柱可以采用电镀的方法制备。在垂直互连通道51采用第一铜柱的情况下，第一连接件为预涂锡膏或者焊球(如图20中所示)。焊球可以预先焊接在基板下表面的焊盘上，或者预先焊接在第二铜柱上。其中，焊球可以为钎料球(Solder Ball)、钎料凸点(Solder Bump)、CCSB、C4，或者其他等效的具有电气互连功能的结构。
根据第一连接件与基板的第一表面连接方式的不同，可以相应地调整基板的焊接顺序。若第一连接件预先连接在基板的第一表面，则可以将第一连接件直接与重构晶圆焊接；若第一连接件预先连接在垂直互连通道(或者说，预先制备在重构晶圆上)，则可以将第一连接件与基板第一表面的焊盘焊接。
可选地，基板与MC之间可以填充应力缓冲层，以增强结构的可靠性。
图21和图22示出的是选用不同的粘附材料的情况下的示意图。其中，图21示出了粘附材料未包裹互连通道的示意图。图21示出的粘附材料38可以为银胶、DAF胶、PI等中的一种或多种。即，在贴基板31之前，在目标芯片的背面涂覆粘附材料。
图22示出了粘附材料包裹互连通道的示意图。其中，该粘附材料可以为银胶、DAF胶、PI、TCNCP、TCNCF等中的一种或多种。
作为一个实施例，可以先将DAF贴于目标芯片37的背面，同时在MC 32的第一表面与目标芯片37的四周相对应的区域涂覆其他粘附材料，例如，银胶。另一方面，在贴基板31之前，该第一连接件52可以预先焊接在基板31的第一表面，在贴基板1时，可以实现该第一连接件52与互连通道51的对接，通过回流完成焊接；同时，通过热压可以使粘附材料38变形，均匀地包裹第一连接件52(如图22所示)，以实现保护目标芯片背面，提高第一连接件52的可靠性的作用。
作为另一个实施例，在贴基板31之前，可以在基板31的第一表面或者MD的表面涂覆TCNCP或TCNCF。另一方面，在贴基板31之前，该第一连接件52可以预先焊接在基板31的第一表面；在焊接基板31时，通过热压，实现第一连接件52与互连通道51对接的同时，使TCNCP/TCNCF变形，包裹第一连接件52(如图22所示)，以实现保 护目标芯片背面，并提高第一连接件52的可靠性的作用。其后，执行步骤2f：在RDL 34的第二表面制备第四连接件41，然后连接顶层芯片80；或者，
步骤2g：在基板31的第二表面通过第三连接件42连接顶层芯片80，然后在RDL 34的第二表面制备第四连接件41。步骤2f和2g可以采用预堆叠技术或SMT实现。
若采用预堆叠技术，可以选择先在RDL的第二表面上制备第四连接件41，然后安装顶层芯片80(方法a)；也可以选择先在基板的第二表面上安装顶层芯片80，然后在RDL的第二表面上制备第四连接件41(方法b)。
具体地，在方法a中，可以先将经上述步骤2e得到的结构翻转至载板92上，使RDL的第二表面朝上，然后在RDL的第二表面制备第四连接件41(如图23所示)。第四连接件的材料和制备方法可以参考封装方法一。然后将该结构翻转至载板93，使基板层的第二表面朝上，安装顶层芯片(如图24所示)。具体过程可以参考封装方法一。
在方法b中，可以先在基板的第二表面上安装顶层芯片80，具体过程可以参考封装方法一。然后将安装了顶层芯片的结构翻转至载板92上，使RDL的第二表面朝上，在RDL的第二表面制备第四连接件41(如图25所示)。第四连接件的材料和制备方法可以参考封装方法一。
若采用SMT，可以先将上述步骤2e得到的结构翻转至载板92上，使RDL 34的第二表面朝上，制备第四连接件41(可以参看图23)，然后划片成单颗封装颗粒。最后在PCB上板时通过SMT技术，将上述划片的封装颗粒固定在PCB上，然后将顶层芯片80固定在基板31的第二表面的上方，通过一次回流将封装颗粒和顶层芯片焊接在PCB上。
应理解，上述示例的各种封装顶层芯片的方法仅为示例性说明，不应对本申请构成任何限定，本申请并不排除通过其他现有的或未来的技术来封装顶层芯片。
因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，减小了基板工艺对封装结构的限制，一方面，可以减小整体厚度，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备；同时可以增加管脚密度；另一方面，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了顶层芯片的带宽。并且，通过使用垂直互连通道代替热压焊球来实现电气互连，以及对MC和目标芯片进行研磨的方法，可以进一步减小厚度。同时，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
封装方法三：
图26示出了根据本申请又一实施例的芯片封装结构60的示意性结构图。
如图26所示，该芯片封装结构60包括：基板31、MC 32、垂直互连通道33(包括第一铜柱(或研磨焊球)51和第一连接件52)、RDL 34、目标芯片37。其中，目标芯片37的焊盘36与露出在RDL 34上表面的金属布线连接。与图13中示出的芯片封装结构60不同的是，在该芯片封装结构60中，目标芯片37的焊盘36可以直接与露出在RDL34上表面的金属布线焊接连接，以实现与目标芯片的管脚之间的电气互连。这是由于该芯片封装结构60的封装工艺不同造成的。
可选地，目标芯片与基板31的第一表面涂覆有粘附材料38，例如，DAF胶、PI等。该粘附材料同时起到应力缓冲作用。
下面结合图27至图30详细说明该芯片封装结构60。图27至图30示出了通过又一种芯片封装方法封装本申请又一实施例的芯片封装结构60的示意图。
首先执行步骤3a：如图27所示，制备垂直互连通道33。
在本申请实施例中，该垂直互连通道33可以包括第一铜柱(或者研磨焊球)51和第一连接件52。在该步骤中，首先制备第一铜柱(或者研磨焊球)51。
本申请实施例中的垂直互连通道33可以与封装方法二的垂直互连通道33所选用的材料相同。在本申请实施例中，第一铜柱(或者研磨焊球)51可以直接在载板91上制备，具体地，在载板91上先制备粘附层、缓冲层、种子层等。然后通过干膜光刻-电镀-去胶-去种子层等步骤制备第一铜柱(或者研磨焊球)51。
其后，执行步骤3b：如图28所示，在载板91上固定目标芯片37。
在本申请实施例中，直接将单颗或者多颗目标芯片37贴于上述载板91上表面，目标芯片37的有源面朝下与载板91的上表面相对，即目标芯片的管脚通过焊盘引出。然后填充MC 32，以将目标芯片与外界隔离，并根据需要研磨MC，或者，MC和目标芯片，以减薄该芯片封装结构，或者，将目标芯片37的背面漏出表面(即，Exposed Die)。MC的填充高度和封装高度可以参考封装方法一。
上述步骤得到的结构可以称为重构晶圆。
其后，执行步骤3c：如图29所示，在MC 32的第二表面上固定基板31。
具体地，可以将重构晶圆与基板31之间通过第一连接件52(即，垂直互连通道33的一部分)互连。可选地，在基板31与MC32之间可以填充缓冲材料。具体过程可参考封装方法二。
其后，执行步骤3d：如图30所示，制备RDL 34。
具体地，可以先将上述步骤3c中得到的结构翻转至载板92，去除载板91及MC 32之间的粘附层、缓冲层等结构。翻转后的结构目标芯片的背面朝上，并与MC的第二表面平齐。在该表面上涂覆介电层并制备单层或多层RDL，然后在RDL的第二表面上制备第四连接件41。
最后，执行步骤3e：固定顶层芯片80。
具体可参考封装方法一和封装方法二。
因此，本申请实施例的芯片封装结构，通过RDL代替下层基板，减小了基板工艺对封装结构的限制，一方面，可以减小整体厚度，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备；同时可以增加管脚密度；另一方面，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了顶层芯片的带宽。并且，通过使用垂直互连通道代替热压焊球来实现电气互连，以及对MC进行研磨的方法，可以进一步减小厚度。同时，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
图31是根据本申请再一实施例的芯片封装结构70的示意性结构图。如图31所示，该芯片封装结构70包括：第一基板31、第二基板43、MC 32、垂直互连通道33、目标芯片37和粘附材料38。其中，目标芯片37的焊盘36通过第二连接件35与第二基板43的第一表面焊接连接，以实现目标芯片的管脚与第二基板之间的电气互连。
其中，该垂直互连通道包括研磨焊球和第一连接件，该研磨焊球通过第第一连接件连接于该第二基板的第一表面；
该互连通道与该第一基板的上表面焊接接触。
芯片封装结构70的具体结构、封装方法以及互连通道与基板之间的连接方式可以参 考现有技术中的基板级工艺，为了简洁，这里不再赘述。
因此，本申请实施例的芯片封装结构，通过使用垂直互连通道代替热压焊球来实现电气互连，可以减小该芯片封装结构的厚度，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了顶层芯片的带宽，同时很好地控制了翘曲。
以上，结合图2至图31详细说明了本申请实施例的芯片封装结构。应理解，上述芯片封装结构可以单独使用，也可以用于堆叠三维芯片封装结构。
图32示出了根据本申请一实施例的三维芯片封装结构100的示意性结构图。
如图32所示，该三维芯片封装结构100包括：上封装层200、下封装层300。其中，上封装层200可以包括上文中所描述的顶层芯片80和第三连接件42，下封装层300可以包括上文中所描述的芯片封装结构30、50、60或70中的任意一种或多种，下封装层200还可以包括其他形式的芯片封装结构，本申请对此并未特别限定。
具体地，该三维芯片封装结构可以包括N个芯片封装结构。以第一平面为参照，该N个芯片封装结构按照由下至上的顺序垂直堆叠，第i层芯片封装结构的目标芯片与第i+1层芯片封装结构的目标芯片之间电气互连。其中，N为三维芯片封装结构所包括的芯片封装结构的总层数，N为大于1的自然数，i∈[1，N-1]，且i为自然数。
因此，本申请实施例的三维芯片封装结构，通过使用本申请实施例的芯片封装结构，可以在总体上减小三维芯片封装结构的整体厚度。
以上，结合图2至图32详细说明了本申请实施例的芯片封装结构和三维芯片封装结构。以下，结合图33至图35详细说明本申请实施例的芯片封装方法。
图33是根据本申请一实施例的芯片封装方法400的示意性流程图。如图33所示，该方法400包括：
S410，在基板的第一表面上连接互连通道，该互连通道的一端与该基板的第一表面相连；
S420，在该基板的第一表面上连接目标芯片，该目标芯片的背面与该基板的第一表面相对；
S430，制备重布线层RDL，该RDL与该互连通道的另一端相连，该RDL的第一表面与该目标芯片的有源面连接。
应理解，本申请实施例的芯片封装方法400在上文所描述的封装方法一中已经结合图5至图12详细说明，为了简洁，这里不再赘述。
图34是根据本申请另一实施例的芯片封装方法的示意性流程图。如图34所示，该方法500包括：
S510，制备重布线层RDL；
S520，在该RDL的第一表面连接互连通道，该互连通道的一端与该RDL的第一表面相连；
S530，在该RDL的第一表面上连接目标芯片，该目标芯片的有源面与该RDL的第一表面连接；
S540，在该目标芯片的背面放置基板，该基板的第一表面与该互连通道的另一端相连。
应理解，本申请实施例的芯片封装方法500在上文所描述的封装方法二中已经结合图13至图25详细说明，为了简洁，这里不再赘述。
图35是根据本申请再一实施例的芯片封装方法的示意性流程图。如图35所示，该方法600包括：
S610，在第一载板的第一表面连接互连通道；
S620，在该第一载板的第一表面上连接目标芯片，该目标芯片的有源面与该第一载板的第一表面至少部分接触；
S630，在该目标芯片的背面放置基板，该基板的第一表面与该互连通道的一端相连；
S640，移除该第一载板，以露出该目标芯片的有源面；
S650，在该目标芯片的有源面上制备重布线层RDL，该RDL的第一表面与该互连通道的另一端相连，且该RDL的第一表面与该目标芯片的有源面至少部分接触。
应理解，本申请实施例的芯片封装方法600在上文所描述的封装方法二中已经结合图26至图30详细说明，为了简洁，这里不再赘述。其中，第一载板可以对应于封装方法二中的载板91，第一载板的第一表面可以对应于封装方法二中的载板91的上表面。
因此，本申请实施例的芯片封装方法，通过RDL代替下层基板，减小了基板工艺对封装结构的限制，一方面，可以减小整体厚度，使得该芯片封装结构能够更多地应用于对厚度要求较高的终端设备；同时可以增加管脚密度；另一方面，在封装面积不变的情况下，增加了垂直互连通道的数量，从而提高了顶层芯片的带宽。并且，通过使用垂直互连通道代替热压焊球来实现电气互连，以及对MC进行研磨的方法，可以进一步减小厚度。同时，在该芯片封装结构中，仍然保留有上层基板，可以很好地将该芯片封装结构的翘曲程度控制在可接受的范围内。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
还应理解，上述列举的芯片封装方法的各实施例，可以通过机器人或者数控加工方式来执行，用于执行芯片封装方法的设备软件或工艺可以通过执行保存在存储器中的计算机程序代码来执行上述芯片封装方法。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个 网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种芯片封装结构，其特征在于，包括：
    重布线层RDL；
    目标芯片，包括有源面和背面，所述目标芯片的有源面与所述RDL的第一表面连接；
    基板，所述基板的第一表面与所述目标芯片的背面相对；
    互连通道，位于所述目标芯片的四周，所述互连通道的一端与所述RDL的第一表面相连，所述互连通道的另一端与所述基板的第一表面相连。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述互连通道包括第一铜柱。
  3. 根据权利要求1所述的芯片封装结构，其特征在于，所述互连通道包括研磨焊球和第一连接件，所述研磨焊球的一端与所述RDL连接，所述研磨焊球的另一端通过所述第一连接件与所述基板的第一表面连接，
    所述研磨焊球包括钎料球，所述第一连接件包括以下任意一种：第二铜柱、预涂锡膏或焊球。
  4. 根据权利要求1所述的芯片封装结构，其特征在于，所述互连通道包括第一铜柱和第一连接件，所述第一铜柱的一端与所述RDL连接，所述第一铜柱的另一端通过所述第一连接件与所述基板的第一表面连接，
    所述第一连接件包括预涂锡膏或焊球。
  5. 根据权利要求1至4中任一项所述的芯片封装结构，其特征在于，所述RDL包括金属布线，所述目标芯片的有源面包括焊盘，所述焊盘与露出于所述RDL的第一表面的金属布线连接。
  6. 根据权利要求5所述的芯片封装结构，其特征在于，所述芯片封装结构还包括第二连接件，所述第二连接件的一端与所述焊盘连接，所述第二连接件的另一端与露出于所述RDL的第一表面的金属布线连接。
  7. 根据权利要求1至6中任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括模塑料MC，所述MC填充于所述RDL与所述基板之间，并从所述目标芯片的四周包围所述目标芯片，所述互连通道沿第一方向贯穿于所述MC，所述第一方向与所述RDL的第一表面基本垂直；
    其中，所述MC为可研磨材料。
  8. 根据权利要求1至7中任一项所述的芯片封装结构，其特征在于，所述基板的第一表面与所述目标芯片的背面之间涂覆有粘附材料，所述粘附材料包括以下至少一种：热压非导电胶、热压非导电膜、芯片粘接薄膜或银胶。
  9. 一种三维芯片封装结构，其特征在于，包括至少一层如权利要求1至8中任一项所述的芯片封装结构。
  10. 一种芯片封装方法，其特征在于，包括：
    在基板的第一表面上连接互连通道，所述互连通道的一端与所述基板的第一表面相连；
    在所述基板的第一表面上连接目标芯片，所述目标芯片的背面与所述基板的第一表面相对；
    制备重布线层RDL，所述RDL与所述互连通道的另一端相连，所述RDL的第一表面与所述目标芯片的有源面连接。
  11. 根据权利要求10所述的芯片封装方法，其特征在于，所述互连通道包括第一铜柱，以及，
    所述在基板的第一表面上连接互连通道，包括：
    在所述基板的第一表面电镀所述第一铜柱。
  12. 根据权利要求10或11所述的芯片封装方法，其特征在于，在所述制备RDL之前，所述芯片封装方法还包括：
    在所述基板的第一表面上填充模塑料MC，以使所述MC从所述目标芯片的四周包围所述目标芯片，
    其中，所述目标芯片的有源面包括焊盘，所述焊盘预先连接第二连接件的一端，所述第二连接件的另一端露出于所述MC的第一表面，所述互连通道沿第一方向贯穿于所述MC，所述第一方向与所述RDL的第一表面基本垂直。
  13. 根据权利要求12所述的芯片封装方法，其特征在于，所述芯片封装方法还包括：
    根据所述芯片封装结构的预设厚度，研磨所述MC的第一表面。
  14. 根据权利要求10至13中任一项所述的芯片封装方法，其特征在于，所述RDL包括金属布线，所述目标芯片的有源面包括焊盘，所述焊盘预先连接第二连接件的一端，所述芯片封装方法还包括：
    将所述第二连接件的另一端与露出于所述RDL的第一表面的金属布线连接，以使所述金属布线与所述目标芯片的有源面连接。
  15. 一种芯片封装方法，其特征在于，包括：
    制备重布线层RDL；
    在所述RDL的第一表面连接互连通道，所述互连通道的一端与所述RDL的第一表面相连；
    在所述RDL的第一表面上连接目标芯片，所述目标芯片的有源面与所述RDL的第一表面连接；
    在所述目标芯片的背面放置基板，所述基板的第一表面与所述互连通道的另一端相连。
  16. 根据权利要求15所述的芯片封装方法，其特征在于，所述互连通道包括研磨焊球和第一连接件，所述研磨焊球包括钎料球，所述第一连接件包括：第二铜柱、预涂锡膏或焊球，
    所述在所述RDL的第一表面连接互连通道，包括：
    通过所述研磨焊球的一端与所述RDL的第一表面连接；
    通过所述研磨焊球的另一端与所述第一连接件的一端连接；
    所述芯片封装方法还包括：
    通过所述研磨焊球的另一端通过所述第一连接件与所述基板的第一表面连接。
  17. 根据权利要求15所述的芯片封装方法，其特征在于，所述互连通道包括第一铜柱和第一连接件，所述第一连接件包括预涂锡膏或焊球，
    所述在所述RDL的第一表面连接互连通道，包括：
    通过所述第一铜柱的一端与所述RDL的第一表面连接；
    通过所述第一铜柱的另一端与所述第一连接件的一端连接；
    所述芯片封装方法还包括：
    通过所述第一连接件的另一端与所述基板的第一表面连接。
  18. 根据权利要求15至17中任一项所述的芯片封装方法，其特征在于，所述RDL包括金属布线，所述目标芯片的有源面包括焊盘，所述焊盘预先连接第二连接件的一端，所述芯片封装方法还包括：
    将所述第二连接件的另一端与露出于所述RDL的第一表面的金属布线连接，以使所述金属布线与所述目标芯片的有源面连接。
  19. 根据权利要求15至18中任一项所述的芯片封装方法，其特征在于，在所述目标芯片的背面放置基板之前，所述芯片封装方法还包括：
    在所述RDL的第一表面上填充模塑料MC，以使所述MC从所述目标芯片的四周包围所述目标芯片，所述目标芯片的背面露出于所述MC的第二表面，所述互连通道沿第一方向贯穿于所述MC，所述第一方向与所述RDL的第一表面基本垂直。
  20. 根据权利要求19所述的芯片封装方法，其特征在于，所述芯片封装方法还包括：
    根据所述芯片封装结构的预设厚度，研磨所述MC的第二表面。
  21. 一种芯片封装方法，其特征在于，包括：
    在第一载板的第一表面连接互连通道；
    在所述第一载板的第一表面上连接目标芯片，所述目标芯片的有源面与所述第一载板的第一表面至少部分接触；
    在所述目标芯片的背面放置基板，所述基板的第一表面与所述互连通道的一端相连，其中，所述目标芯片的背面为所述目标芯片上与所述有源面相平行的面；
    移除所述第一载板，以露出所述目标芯片的有源面；
    在所述目标芯片的有源面上制备重布线层RDL，所述RDL的第一表面与所述互连通道的另一端相连，且所述RDL的第一表面与所述目标芯片的有源面至少部分接触。
  22. 根据权利要求21所述的芯片封装方法，其特征在于，所述互连通道包括研磨焊球和第一连接件，所述研磨焊球包括钎料球，所述第一连接件包括：第二铜柱、预涂锡膏或焊球，所述芯片封装方法还包括：
    通过所述第一连接件的一端与所述基板的第一表面连接；
    通过所述第一连接件的另一端与所述研磨焊球的一端连接；
    通过所述研磨焊球的另一端与所述RDL的第一表面连接。
  23. 根据权利要求21所述的芯片封装方法，其特征在于，所述互连通道包括第一铜柱和第一连接件，所述第一连接件包括预涂锡膏或焊球，所述芯片封装方法还包括：
    通过所述第一连接件的一端与所述基板的第一表面连接；
    通过所述第一连接件的另一端与所述第一铜柱的一端连接；
    通过所述第一铜柱的另一端与所述RDL的第一表面连接。
  24. 根据权利要求21至23中任一项所述的芯片封装方法，其特征在于，所述RDL包括金属布线，所述目标芯片的有源面包括焊盘，所述芯片封装方法还包括：
    将所述焊盘与露出于所述RDL的第一表面的金属布线焊接，以使所述金属布线与所述目标芯片的有源面连接。
  25. 根据权利要求21至24中任一项所述的芯片封装方法，其特征在于，在所述目标芯片的背面放置基板之前，所述芯片封装方法还包括：
    在所述载板的第一表面上填充模塑料MC，以使所述MC从所述目标芯片的四周包 围所述目标芯片和所述目标芯片的背面，所述互连通道沿第一方向贯穿于所述MC，所述第一方向与所述RDL的第一表面垂直。
  26. 根据权利要求25所述的芯片封装方法，其特征在于，所述芯片封装方法还包括：
    根据所述芯片封装结构的预设厚度，研磨所述MC的第一表面，所述MC的第一表面与所述基板的第一表面相对。
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