WO2017188269A1 - 半導体パッケージおよびそれを用いた半導体装置 - Google Patents

半導体パッケージおよびそれを用いた半導体装置 Download PDF

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Publication number
WO2017188269A1
WO2017188269A1 PCT/JP2017/016419 JP2017016419W WO2017188269A1 WO 2017188269 A1 WO2017188269 A1 WO 2017188269A1 JP 2017016419 W JP2017016419 W JP 2017016419W WO 2017188269 A1 WO2017188269 A1 WO 2017188269A1
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WO
WIPO (PCT)
Prior art keywords
base
semiconductor package
terminal
wiring board
signal terminal
Prior art date
Application number
PCT/JP2017/016419
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English (en)
French (fr)
Japanese (ja)
Inventor
白崎　隆行
Original Assignee
京セラ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to CN201780024399.9A priority Critical patent/CN109075527B/zh
Priority to KR1020187029979A priority patent/KR102164911B1/ko
Priority to JP2018514634A priority patent/JP6849670B2/ja
Publication of WO2017188269A1 publication Critical patent/WO2017188269A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0239—Combinations of electrical or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Definitions

  • the present invention relates to a semiconductor package for housing a semiconductor element used in the field of optical communication and the like and a semiconductor device using the same.
  • the semiconductor device is composed of a semiconductor package and semiconductor elements such as LD (Laser Diode) and PD (Photo Diode) (see Japanese Patent Application Laid-Open No. 2011-119634).
  • LD Laser Diode
  • PD Photo Diode
  • the semiconductor package according to the embodiment of the present invention includes a base, a signal terminal, a wiring board, and a ground terminal.
  • the base has a through hole penetrating in the thickness direction.
  • the signal terminal is provided in the through hole.
  • the wiring board is provided with a ground conductor layer on the upper surface between the lower surface of the base and a line conductor connected to the signal terminal so as to overlap the ground conductor layer on the lower surface.
  • the ground terminal penetrates the wiring board and is connected to the ground conductor layer.
  • the ground terminal is provided at a distance less than a quarter of the wavelength of the high-frequency signal transmitted through the line conductor from the position overlapping the outer edge of the base.
  • a semiconductor device includes a semiconductor package according to an embodiment of the present invention having the above-described configuration, a semiconductor element mounted in the semiconductor package, and a lid bonded to the base body of the semiconductor package. And.
  • FIG. 1A and 1B are perspective views illustrating a semiconductor package according to an embodiment of the present invention, in which FIG. 1A is a perspective view from the top surface and FIG. 1B is a perspective view from the bottom surface.
  • FIG. 2A is a perspective view showing a semiconductor package according to an embodiment of the present invention
  • FIG. 2A is a perspective view from above
  • FIG. 2B is a perspective view from below.
  • 3A is a plan view of a wiring board of the semiconductor package according to the embodiment of the present invention shown in FIG. 1
  • FIG. 3A is a plan view of the upper surface of the wiring board
  • FIG. 3B is a plan view of the lower surface of the wiring board.
  • FIG. 2 is a top perspective view of the semiconductor package according to the embodiment of the present invention shown in FIG. 1.
  • FIG. 2 is a bottom perspective view of the semiconductor package according to the embodiment of the present invention shown in FIG. 1. It is a perspective view which shows the semiconductor package which concerns on other embodiment of this invention. It is a perspective view showing a semiconductor package concerning one embodiment of the present invention. It is a perspective view which shows the semiconductor device which concerns on other embodiment of this invention.
  • FIG. 1 is a perspective view of a semiconductor package 1 according to an embodiment of the present invention
  • FIG. 1A is a perspective view showing an upper surface side of the semiconductor package 1 according to an embodiment of the present invention
  • FIG. 1B is a perspective view showing the lower surface side of the semiconductor package 1 according to one embodiment of the present invention
  • 2 is a perspective view of the semiconductor package 1 according to the embodiment of the present invention shown in FIG. 1 when each terminal is fixed with solder or the like, and FIG. 2A shows the upper surface side.
  • FIG. 2B is a perspective view showing the lower surface side.
  • 3 is a plan view of the wiring board 4, FIG. 3 (a) is a top plan view, and FIG. 3 (b) is a bottom plan view.
  • a semiconductor package 1 according to an embodiment of the present invention includes a base 2, a signal terminal 3, a wiring board 4, and a ground terminal 5.
  • the base body 2 has a through hole 21 that penetrates in the thickness direction, as shown in FIG.
  • the base 2 is made of, for example, a metal having good thermal conductivity.
  • the base 2 can dissipate heat generated from the semiconductor element to the outside of the semiconductor package 1 when the semiconductor device operates.
  • the base 2 is close to the thermal expansion coefficient of the semiconductor element to be mounted and the internal wiring board 9 connected to the base 2.
  • the substrate 2 is made of, for example, an iron-based alloy such as an Fe—Ni—Co alloy or an Fe—Mn alloy, or a metal such as pure iron. More specifically, there is an SPC (Steel Plate Cold) material of Fe 99.6 mass% -Mn 0.4 mass%.
  • the shape of the substrate 2 is, for example, a circular shape, a semicircular shape, a rectangular shape, etc. in plan view.
  • the substrate 2 is, for example, a flat plate having a thickness of 0.5 mm to 2 mm, a circular shape having a diameter of 3 mm to 10 mm, a semicircular shape obtained by cutting a part of a circumference having a radius of 1.5 mm to 8 mm, and a side of 3 mm.
  • the thickness of the base body 2 may not be uniform. For example, if the thickness of the outer side of the base body 2 is increased, a heat sink such as a housing for housing a semiconductor device can be easily adhered. The generated heat is easily released to the outside through the substrate 2.
  • the thickness of the substrate 2 is 0.5 mm or more, when the lid for protecting the semiconductor element is bonded to the upper surface of the substrate 2, the substrate 2 is difficult to be deformed such as bending due to bonding conditions such as a bonding temperature. Become. Moreover, when the thickness of the base 2 is 2 mm or less, the semiconductor package 1 and the semiconductor device can be prevented from being enlarged. That is, the semiconductor package 1 and the semiconductor device can be reduced in size.
  • the surface of the base 2 has excellent corrosion resistance, excellent wettability with the brazing material for bonding and fixing the internal wiring board 9 or the lid, and a Ni layer having a thickness of 0.5 ⁇ m to 9 ⁇ m and a thickness.
  • An Au layer having a thickness of 0.5 ⁇ m to 5 ⁇ m is preferably sequentially deposited by a plating method. Thereby, it is possible to effectively prevent the base 2 from being oxidatively corroded and to favorably bond the internal wiring board 9 or the lid to the base 2.
  • the signal terminal 3 is provided in the 1st through-hole 21 of the base
  • one end 32 of the signal terminal 3 is formed from the lower surface of the wiring board 4 through a second through hole 43 provided at a position overlapping the line conductor 42 of the wiring board 4, which will be described later.
  • the other end 31 protrudes from the upper surface of the base 2 by about 1 mm to 20 mm and is fixed.
  • the other end 31 of the signal terminal 3 and the signal line 91 provided on the internal wiring board 9 are electrically connected by a conductive bonding material, and the semiconductor element 7 is conductive.
  • the signal terminal 3 fulfills a function of inputting and outputting a high frequency signal between the semiconductor element 7 and the external electric circuit.
  • the signal terminal 3 is made of, for example, an Fe—Ni—Co alloy, an Fe—Mn alloy, SUS, or an SPC material. Since the signal terminal 3 is made of such a material, it is possible to suppress thermal stress caused by a difference in thermal expansion coefficient between the base 2 and the fixing member 23 and to transmit a high-frequency signal satisfactorily over a long period of time. be able to.
  • the signal terminal 3 has a diameter of 0.2 mm to 2 mm, for example.
  • a sealing material 22 is provided between the base 2 and the signal terminal 3 to ensure insulation between the base 2 and the signal terminal 3 and to fix the signal terminal 3 in the through hole 21 of the base 2. It has been.
  • the sealing material 22 is made of an insulating inorganic material such as glass or ceramics.
  • Such a sealing material 22 includes, for example, glass such as borosilicate glass and soda glass and those glass added with a ceramic filler for adjusting the thermal expansion coefficient and relative dielectric constant of the sealing material.
  • the relative dielectric constant is appropriately selected for impedance matching. Examples of the filler that lowers the dielectric constant include lithium oxide.
  • the diameter of the first through hole 21 is 0.75 mm when the outer diameter of the signal terminal 3 is 0.25 mm.
  • the characteristic impedance can be set to 25 ⁇ .
  • the characteristic impedance is 25 ⁇ by setting the diameter of the through hole 21 to 0.64 mm. By setting the diameter of the through hole 21 to 1.62 mm, the characteristic impedance can be set to 50 ⁇ .
  • the diameter of the signal terminal 3 is, for example, 0.15 mm to 0.25 mm.
  • the diameter of the signal terminal 3 is 0.15 mm or more, the signal terminal 3 is difficult to bend in handling when the semiconductor package 1 is mounted. Further, when the diameter is 0.25 mm or less, the impedance can be reduced even if impedance matching is performed.
  • a wiring substrate 4 is provided on the lower surface of the base 2.
  • the wiring substrate 4 is made of a ceramic insulating material such as an aluminum oxide (alumina: Al 2 O 3 ) sintered body and an aluminum nitride (AlN) sintered body, or a base having insulating properties and flexibility. It consists of a flexible substrate or the like in which an electric circuit is formed by bonding a conductive metal such as copper foil to a film. In plan view, for example, one end is provided in a semicircular shape so as to overlap the outer shape of the base 2, and the other end is provided in a rectangular shape and connected to an external electric circuit.
  • the wiring board 4 has a length from one end to the other end of 5 mm ⁇ 50 mm, a length in the width direction perpendicular to the direction from the one end to the other end, 3 mm ⁇ 10 mm, and a thickness of 0.1 mm to 1 mm.
  • the wiring board 4 is provided with a ground conductor layer 41 between the upper surface, that is, the lower surface of the substrate 2, and a line conductor 42 is formed on the lower surface.
  • the thickness of the wiring board 4 is approximately the same as the distance between the outer surface of the signal terminal 3 and the inner surface of the through hole 21. More specifically, the thickness of the insulating substrate, which is the dielectric of the wiring substrate 4, is the distance between the outer surface of the signal terminal 3 and the inner surface of the through hole 21, that is, the dielectric between the signal terminal 3 and the through hole 21. It is about the same as the thickness of the sealing material 22. If the thickness of the wiring board 4 is ⁇ 20% of the thickness of the sealing material 22, as described above, the propagation mode in the course of conversion from the coaxial structure to the microstrip structure is prevented from being stably radiated. be able to.
  • a ground conductor layer 41 is provided on the upper surface of the wiring board 4.
  • the ground conductor layer 41 is made of, for example, gold, silver, nickel, copper, or the like.
  • the ground conductor layer 41 has, for example, a width of 0.05 mm to 1 mm and a thickness of 0.01 mm to 0.5 mm. The length is 5 mm to 50 mm.
  • the ground conductor layer 41 serves as a ground and can be set to a reference potential.
  • the line conductor 42 is provided on the lower surface of the wiring board 4 so as to overlap the ground conductor layer 41.
  • the microstrip structure enables smooth transmission of high-frequency signals.
  • the line conductor 42 can input a high-frequency signal from the external electric circuit to the semiconductor element via the signal terminal 3, for example.
  • the ground conductor layer 41 is provided with a non-formation region 41a where the ground conductor layer 41 is not provided at a position overlapping the line conductor 42 in plan view.
  • the semiconductor package 1 of this embodiment can reduce the electrostatic capacitance of the line conductor 42 and the grounding conductor layer 41, and can improve the fall of the characteristic impedance in the line conductor 42.
  • the line conductor 42 is formed accordingly.
  • the line conductor 42 and the external electric circuit are connected by, for example, solder.
  • the line conductor 42 is bent. As a shape, the connection position with the external electric circuit may be as close as possible.
  • the line conductor 42 When the line conductor 42 is bent, for example, if the bending angle is bent stepwise so that the bending angle is larger than 90 °, or the corner portion of the bent portion is rounded, the high frequency due to reflection at the bent portion is obtained. It is good because the loss of can be reduced. In the case of bending in stages, the loss is reduced when the bending angle is 120 ° or more. Further, the line conductor 42 may be bent stepwise only at the outer side of the bent portion, but the inner side of the bent portion may be bent stepwise or rounded in the same manner.
  • the semiconductor package 1 has a ground terminal 5 that penetrates the wiring board 4 and is connected to the ground conductor layer 41.
  • the ground terminal 5 is made of, for example, an Fe—Ni—Co alloy, Fe—Mn alloy, SUS, SPC material, or the like.
  • the ground terminal 5 has a diameter of 0.2 mm to 1 mm, for example, and a length of 1 mm to 5 mm.
  • the ground terminal 5 is inserted into a fourth through-hole 44 provided in the wiring board 4 and is connected to the ground conductor layer 41 by a conductive bonding material 24 such as solder, and serves as a ground. For this reason, the ground terminal 5 can be set to the reference potential.
  • the wiring board 4 is provided with a connection conductor layer 45 around the fourth through hole 44 on the lower surface in order to improve the bonding strength with the ground terminal 5 via the bonding material 24 such as solder.
  • FIG. 4 and 5 are plan perspective views of the semiconductor package 1 according to one embodiment of the present invention. 4 is a top perspective view, and FIG. 5 is a bottom perspective view.
  • the ground terminal 5 is provided at a distance less than a quarter of the wavelength of the high-frequency signal transmitted through the line conductor 42 from the position overlapping the outer edge of the base 2.
  • the distance between the ground terminal 5 and the outer edge of the base 2 is L1 in FIG. L1 is, for example, 0.7 mm to 7 mm.
  • L1 is less than a quarter of the wavelength of the high-frequency signal to be transmitted, resonance between the base 2 and the ground terminal 5 that occurs at a quarter of the wavelength can be suppressed.
  • Resonance is a phenomenon that occurs at an integral multiple of a quarter of the wavelength. For this reason, when resonance occurs in transmission of a high-frequency signal, transmission loss increases.
  • the distance between the ground terminal 5 and the outer edge of the substrate 2 is set to a distance less than one-fourth of the wavelength in plan view, resonance does not occur, and transmission loss can be suppressed. That is, a high frequency signal can be transmitted under favorable conditions.
  • Resonance depends on the relationship between the distance that the wave propagates and the wavelength.
  • the distance that this wave propagates is the distance between the base 2 and the ground terminal 5, the distance between the ground conductor layer 41 and the ground terminal 5, and the distance between the signal terminal 3 and the ground terminal 5.
  • resonance occurs at a distance that is an integral multiple of a quarter of a wavelength, and resonance does not occur at a distance that is outside an integral multiple of a quarter of a wavelength. That is, if the distance between the base 2 and the ground terminal 5, the distance between the ground conductor layer 41 and the ground terminal 5, and the distance between the signal terminal 3 and the ground terminal 5 are out of an integral multiple of a quarter of the wavelength, Resonance does not occur.
  • the distance L1 between the base 2 and the ground terminal 5 the distance L2 between the ground conductor layer 41 and the ground terminal 5 described later, and the distance L3 between the signal terminal 3 and the ground terminal 5 are 1 ⁇ 4 of the wavelength. Resonance can be prevented from occurring by making the distance less than.
  • 18 GHz to 22 GHz is regarded as a 20 GHz signal.
  • 40 GHz 36 GHz to 44 GHz is regarded as a 40 GHz signal.
  • Up to 10% before and after the frequency of the standard value signal can be regarded as the standard value signal.
  • the ground conductor layer 41 is provided at a position overlapping the base 2 in a plan view.
  • the ground conductor layer 41 provided at a position overlapping the base 2 is provided at a distance of less than a quarter of the wavelength of the high frequency signal transmitted from the ground terminal 5 through the line conductor 42.
  • the distance between the ground conductor layer 41 and the ground terminal 5 is L2 in FIG. L2 is, for example, 0.7 mm to 7 mm.
  • the signal terminal 3 is provided at a distance less than a quarter of the wavelength of the high-frequency signal transmitted from the ground terminal 5 through the line conductor 42 in a plan view.
  • the distance between the signal terminal 3 and the ground terminal 5 is L3 in FIG. L3 is, for example, 0.7 mm to 7 mm.
  • L3 is less than a quarter of the wavelength of the high-frequency signal to be transmitted, resonance between the signal terminal 3 and the ground terminal 5 that occurs at a quarter of the wavelength can be suppressed.
  • transmission loss can be suppressed. That is, a high frequency signal can be transmitted under favorable conditions.
  • FIG. 6 shows a semiconductor package 1 according to another embodiment of the present invention.
  • FIG. 6 shows that the substrate 6 for reinforcing the wiring board 4 is provided between the base 2 and the wiring board 4 in addition to the semiconductor package 1 according to the embodiment of the present invention. Different from the semiconductor package 1 according to the embodiment.
  • the substrate 6 is provided between the base 2 and the wiring substrate 4.
  • the substrate 6 is provided for reinforcement when the wiring substrate 4 is a flexible substrate or the like.
  • the substrate 6 has, for example, a rectangular shape, a circular shape, a semicircular shape, or the like in plan view.
  • the size is 3 mm ⁇ 3 mm to 10 mm ⁇ 10 mm.
  • the thickness is 0.5 mm to 3 mm.
  • the substrate 6 is made of, for example, a ceramic substrate, a resin substrate, a glass substrate, or the like.
  • the semiconductor package 1 includes the substrate 6 between the base 2 and the wiring substrate 4, the strength of the semiconductor package 1 can be maintained even when the wiring substrate 4 is a flexible substrate or the like. That is, even when a force is applied from the outside, it is possible to suppress the connection inside the semiconductor package 1, particularly the connection of the semiconductor element and the load on each terminal.
  • the base 2 is made of an Fe—Mn alloy
  • the ingot (lumb) is manufactured in a predetermined shape by applying a known metal processing method such as rolling or punching, and the first through hole 21 is drilled. It is formed by punching with a metal mold. Further, the mounting surface 1b of the base body 2 can be formed by cutting or pressing.
  • the signal terminal 3 is made of a metal such as an Fe—Ni—Co alloy or an Fe—Ni alloy.
  • a metal such as an Fe—Ni—Co alloy or an Fe—Ni alloy.
  • the ingot (lumb) is rolled or punched, By applying a metal processing method such as cutting, a wire having a length of 1.5 mm to 22 mm and a diameter of 0.1 mm to 1 mm is manufactured.
  • the sealing material 22 filled in the first through hole 21 for example, when the sealing material is made of glass, first, a powder pressing method or an extrusion molding method is used. Use to mold glass powder. Next, a cylindrical molded body is produced in which the inner diameter is matched with the outer diameter of the signal terminal 3 and the outer diameter is matched with the shape of the first through hole 21.
  • the signal terminal 3 is inserted into the hole of the molded body of the sealing material 22, the molded body is inserted into a mold, heated to a predetermined temperature to melt the glass, and then cooled and solidified. By solidifying, a sealing material having a predetermined shape to which the signal terminal 3 is fixed is formed.
  • the through hole 21 is hermetically sealed by the sealing material 22, and the signal terminal 3 is insulated and fixed from the base 2 by the sealing material 22, thereby forming a coaxial line.
  • Only the sealing material that matches the shape of the through hole 21 is formed in advance, and this is inserted into the through hole 21 and the signal terminal 3 is also inserted into the hole of the sealing material 22, and the sealing material 22 and the first
  • the inner surface of the through hole 21 and the outer surface of the signal terminal 3 may be joined at the same time.
  • the signal terminal 3 is made of a metal such as an Fe—Ni—Co alloy or an Fe—Ni alloy.
  • a metal such as an Fe—Ni—Co alloy or an Fe—Ni alloy.
  • the ingot (lumb) is rolled or punched, By applying a metal processing method such as cutting, a wire having a length of 1.5 mm to 22 mm and a diameter of 0.1 mm to 1 mm is manufactured.
  • the ground terminal 5 is joined to the base 2.
  • the ground terminal 5 is manufactured in the same manner as the signal terminal 3 and is joined to the lower surface of the base 2 using a brazing material or the like.
  • a hole may be formed in the lower surface of the base 2 in advance, and the ground terminal 5 may be inserted into the hole for bonding.
  • the wiring substrate 4 is, for example, a flexible wiring substrate
  • a conductive metal such as copper foil is bonded to the upper and lower surfaces of a thin and soft base film having an insulating property made of polyimide or the like.
  • the wiring board 4 provided with the ground conductor layer 41 and the line conductor 42 having a desired shape is manufactured.
  • the wiring board 4 manufactured in this way is joined to the lower surface of the base 2 via solder, and the tip of the signal terminal 3 and the line conductor 42 are connected with a brazing material, whereby the semiconductor package according to the embodiment of the present invention. 1
  • FIG. 7 is a perspective view of the semiconductor device 10 according to an embodiment of the present invention.
  • a semiconductor device 10 according to an embodiment of the present invention includes a semiconductor package 1 according to an embodiment of the present invention, a semiconductor element 7 mounted on a base 2, and a lid 8 bonded to the base 2. I have.
  • Examples of the semiconductor element 7 include optical semiconductor elements such as LD (laser diode) and PD (photodiode), semiconductor elements including semiconductor integrated circuit elements, piezoelectric elements such as crystal resonators and surface acoustic wave elements, and pressure sensor elements. , Capacitive elements, resistors and the like. These semiconductor elements are mounted on the base 2.
  • optical semiconductor elements such as LD (laser diode) and PD (photodiode)
  • semiconductor elements including semiconductor integrated circuit elements, piezoelectric elements such as crystal resonators and surface acoustic wave elements, and pressure sensor elements.
  • Capacitive elements, resistors and the like are mounted on the base 2.
  • the semiconductor element 7 may be mounted on the base 2 by being fixed with a conductive bonding material such as a brazing material or a conductive resin.
  • a conductive bonding material such as a brazing material or a conductive resin.
  • a gold-tin (Au—Sn) alloy or a gold-germanium (Au—Ge) alloy is used to fix the wiring board 4.
  • a brazing material such as a tin-silver (Sn—Ag) alloy or a tin-silver-copper (Sn—Ag—Cu) alloy having a lower melting point is used to fix the semiconductor element 7.
  • An adhesive made of a resin such as Ag epoxy that can be cured at a temperature lower than the melting point may be used as the bonding material.
  • the wiring board 4 may be mounted on the base 2 after the semiconductor element 7 is mounted on the base 2.
  • the melting point of the bonding material used when mounting the wiring board 4 on the base 2. Should be lower.
  • the paste of the bonding material is printed on the wiring board 4 or the base body 2 by using a screen printing method, a bonding material layer is formed by a photolithography method, or the low melting point brazing material to be the bonding material
  • a preform can be placed.
  • the lid body 8 has an outer shape along the outer peripheral region of the base body 2 and a shape having a space that covers the semiconductor element 7 mounted on the base body 2.
  • the size is the same as that of the base 2 in a top view. Further, the lid 8 may be smaller than the base 2.
  • a third through hole 81 is provided as a window that transmits light in a portion facing the semiconductor element 7. Instead of the third through hole 81 or in addition to the window, an optical fiber and an optical isolator for preventing return light may be joined.
  • the lid 8 is made of a metal such as an Fe—Ni—Co alloy, an Fe—Ni alloy, or an Fe—Mn alloy, and is produced by subjecting these plate materials to a known metal working method such as press working or punching. .
  • the lid 8 should preferably have the same thermal expansion coefficient as the material of the base 2, and it is better to use the same material as that of the base 2.
  • a flat or lens-shaped glass window member is joined to a member provided with a hole in a portion facing the semiconductor element 7 with a low melting point glass or the like.
  • the lid 8 is joined to the base 2 by welding such as seam welding or YAG laser welding or brazing with a brazing material such as an Au—Sn brazing material.
  • the semiconductor element 7 is mounted on the base 2, the terminal of the semiconductor element 7 and the line conductor 42 of the wiring substrate 4 are connected by a bonding wire or the like, and the lid body 8 is joined to the upper surface of the frame portion.
  • a semiconductor device according to one embodiment is obtained.
  • the semiconductor element 7 is directly mounted on the base 2, which is to radiate the heat generated in the semiconductor element 7 to the outside through the metal base 2.
  • a Peltier element or the like may be mounted between the semiconductor element 7 (and the wiring board 4) to cool the semiconductor element 7.
  • the semiconductor device 10 may include a substrate 6 as a reinforcing member similarly to the semiconductor package 1 shown in FIG. Since the semiconductor device 10 includes the substrate 6, the strength of the wiring substrate 4 made of a flexible substrate or the like can be improved.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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PCT/JP2017/016419 2016-04-26 2017-04-25 半導体パッケージおよびそれを用いた半導体装置 WO2017188269A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201780024399.9A CN109075527B (zh) 2016-04-26 2017-04-25 半导体封装件及使用其的半导体装置
KR1020187029979A KR102164911B1 (ko) 2016-04-26 2017-04-25 반도체 패키지 및 그것을 사용한 반도체 장치
JP2018514634A JP6849670B2 (ja) 2016-04-26 2017-04-25 半導体パッケージおよびそれを用いた半導体装置

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Application Number Priority Date Filing Date Title
JP2016-088170 2016-04-26
JP2016088170 2016-04-26

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WO2017188269A1 true WO2017188269A1 (ja) 2017-11-02

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KR (1) KR102164911B1 (ko)
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WO (1) WO2017188269A1 (ko)

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JP7264320B1 (ja) * 2022-07-19 2023-04-25 三菱電機株式会社 半導体レーザ光源装置

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JP2021027136A (ja) * 2019-08-02 2021-02-22 ＣＩＧ Ｐｈｏｔｏｎｉｃｓ Ｊａｐａｎ株式会社 光モジュール

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005228766A (ja) * 2004-02-10 2005-08-25 Opnext Japan Inc 光送信機
JP2008211072A (ja) * 2007-02-27 2008-09-11 Mitsubishi Electric Corp 光モジュール
JP2010245507A (ja) * 2009-01-27 2010-10-28 Kyocera Corp 電子部品搭載用パッケージおよびそれを用いた電子装置
JP2011134740A (ja) * 2009-12-22 2011-07-07 Kyocera Corp 電子部品搭載用パッケージおよびそれを用いた電子装置
JP2012064817A (ja) * 2010-09-16 2012-03-29 Kyocera Corp 電子部品搭載用パッケージおよび通信用モジュール
JP2012238647A (ja) * 2011-05-10 2012-12-06 Sumitomo Electric Device Innovations Inc 光学素子搭載用パッケージ及び光モジュール
JP2013197274A (ja) * 2012-03-19 2013-09-30 Nippon Telegr & Teleph Corp <Ntt> 光モジュール

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3436009B2 (ja) * 1996-07-31 2003-08-11 住友電気工業株式会社 光半導体素子
JPH1197846A (ja) * 1997-09-16 1999-04-09 Micronics Japan Co Ltd 配線基盤及びこれを用いた配線装置
JP4091938B2 (ja) * 2004-10-21 2008-05-28 日東電工株式会社 配線回路基板の製造方法
JP2007123738A (ja) * 2005-10-31 2007-05-17 Sony Corp 光送信モジュール、光送受信モジュール及び光通信装置
CN101246886B (zh) * 2008-03-19 2010-06-02 江苏宏微科技有限公司 Mos结构的功率晶体管及其制作方法
CN101587933B (zh) * 2009-07-07 2010-12-08 苏州晶方半导体科技股份有限公司 发光二极管的晶圆级封装结构及其制造方法
US8475058B2 (en) * 2010-08-18 2013-07-02 Sumitomo Electric Industries, Ltd. Optical module with ceramic package reducing optical coupling stress
JP2013089727A (ja) * 2011-10-17 2013-05-13 Fujikura Ltd フレキシブルプリント基板
CN204597019U (zh) * 2012-06-29 2015-08-26 株式会社村田制作所 将电缆固定于布线基板的固定结构、以及电缆
JP6218481B2 (ja) * 2012-09-27 2017-10-25 三菱電機株式会社 フレキシブル基板、基板接続構造及び光モジュール
CN104364897B (zh) * 2012-10-29 2017-07-25 京瓷株式会社 元件收纳用封装件以及安装结构体
KR20140057979A (ko) * 2012-11-05 2014-05-14 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR20150075347A (ko) * 2013-12-25 2015-07-03 가부시끼가이샤 도시바 반도체 패키지, 반도체 모듈 및 반도체 디바이스
JP6305179B2 (ja) * 2014-04-15 2018-04-04 日本オクラロ株式会社 光モジュール
JP6317989B2 (ja) * 2014-04-24 2018-04-25 新光電気工業株式会社 配線基板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005228766A (ja) * 2004-02-10 2005-08-25 Opnext Japan Inc 光送信機
JP2008211072A (ja) * 2007-02-27 2008-09-11 Mitsubishi Electric Corp 光モジュール
JP2010245507A (ja) * 2009-01-27 2010-10-28 Kyocera Corp 電子部品搭載用パッケージおよびそれを用いた電子装置
JP2011134740A (ja) * 2009-12-22 2011-07-07 Kyocera Corp 電子部品搭載用パッケージおよびそれを用いた電子装置
JP2012064817A (ja) * 2010-09-16 2012-03-29 Kyocera Corp 電子部品搭載用パッケージおよび通信用モジュール
JP2012238647A (ja) * 2011-05-10 2012-12-06 Sumitomo Electric Device Innovations Inc 光学素子搭載用パッケージ及び光モジュール
JP2013197274A (ja) * 2012-03-19 2013-09-30 Nippon Telegr & Teleph Corp <Ntt> 光モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7264320B1 (ja) * 2022-07-19 2023-04-25 三菱電機株式会社 半導体レーザ光源装置

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