WO2017094189A1 - 半導体モジュール - Google Patents

半導体モジュール Download PDF

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Publication number
WO2017094189A1
WO2017094189A1 PCT/JP2015/084164 JP2015084164W WO2017094189A1 WO 2017094189 A1 WO2017094189 A1 WO 2017094189A1 JP 2015084164 W JP2015084164 W JP 2015084164W WO 2017094189 A1 WO2017094189 A1 WO 2017094189A1
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WO
WIPO (PCT)
Prior art keywords
base plate
semiconductor module
case
semiconductor
semiconductor chip
Prior art date
Application number
PCT/JP2015/084164
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English (en)
French (fr)
Japanese (ja)
Inventor
大介 大宅
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US15/766,112 priority Critical patent/US10483176B2/en
Priority to PCT/JP2015/084164 priority patent/WO2017094189A1/ja
Priority to DE112015007169.5T priority patent/DE112015007169B4/de
Priority to JP2017553591A priority patent/JP6407451B2/ja
Priority to CN201580084967.5A priority patent/CN108292631B/zh
Publication of WO2017094189A1 publication Critical patent/WO2017094189A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Definitions

  • the present invention relates to a semiconductor module in which a semiconductor chip is housed in a case.
  • a sealing resin gel
  • a configuration using an adhesive has been proposed in order to prevent moisture from entering the inside of the case through the joint and fixing portion between the case and the base plate (heat sink).
  • Patent Document 1 a configuration is proposed in which the case and the base plate are fixed by providing a convex portion and a concave portion in the case and the base plate (heat dissipation plate) without using an adhesive, and fitting them together.
  • an adhesive (sealing material) is filled in a groove provided in a portion of the upper surface of the base plate below the side wall of the case.
  • air bubbles are likely to remain in the adhesive in the groove, and there is a possibility that the insulation resistance of the module may be reduced by the air bubbles.
  • the case and the base plate are fixed by the convex portion and the concave portion without using an adhesive, so the structure becomes complicated.
  • the sealing resin gel
  • the insulation withstand capacity insulation performance
  • the present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor module capable of joining a case and a base plate with a simple structure and enhancing the insulation withstand capacity. I assume.
  • the semiconductor module according to the present invention is joined with a base plate, a semiconductor chip disposed above the base plate inside the outer periphery of the base plate, and the outer periphery of the base plate by an adhesive.
  • a case for containing a semiconductor chip is provided, and a concave portion or a convex portion is provided in a portion between the inner wall of the case and the semiconductor chip in a plan view of the upper surface of the base plate.
  • the concave portion or the convex portion is disposed in a portion between the inner wall of the case and the semiconductor chip in plan view of the upper surface of the base plate.
  • FIG. 1 is a cross-sectional view showing a configuration of a semiconductor module according to Embodiment 1; It is sectional drawing which shows the structure of a related semiconductor module.
  • FIG. 7 is a cross-sectional view showing a configuration of a semiconductor module according to Embodiment 2;
  • FIG. 14 is a diagram for explaining the effect of the semiconductor module according to the second embodiment. It is a top view showing a part of composition of a semiconductor module concerning a modification. It is a sectional view showing a part of composition of a semiconductor module concerning a modification.
  • FIG. 16 is a cross-sectional view showing a configuration of a semiconductor module according to Embodiment 3;
  • FIG. 1 is a cross-sectional view showing a configuration of a semiconductor module (power semiconductor module) according to Embodiment 1 of the present invention.
  • the semiconductor module of FIG. 1 includes a base plate 1, a semiconductor chip 2, a case 3, an insulating ceramic substrate 4 which is an insulating substrate, and a sealant 5.
  • the base plate 1 is made of, for example, a metal such as Cu, AlSiC, Al (Cu is copper, Al is aluminum, Si is silicon, C is carbon), and is used as a heat sink, for example.
  • the semiconductor chip 2 is disposed above the base plate 1 inside the outer peripheral portion of the base plate 1.
  • the semiconductor chip 2 may be made of, for example, Si, or a wide band gap semiconductor such as SiC, GaN (gallium nitride) or the like.
  • an IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • diode a SBD (Schottky Barrier Diode) or the like is applied.
  • SBD Schottky Barrier Diode
  • Case 3 is bonded to the outer peripheral portion of the base plate 1 by an adhesive 6 and accommodates the semiconductor chip 2.
  • Case 3 is made of, for example, PPS (polyphenylene sulfide), PET (polyethylene terephthalate) + PBT (polybutylene terephthalate).
  • the adhesive 6 is made of, for example, a silicone-based or epoxy-based material.
  • the lower portion of the case 3 is provided with a notch 3 b which can be engaged with the upper portion (corner portion) of the outer peripheral portion of the base plate 1.
  • the adhesive 6 is provided between the notch 3 b of the case 3 and the upper portion (corner portion) of the base plate 1.
  • the insulating ceramic substrate 4 is disposed between the semiconductor chip 2 and the base plate 1 in cross section.
  • a surface metal pattern 4a and a back surface metal pattern 4b are provided on the front and back surfaces of the insulating ceramic substrate 4, respectively.
  • the front surface metal pattern 4 a is connected to the lower portion of the semiconductor chip 2, and the back surface metal pattern 4 b is joined to the base plate 1 by the solder 7.
  • the sealant 5 is made of, for example, an insulating material such as silicone gel, and is filled inside the case 3. Thereby, the insulation of the semiconductor module is secured.
  • a concave portion is provided in a portion between the inner wall 3 a of the case 3 and the semiconductor chip 2 in a plan view.
  • a groove 8 extending along the inner wall 3 a of the case 3 in a plan view is disposed on the upper surface of the base plate 1 as a recess. It is assumed that the sealant 5 is filled in the groove 8.
  • the base plate 1 When the base plate 1 is molded by metal melting, the base plate 1 provided with the groove 8 can be molded by providing a protrusion corresponding to the groove 8 in a mold (mold). In addition, processing by etching may be additionally performed for the stability of the groove 8.
  • the surface of the base plate 1 not forming the groove 8 is masked with a resist and the base plate 1 is formed Selectively etch. Thereby, the base plate 1 in which the groove 8 is disposed can be formed. When the etching is not performed, the groove 8 may be formed in the base plate 1 by pressing.
  • the case 3 and the base plate 1 can be joined with a simple structure. Moreover, since the groove is not provided in the lower part of the side wall of case 3 among the upper surfaces of base plate 1, the air bubbles in adhesive 6 after solidification can be reduced. As a result, the insulation withstand capacity of the semiconductor module can be increased.
  • a semiconductor module associated with the semiconductor module according to the first embodiment shown in FIG. 2 (hereinafter referred to as “related semiconductor module”) Will be explained.
  • the components of the related semiconductor module that are the same as or similar to those of the first embodiment are given the same reference numerals, and different components will be mainly described.
  • the first point is a problem caused by the fact that the height H (FIG. 2) may be insufficient in the fillet 6 a inside the case 3 of the adhesive 6.
  • the height H of the fillet 6a is insufficient, a gap is generated at the interface, and the sealant 5 inside the case 3 leaks to the outside from the gap or water outside the case 3 infiltrates to the inside A problem arises.
  • the fillet 6 a of the adhesive 6 before solidification is the case of It is necessary to sufficiently extend upward along the inner wall 3a. That is, it is necessary to make the height H of the fillet 6a sufficiently high so that a gap does not occur due to a variation factor.
  • the second point is a problem caused by the fact that the sag length L (FIG. 2) may increase in the fillet 6 a inside the case 3 of the adhesive 6.
  • the sag length L (FIG. 2) may increase in the fillet 6 a inside the case 3 of the adhesive 6.
  • the risk that the air bubble 6b bites into the adhesive 6 increases.
  • the air bubbles 6 b caught in the adhesive 6 may pop out of the adhesive 6 at high temperature and move into the sealant 5. Then, when the air bubbles move to the periphery of the insulating ceramic substrate 4, the insulation performance is lowered, causing a problem of insulation failure.
  • the sagging of the adhesive 6 is caused by the groove 8 in FIG. 1 with respect to the adhesive 6 before solidification which is extruded when the case 3 and the base plate 1 are joined. Is suppressed by the surface tension effect. Thereby, the dripping length L of the fillet 6a is suppressed, and on the other hand, the fillet 6a swells, and the height H of the fillet 6a becomes high. As a result, the first problem (the leakage of the sealant 5 and the entry of water) can be solved, and the second problem (the reduction of the insulation performance) can be solved. Furthermore, since reduction in the clearance between the case 3 and the insulating ceramic substrate 4 can also be expected, miniaturization of the semiconductor module can be expected.
  • the adhesive 6 is provided between the notch 3 b of the case 3 and the upper portion (corner portion) of the base plate 1. As a result, the occurrence of the gap between the case 3 and the base plate 1 can be reduced, so that the leakage of the sealant 5 and the entry of water can be suppressed.
  • the semiconductor chip 2 is made of a wide band gap semiconductor such as SiC.
  • a wide band gap semiconductor such as SiC.
  • FIG. 3 is a cross-sectional view showing the configuration of the semiconductor module according to the second embodiment of the present invention.
  • the same or similar components as or to those of the first embodiment are denoted by the same reference numerals, and different components will be mainly described.
  • one end in the width direction of the groove 8 is located in the vicinity of the inner wall 3 a of the case 3 in a plan view. Then, the other end of the groove 8 in the width direction in plan view is located outside the solder 7 and in the vicinity of the solder 7.
  • the solder 7 is a joint portion between the insulating ceramic substrate 4 and the base plate 1.
  • the depth of the groove 8 corresponds to a length obtained by removing the thickness of the back surface metal pattern 4 b and the solder 7 from the distance D.
  • the electric field E at the end 4c of the surface metal pattern 4a can be relaxed as the distance D is increased.
  • the distance D is preferably 1 mm or more, and more preferably 2 mm or more.
  • the electric field of the insulating ceramic substrate 4 (surface metal pattern 4a) can be alleviated, so that the insulation performance can be enhanced.
  • FIG. 5 is a plan view showing a part of the configuration of the semiconductor module according to the present modification
  • FIG. 6 is a cross-sectional view taken along the line AA of FIG.
  • semiconductor chips 2a, 2b, 2c and 2d are provided instead of the semiconductor chip 2.
  • the semiconductor chip 2a is adjacent to the semiconductor chips 2b and 2c, and the semiconductor chip 2b is adjacent to the semiconductor chips 2a and 2d.
  • the semiconductor chip 2c is adjacent to the semiconductor chips 2a and 2d, and the semiconductor chip 2d is adjacent to the semiconductor chips 2b and 2c.
  • the first semiconductor chip is described as the semiconductor chip 2c
  • the second semiconductor chip is described as the semiconductor chip 2d, but the other combinations are configured in the same manner as the following description.
  • insulating ceramic substrate 4 instead of the insulating ceramic substrate 4, divided insulating ceramic substrates 9a, 9b, 9c, 9d are provided.
  • Each of insulating ceramic substrates 9 a, 9 b, 9 c, 9 d is configured in the same manner as insulating ceramic substrate 4. That is, the insulating ceramic substrate 9c which is the first insulating substrate is disposed between the semiconductor chip 2c which is the first semiconductor chip and the one base plate 1, and the insulating ceramic which is the second insulating substrate.
  • the substrate 9 d is disposed between the semiconductor chip 2 d which is a second semiconductor chip and the one base plate 1.
  • the insulating ceramic substrates 9a and 9b are disposed between the semiconductor chips 2a and 2b and the one base plate 1, respectively.
  • the groove 8 is provided also in the portion between the solder 9 c and the solder 9 d in the upper surface of the base plate 1.
  • the solder 9c is a bonding portion of the insulating ceramic substrate (first insulating substrate) 9c and the base plate 1
  • the solder 9d is a bonding portion of the insulating ceramic substrate (second insulating substrate) 9d and the base plate 1 It is.
  • the insulation performance can be enhanced as in the second embodiment.
  • FIG. 7 is a cross-sectional view showing the configuration of the semiconductor module according to the third embodiment of the present invention.
  • the same or similar components as or to those in the first embodiment are given the same reference numerals, and different components will be mainly described.
  • a convex portion is disposed in a portion between the inner wall 3 a of the case 3 and the semiconductor chip 2 in a plan view.
  • the resist 10 is disposed on the upper surface of the base plate 1 as a convex portion.
  • the resist 10 may extend along the inner wall 3a of the case 3 in plan view, as with the groove 8 described in the first embodiment.
  • the height of the resist 10 is preferably sufficiently higher than the height of the tip portion of the fillet 6a.
  • the case 3 and the base plate 1 can be joined with a simple structure. Moreover, since the groove is not provided in the lower part of the side wall of case 3 among the upper surfaces of base plate 1, the air bubbles in adhesive 6 after solidification can be reduced. As a result, the insulation withstand capacity of the semiconductor module can be increased. Further, as in the first embodiment, since the sagging of the adhesive 6 is suppressed by the resist 10, the leakage of the sealing agent 5 and the entry of water can be suppressed, and the decrease in the insulation performance is suppressed. be able to.
  • each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.
  • Base plate 2, 2a, 2b, 2c, 2d semiconductor chip, 3 cases, 3a inner wall, 3b notch, 4, 9a, 9b, 9c, 9d Insulating ceramic substrate, 6 adhesive, 8 groove, 10 resist.
PCT/JP2015/084164 2015-12-04 2015-12-04 半導体モジュール WO2017094189A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US15/766,112 US10483176B2 (en) 2015-12-04 2015-12-04 Semiconductor module
PCT/JP2015/084164 WO2017094189A1 (ja) 2015-12-04 2015-12-04 半導体モジュール
DE112015007169.5T DE112015007169B4 (de) 2015-12-04 2015-12-04 Halbleitermodul
JP2017553591A JP6407451B2 (ja) 2015-12-04 2015-12-04 半導体モジュール
CN201580084967.5A CN108292631B (zh) 2015-12-04 2015-12-04 半导体模块

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/084164 WO2017094189A1 (ja) 2015-12-04 2015-12-04 半導体モジュール

Publications (1)

Publication Number Publication Date
WO2017094189A1 true WO2017094189A1 (ja) 2017-06-08

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PCT/JP2015/084164 WO2017094189A1 (ja) 2015-12-04 2015-12-04 半導体モジュール

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Country Link
US (1) US10483176B2 (de)
JP (1) JP6407451B2 (de)
CN (1) CN108292631B (de)
DE (1) DE112015007169B4 (de)
WO (1) WO2017094189A1 (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019192877A (ja) * 2018-04-27 2019-10-31 株式会社デンソー 半導体装置
JP2021027137A (ja) * 2019-08-02 2021-02-22 株式会社東芝 半導体装置
JP2021150575A (ja) * 2020-03-23 2021-09-27 株式会社東芝 半導体装置
JP2021170616A (ja) * 2020-04-17 2021-10-28 三菱電機株式会社 半導体装置および半導体装置の製造方法
WO2023112274A1 (ja) * 2021-12-16 2023-06-22 三菱電機株式会社 半導体装置

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