JP4735446B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4735446B2 JP4735446B2 JP2006184568A JP2006184568A JP4735446B2 JP 4735446 B2 JP4735446 B2 JP 4735446B2 JP 2006184568 A JP2006184568 A JP 2006184568A JP 2006184568 A JP2006184568 A JP 2006184568A JP 4735446 B2 JP4735446 B2 JP 4735446B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- solder
- filler
- substrate
- under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/22—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device liquid at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
図1は、本発明の実施の形態1に係る半導体装置を示す断面図であり、図2は、この半導体装置の要部を拡大した断面図である。
図3は、本発明の実施の形態2に係る半導体装置の要部を拡大した断面図である。充填剤22は、充填剤22自身よりも熱伝導率が高い微粒子23を含有する。その他の構成は実施の形態1と同様である。これにより、充填剤22の熱伝導が向上するため、半導体装置の寿命が実施の形態1よりも長くなる。
図4は、本発明の実施の形態3に係る半導体装置の要部を拡大した断面図である。図に示すように、充填剤22は、その最上部に硬化層24が形成されている。そして、この硬化層24は、例えば、紫外線等を照射することで硬化する充填剤22を用いたり、また、熱硬化性の樹脂(シリコンゲルなども含む)を充填剤22の表面に薄く塗布し、加熱処理を加えることなどにより形成することができる。その他の構成は実施の形態1又は2と同様である。これにより、実施の形態1又は2と同様の効果を奏するだけでなく、充填剤の高さを安定させることができ、半導体素子14や素子下はんだ15及び上部半導体12を覆うシリコンゲル20の注入作業を容易なものとすることができる。従って、半導体装置の品質及び信頼性を向上させることができる。
12 上部導体
13 下部導体
14 半導体素子
15 素子下はんだ
16 放熱板
17 基板下はんだ
20 シリコーンゲル
22 充填剤
23 微粒子
24 硬化層
Claims (3)
- 上面に上部導体が形成され、下面に下部導体が形成された絶縁基板と、
前記絶縁基板上に素子下はんだを介して搭載された半導体素子と、
前記絶縁基板が基板下はんだを介して搭載された放熱板と、
前記半導体素子、前記素子下はんだ及び前記上部導体を覆うシリコーンゲルと、
前記半導体素子、前記素子下はんだ及び前記上部導体を覆うことなく、前記下部導体及び前記基板下はんだを覆う、空気よりも熱伝導率が大きく、前記シリコーンゲルよりも流動性が高い充填剤とを有することを特徴とする半導体装置。 - 前記充填剤は、前記充填剤自身よりも熱伝導率が高い微粒子を含有することを特徴とする請求項1に記載の半導体装置。
- 前記充填剤は最上部に硬化層が形成されていることを特徴とする請求項1に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006184568A JP4735446B2 (ja) | 2006-07-04 | 2006-07-04 | 半導体装置 |
US11/553,235 US7554192B2 (en) | 2006-07-04 | 2006-10-26 | Semiconductor device having filler with thermal conductive particles |
DE102007008912A DE102007008912B4 (de) | 2006-07-04 | 2007-02-23 | Halbleitervorrichtung |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006184568A JP4735446B2 (ja) | 2006-07-04 | 2006-07-04 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008016551A JP2008016551A (ja) | 2008-01-24 |
JP4735446B2 true JP4735446B2 (ja) | 2011-07-27 |
Family
ID=38825408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006184568A Expired - Fee Related JP4735446B2 (ja) | 2006-07-04 | 2006-07-04 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7554192B2 (ja) |
JP (1) | JP4735446B2 (ja) |
DE (1) | DE102007008912B4 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5212417B2 (ja) | 2010-04-12 | 2013-06-19 | 三菱電機株式会社 | パワー半導体モジュール |
US20120083763A1 (en) * | 2010-10-04 | 2012-04-05 | Diaz Edwin A | Method for Delivering a Topical Agent to a Nasaogastric Passage |
WO2013089099A1 (ja) * | 2011-12-12 | 2013-06-20 | 三菱マテリアル株式会社 | パワーモジュール用基板、ヒートシンク付パワーモジュール用基板、パワーモジュール、フラックス成分侵入防止層形成用ペーストおよび接合体の接合方法 |
KR102046099B1 (ko) | 2012-12-31 | 2019-11-19 | 삼성전자주식회사 | 열전재료 및 이를 포함하는 열전소자 |
US9478473B2 (en) * | 2013-05-21 | 2016-10-25 | Globalfoundries Inc. | Fabricating a microelectronics lid using sol-gel processing |
WO2017094189A1 (ja) * | 2015-12-04 | 2017-06-08 | 三菱電機株式会社 | 半導体モジュール |
US10886251B2 (en) | 2017-04-21 | 2021-01-05 | Toyota Motor Engineering & Manufacturing North America, Inc. | Multi-layered composite bonding materials and power electronics assemblies incorporating the same |
US10381223B2 (en) | 2017-11-28 | 2019-08-13 | Toyota Motor Engineering & Manufacturing North America, Inc. | Multilayer composite bonding materials and power electronics assemblies incorporating the same |
JP7258806B2 (ja) * | 2020-03-23 | 2023-04-17 | 株式会社東芝 | 半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6396945A (ja) * | 1986-10-14 | 1988-04-27 | Nippon Denso Co Ltd | 大電力用半導体装置 |
JPH10173098A (ja) * | 1996-12-10 | 1998-06-26 | Mitsubishi Electric Corp | パワー半導体装置およびその製法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000114413A (ja) * | 1998-09-29 | 2000-04-21 | Sony Corp | 半導体装置、その製造方法および部品の実装方法 |
SE0003050D0 (sv) | 2000-08-30 | 2000-08-30 | Abb Ab | Komposit |
JP4130527B2 (ja) * | 2000-12-13 | 2008-08-06 | 三菱電機株式会社 | 半導体装置 |
US7087458B2 (en) * | 2002-10-30 | 2006-08-08 | Advanpack Solutions Pte. Ltd. | Method for fabricating a flip chip package with pillar bump and no flow underfill |
JP3972821B2 (ja) * | 2003-01-22 | 2007-09-05 | 三菱電機株式会社 | 電力用半導体装置 |
CN100378969C (zh) * | 2003-06-24 | 2008-04-02 | 日本特殊陶业株式会社 | 中间衬底及具有半导体元件、中间衬底和衬底的结构体 |
-
2006
- 2006-07-04 JP JP2006184568A patent/JP4735446B2/ja not_active Expired - Fee Related
- 2006-10-26 US US11/553,235 patent/US7554192B2/en active Active
-
2007
- 2007-02-23 DE DE102007008912A patent/DE102007008912B4/de not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6396945A (ja) * | 1986-10-14 | 1988-04-27 | Nippon Denso Co Ltd | 大電力用半導体装置 |
JPH10173098A (ja) * | 1996-12-10 | 1998-06-26 | Mitsubishi Electric Corp | パワー半導体装置およびその製法 |
Also Published As
Publication number | Publication date |
---|---|
US20080006932A1 (en) | 2008-01-10 |
US7554192B2 (en) | 2009-06-30 |
DE102007008912A1 (de) | 2008-01-17 |
JP2008016551A (ja) | 2008-01-24 |
DE102007008912B4 (de) | 2009-01-29 |
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