JPWO2018096656A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 238000003825 pressing Methods 0.000 claims abstract description 58
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000003566 sealing material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置を示す断面図である。図2は、本発明の実施の形態1に係るケース電極を示す上面図である。絶縁基板1の下面に下面電極2が設けられ、上面にベース板3が設けられている。ベース板3上にはんだ4を介して半導体チップ5が設けられている。
図3は、本発明の実施の形態2に係る半導体装置を示す断面図である。凹部12はケース6の内端面から外側に離間している。これにより、半導体チップ5とケース電極7との沿面距離を確保することができる。その他の構成及び効果は実施の形態1と同様である。
図4は、本発明の実施の形態3に係る半導体装置を示す断面図である。ケース電極7の曲げ加工された部分に貫通孔13が設けられている。第2の押さえ部11をケース樹脂により形成する際に、貫通孔13を介して第2の押さえ部11にケース樹脂が回り込み易くなる。その他の構成及び効果は実施の形態2と同様である。なお、実施の形態2の構成に貫通孔13を追加しているが、実施の形態1の構成に貫通孔13を追加してもよい。
図5は、本発明の実施の形態4に係る半導体装置を示す断面図である。本実施の形態では、ケース電極7を研削することで、ケース電極7の上面に凹部14を設けている。第2の押さえ部11は凹部14内に配置されている。これにより、実施の形態1と同様の効果を得ることができる。また、実施の形態1の曲げ加工よりもケース電極7の加工精度を向上することができる。
図6は、本発明の実施の形態5に係る半導体装置を示す断面図である。図7は、本発明の実施の形態5に係るケース電極を示す上面図である。凹部14は下方に向かって階段状に幅が狭くなる貫通孔である。これにより、第2の押さえ部11は、各ケース電極7の凹部14内のみに配置すればよく、隣接するケース電極7間に配置する必要は無い。従って、第2の押さえ部11に用いる樹脂量を削減することができる。その他の構成及び効果は実施の形態2と同様である。
図8は、本発明の実施の形態6に係る半導体装置を示す断面図である。図9は、本発明の実施の形態6に係るケース電極を示す上面図である。凹部14は断面形状が台形の貫通孔である。このため、加工が容易である。その他の構成及び効果は実施の形態5と同様である。
図10は、本発明の実施の形態7に係る半導体装置を示す断面図である。図11は、本発明の実施の形態7に係るケース電極を示す上面図及び断面図である。ケース電極7は、断面がエの字型であり、側面に凹部15が設けられている。この凹部15内にケース樹脂が充填されることでケース電極7がケース6に固定されている。これにより、ケース電極7をケース6に対して強固に固定できるため、ワイヤ接合性を向上させることができる。また、ケース電極7上に第2の押さえ部11を設ける必要が無いため、ワイヤ8の高さを低減することができる。
図12は、本発明の実施の形態8に係る半導体装置を示す断面図である。図13は、本発明の実施の形態8に係る第2の押さえ部を拡大した断面図である。実施の形態1と同様に、第1の押さえ部10と第2の押さえ部11でケース電極7の両端を押さえつけることでケース電極7をケース6に対して強固に固定できるため、ワイヤ接合性を向上させることができる。
図14は、本発明の実施の形態9に係る半導体装置を示す断面図である。図15は、本発明の実施の形態9に係るケース電極を示す上面図である。実施の形態1と同様に、第1の押さえ部10と第2の押さえ部11でケース電極7の両端を押さえつけることでケース電極7をケース6に対して強固に固定できるため、ワイヤ接合性を向上させることができる。
Claims (11)
- 半導体チップと、
前記半導体チップを取り囲むケースと、
前記ケースの上面に取り付けられたケース電極と、
前記半導体チップと前記ケース電極に接続されたワイヤと、
前記ワイヤが接合された前記ケース電極の接合部分よりも外側で前記ケース電極を前記ケースの前記上面に押さえつける第1の押さえ部と、
前記接合部分よりも内側で前記ケース電極を前記ケースの前記上面に押さえつける第2の押さえ部とを備え、
前記ケースの前記上面に凹部が設けられ、
前記ケース電極は前記凹部に入り込むように曲げ加工され、
前記第2の押さえ部は前記凹部内に配置されていることを特徴とする半導体装置。 - 前記凹部は前記ケースの内端面から離間していることを特徴とする請求項1に記載の半導体装置。
- 前記ケース電極の曲げ加工された部分に貫通孔が設けられていることを特徴とする請求項1又は2に記載の半導体装置。
- 半導体チップと、
前記半導体チップを取り囲むケースと、
前記ケースの上面に取り付けられたケース電極と、
前記半導体チップと前記ケース電極に接続されたワイヤと、
前記ワイヤが接合された前記ケース電極の接合部分よりも外側で前記ケース電極を前記ケースの前記上面に押さえつける第1の押さえ部と、
前記接合部分よりも内側で前記ケース電極を前記ケースの前記上面に押さえつける第2の押さえ部とを備え、
前記ケース電極の上面に凹部が設けられ、
前記第2の押さえ部は前記凹部内に配置されていることを特徴とする半導体装置。 - 前記凹部は下方に向かって幅が狭くなる貫通孔であることを特徴とする請求項4に記載の半導体装置。
- 前記凹部は断面形状が台形の貫通孔であることを特徴とする請求項5に記載の半導体装置。
- 前記第2の押さえ部の上面の高さは、前記ケース電極の前記接合部分の上面以下であることを特徴とする請求項1〜6の何れか1項に記載の半導体装置。
- 半導体チップと、
前記半導体チップを取り囲むケースと、
前記ケースの上面に取り付けられたケース電極と、
前記半導体チップと前記ケース電極に接続されたワイヤとを備え、
前記ケース電極の側面に凹部が設けられ、
前記凹部内にケース樹脂が充填されることで前記ケース電極が前記ケースに固定されていることを特徴とする半導体装置。 - 半導体チップと、
前記半導体チップを取り囲むケースと、
前記ケースの上面に取り付けられたケース電極と、
前記半導体チップと前記ケース電極に接続されたワイヤと、
前記ワイヤが接合された前記ケース電極の接合部分よりも外側で前記ケース電極を前記ケースの前記上面に押さえつける第1の押さえ部と、
前記接合部分よりも内側で前記ケース電極を前記ケースの前記上面に押さえつける第2の押さえ部とを備え、
前記第2の押さえ部は前記ワイヤに沿ったテーパー形状であることを特徴とする半導体装置。 - 半導体チップと、
前記半導体チップを取り囲むケースと、
前記ケースの上面に取り付けられたケース電極と、
前記半導体チップと前記ケース電極に接続されたワイヤと、
前記ワイヤが接合された前記ケース電極の接合部分よりも外側で前記ケース電極を前記ケースの前記上面に押さえつける第1の押さえ部と、
前記接合部分よりも内側で前記ケース電極を前記ケースの前記上面に押さえつける第2の押さえ部とを備え、
前記第2の押さえ部は接着材であることを特徴とする半導体装置。 - 前記半導体チップはワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1〜10の何れか1項に記載の半導体装置。
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