WO2016173394A1 - 一种半导体超级结功率器件及其制造方法 - Google Patents
一种半导体超级结功率器件及其制造方法 Download PDFInfo
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Definitions
- the invention belongs to the technical field of semiconductor power devices, and in particular to a semiconductor super junction power device and a manufacturing method thereof.
- Super Junction Power Devices are based on charge balancing technology that reduces on-resistance and parasitic capacitance, making superjunction power devices extremely fast switching characteristics, reducing switching losses and achieving higher power conversion efficiency.
- a known super junction power device includes a cell region for obtaining low on-resistance and a termination region for increasing the withstand voltage of the most marginal cell in the cell region.
- the terminal area has different number of columnar epitaxial doping regions 102, and is mainly used for the withstand voltage requirements of different products.
- the cell region includes a drain region 100 of the substrate epitaxial layer 101 and a plurality of columnar epitaxial doping regions 102 for forming a charge balance with the substrate epitaxial layer 101.
- the width of the columnar epitaxial doping region 102 and the adjacent columnar epitaxial doping The pitch of the inter-cells is equal to achieve charge balance; a body region 103 is disposed on the top of the columnar epitaxial doping region 102, and the body region 103 extends beyond the corresponding columnar epitaxial doping region 102 and extends to the substrate.
- a source region 106 is disposed on both sides of the body region 103, and a gate oxide layer 104 and a gate electrode 105 are disposed on the body region 103 and the substrate epitaxial layer 101.
- the Miller capacitance (Crss) and its corresponding gate-drain capacitance (Cgd) play a leading role in the switching speed of the super-junction power device. If the Cgd can be lowered, the super-super can be improved. The switching speed of the junction power device reduces the switching loss.
- the gate leakage capacitance (Cgd) will be abrupt, as shown in Figure 1b, which makes the gate of the super junction power device. The extreme voltage oscillation is severe.
- the super junction power device of the present invention employs a body structure having two or more unequal widths.
- the gate-to-drain capacitance abrupt speed of the super junction power device when turned on or off can be reduced, thereby reducing the gate voltage oscillation of the super junction power device.
- a semiconductor super junction power device includes a termination region and a cell region, the cell region including a drain region in the substrate epitaxial layer, a JFET region, and a plurality of columnar epitaxial doping regions, The top of each of the columnar epitaxial doping regions is respectively provided with a body region, and the body region is provided with two or more unequal widths, and the body region is provided with a source region.
- a gate oxide layer is disposed over the body region and the JFET region, and a gate is disposed on the gate oxide layer.
- the width of the body region of the present invention is sequentially set to: C, C+1D, C, C+1D, C, ...; or sequentially set to: C, C+1D, ..., C+nD, C+(n-1 ) D, ..., C, C+1D, ..., C+nD, C+(n-1)D, ..., C, ...; or set to: C, C, ..., C+1D, C+1D, ..., C+nD, C+nD, ..., C+(n-1)D, C+(n-1)D, ..., C, C, ..., where: n ⁇ 2.
- Each of the plurality of columnar epitaxial doped regions of the present invention has an equal width of each of the columnar epitaxial doped regions, and the spacing between adjacent columnar epitaxial doped regions is equal.
- the pitch can be set to: A, A+1B, A, A+1B, A, ...; or sequentially set to: A, A+1B, ..., A+nB, A+(n-1)B, ..., A, A+1B, ..., A+nB, A+(n-1)B, ..., A, ..., or sequentially set to: A, A, ..., A+1B, A+1B, ..., A+nB , A+nB, ..., A+(n-1)B, A+(n-1)B, ..., A, A, ..., wherein: n ⁇ 2.
- the gate of the present invention may be a full gate gate covering the channel region and the JFET region, or a split gate gate covering and extending beyond the channel region and over the JFET region.
- a field oxide layer is disposed between the gate and the gate oxide layer above the JFET region of the present invention, and the field oxide is The thickness of the layer is 2 to 10 times the thickness of the gate oxide layer.
- the epitaxial layer, the drain region and the source region of the substrate of the present invention each have a first doping type, and the columnar epitaxial doping region and the body region respectively have a second doping type.
- the first doping type is n-type doping
- the second doping type is p-type doping
- the first doping type is p-type doping
- the second doping type is N-type doping.
- a gate resistor is disposed on the body region and the substrate epitaxial layer of the present invention, and a dielectric layer is disposed between the gate resistor and the body region and the substrate epitaxial layer, and the gate passes through the gate resistor Connect to an external circuit.
- the invention discloses a method for manufacturing a semiconductor super junction power device, which comprises the following basic steps:
- Step 1 etching the epitaxial layer of the first doping type to form a columnar epitaxial doping region of a second doping type recessed in the epitaxial layer of the substrate for forming a charge balance with the impurity of the epitaxial layer of the substrate ;
- Step 2 forming a body region of a second doping type on top of the columnar epitaxial doping region, the body region extending beyond the opposite sides of the corresponding columnar epitaxial doping region and extending into the epitaxial layer of the substrate, and The body region is provided with two or more unequal widths;
- Step 3 forming a gate oxide layer over the body region and the substrate epitaxial layer, and forming a polysilicon dielectric layer over the gate oxide layer;
- Step 4 etching the polysilicon dielectric layer and the gate oxide layer, and the remaining polysilicon dielectric layer after etching forms a gate;
- Step 5 performing source region lithography, and then performing ion implantation of a first doping type to form a source region in the body region;
- Step 6 depositing an insulating dielectric layer and etching the insulating dielectric layer to form a contact hole, then depositing a metal layer and etching the metal layer to form an electrode contact body of the source region and an electrode contact body of the gate;
- Step 7 forming a drain region of a first doping type in the epitaxial layer of the substrate, and depositing a metal layer to form an electrode contact body of the drain region.
- a further preferred embodiment of the method for fabricating a semiconductor super junction power device proposed by the present invention is as follows under:
- step 1 of the present invention two or more pitches of different widths are disposed between adjacent columnar epitaxial doped regions.
- the gate oxide layer is made of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide or other insulating material having a high dielectric constant.
- a gate resistance is formed on the body region and the epitaxial layer of the substrate.
- step 5 of the present invention prior to performing source region lithography, a low concentration of the first doping type of ion implantation is performed in a self-aligned manner.
- two or more body structures having different widths are used, which can cause a sudden change in gate leakage capacitance of a super junction power device when turned on or off. The speed is reduced, thereby reducing the gate voltage oscillation of the super junction power device.
- a semiconductor super junction power device of the present invention also adopts the synergistic action of the columnar epitaxial doped region structure with unequal spacing and the body structure of different widths, and can introduce more gradual changes in the super junction power device. This makes the gate-drain capacitance abruptly smoother, further reducing gate voltage oscillation.
- a semiconductor super junction power device of the present invention can conveniently integrate a gate resistor inside the chip, and can further suppress gate voltage oscillation.
- FIG. 1 is a schematic cross-sectional view of a known semiconductor super junction power device.
- FIG. 2 is a schematic diagram of a gate leakage capacitance (Cgd) curve of a known semiconductor super junction power device when turned on and off.
- Cgd gate leakage capacitance
- FIG. 3 is a schematic cross-sectional view showing a first embodiment of a semiconductor super junction power device of the present invention.
- Embodiment 4 is a cross-sectional structural view showing Embodiment 2 of a semiconductor super junction power device of the present invention.
- Fig. 5 is a cross-sectional structural view showing a third embodiment of a semiconductor super junction power device of the present invention.
- Embodiment 4 is a cross-sectional structural view showing Embodiment 4 of a semiconductor super junction power device of the present invention.
- FIG. 7 is a schematic diagram showing a gate leakage capacitance (Cgd) curve of a semiconductor super junction power device of the present invention when turned on and off.
- Cgd gate leakage capacitance
- FIG. 8 is a schematic diagram showing a comparison of switching waveforms of a semiconductor super junction power device of the present invention and a prior art semiconductor super junction power device.
- 9 to 12 are schematic diagrams showing the process flow of an embodiment of a method of fabricating a semiconductor super junction power device of the present invention.
- a semiconductor super junction power device of the present invention includes a cell region for obtaining low on-resistance and a termination region for increasing the withstand voltage of the most marginal cell in the cell region.
- the terminal area is a general structure in the existing semiconductor super junction power devices, and has different design conclusions according to different product requirements. The specific structure of the termination region of the semiconductor super junction power device is not shown and described in the practice of the present invention.
- FIG. 3 is a cross-sectional structural view showing a first embodiment of a semiconductor super junction power device of the present invention
- FIG. 3 is a cross-sectional view showing a cell region of the semiconductor super junction power device of the present invention, and a semiconductor of the present invention.
- the cell region of the super junction power device includes: a first doping type substrate epitaxial layer 201 and a first doping type drain region 200 at the bottom of the substrate epitaxial layer 201; the material of the substrate epitaxial layer 201 is preferably silicon. But not limited to silicon.
- the inside of the substrate epitaxial layer 201 is provided with a plurality of columnar epitaxial doping regions 202 recessed in the substrate epitaxial layer 201 for forming a charge balance with the substrate epitaxial layer 201 impurities, in Embodiment 1 Only three columnar epitaxial doping regions 202 are shown, the number of which can be determined according to product design requirements; preferably, each columnar epitaxial doping region 202 has the same width and between adjacent columnar epitaxial doping regions 202. The spacing is equal to achieve charge balance.
- Body regions 203 of a second doping type are respectively disposed on top of each of the columnar epitaxial doping regions 202, and each of the body regions 203 extends beyond the corresponding columnar epitaxial doping regions 202 and extends to the substrate epitaxial layer 201. internal.
- the body region 203 of the present invention is provided with two or more different widths.
- the body region is exemplarily shown to have three different widths of aa1, aa2, aa3, preferably, the present invention
- the width combination of the body region 203 may be sequentially set to: C, C+1D, C, C+1D, C, ...; or sequentially set to: C, C+1D, ..., C+nD, C+(n-1) D, ..., C, C+1D, ..., C+nD, C+(n-1)D, ..., C, ...; or set to: C, C, ..., C+1D, C+1D, ...
- n ⁇ 2 C is the basic width of the body region;
- C is the basic width of the body region;
- the specific values of n, C, and D are determined according to product design requirements.
- the body structure of different widths can reduce the sudden change of gate-drain capacitance when the super junction power device is turned on and off.
- the portion of the substrate epitaxial layer between adjacent body regions 203 is the JFET region 500 of the device, which is the parasitic FET region within the superjunction power device.
- a source region 206 of a first doping type is provided inside each body region 203, respectively, in the body region 203 and A gate oxide layer 204 is further disposed on the JFET region, and a gate electrode 205 is disposed on the gate oxide layer 204.
- the gate electrode completely covers the gate oxide layer 204 over the JFET region 500, and is a full gate structure. Gate.
- the gate electrodes are separated by an insulating dielectric layer, and a contact hole is further disposed inside the insulating dielectric layer, and the contact hole is filled with a metal layer, and the metal layer should cover the gate.
- the ohmic contact is formed with the body region 203 and the source region 206 at the same time and at the same time.
- the first doping type and the second doping type described in the present invention are opposite doping types, that is, if the first doping type is n-type doping, the second doping type is p-type doping If the first doping type is p-type doping, the second doping type is n-type doping.
- Embodiment 4 is a cross-sectional structural view of Embodiment 2 of a semiconductor super junction power device according to the present invention.
- a semiconductor super junction power device of Embodiment 2 is gated.
- the pole 205 covers the channel region (the channel region is the inversion layer formed in the body region during operation of the device, not shown in FIG. 4) and extends beyond the channel region to ensure full coverage of the channel region, in the JFET
- the gate 205 forming the split gate structure is turned off over the region 500, and the gate 205 of the split gate structure can reduce the gate-drain capacitance, thereby reducing the gate-drain capacitance abrupt change of the device during turn-on and turn-off.
- FIG. 5 is a cross-sectional structural view of a third embodiment of a semiconductor super junction power device according to the present invention.
- a semiconductor super junction power device of Embodiment 3 is Above the JFET region 500 is disposed a field oxide layer 300 between the gate 205 and the gate oxide layer 204 to reduce the gate-drain capacitance, thereby reducing the gate-to-drain capacitance abrupt change of the device during turn-on and turn-off.
- the thickness of the field oxide layer 300 is 2 to 10 times the thickness of the gate oxide layer 204.
- FIG. 6 is a cross-sectional structural view of a fourth embodiment of a semiconductor super junction power device according to the present invention.
- a semiconductor super junction power device of Embodiment 4 is When the body structure of different widths is used, there are two or more unequal spacings between adjacent columnar epitaxial doping regions 202, and two types are not shown in Embodiment 4. Same spacing bb1 and bb2.
- the spacing between adjacent columnar epitaxial doping regions 202 may be sequentially set to: A, A+1B, A, A+1B, A, ...; or sequentially set to: A, A+1B, ..., A+nB, A+(n-1)B, ..., A, A+1B, ..., A+nB, A+(n-1)B, ..., A, ..., or sequentially set to: A, A, ...
- n ⁇ 2 A is the basic pitch size of the adjacent columnar epitaxial doped regions
- B is the varying pitch size of the adjacent columnar epitaxial doped regions
- FIG. 7 is a schematic diagram showing a gate leakage capacitance (Cgd) curve of a semiconductor super junction power device of the present invention when turned on and off.
- Cgd gate leakage capacitance
- FIG. 8 is a schematic diagram showing a comparison of switching waveforms of a semiconductor super junction power device of the present invention and a prior art semiconductor super junction power device. As can be seen from FIG. 8, the Vds of a semiconductor super junction power device of the present invention is switched. The impulse is significantly reduced.
- FIG. 12 are schematic diagrams showing the process flow of an embodiment of a method for fabricating a semiconductor super junction power device according to the present invention, specifically taking the super junction power device shown in the manufacturing embodiment 2 as an example.
- a hard mask layer is first deposited on the surface of the first doped type substrate epitaxial layer 201, and then photolithography and etching are performed to form a plurality of hard masks in the hard mask layer.
- the impurities form a plurality of columnar epitaxial doping regions 202 of a second doping type that are charge balanced.
- the position of the body region is first defined by a photolithography process, and then ion implantation of a second doping type is performed to form a second doping type on the top of each of the columnar epitaxial doping regions 202.
- the body region 203 extends beyond the corresponding columnar epitaxial doping regions 202 to extend to the inside of the substrate epitaxial layer 201.
- the body region 203 is exemplarily shown to have three different widths of aa1, aa2, and aa3.
- a gate oxide layer 204 is formed on the surface of the body region 203 and the substrate epitaxial layer 201, and a polysilicon dielectric layer is formed over the gate oxide layer 204; then photolithography is performed to define the super junction power.
- a gate position of the device, and then etching the polysilicon dielectric layer and the gate oxide layer 204, and the remaining polysilicon dielectric layer after etching forms a gate 205 of the device, which is a gate 205 of the split gate structure in this embodiment;
- the material of layer 204 is silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide or other insulating material having a high dielectric constant.
- a gate resistor located on the epitaxial layer and the body region of the substrate may be simultaneously formed by controlling the pattern of the photolithographic mask, and the gate resistor may pass through the gate oxide layer and the body region.
- the substrate epitaxial layer is isolated.
- source region lithography is performed to define the source region position of the device, and then ion implantation of the first doping type is performed, and source regions 206 of the device are formed on both sides of the inside of the body region 203.
- a low concentration of the first doping type of ion implantation may be performed in a self-aligned manner to adjust the impurity doping concentration on the surface of the epitaxial layer 201 of the substrate, thereby suppressing the parasitic junction type.
- Field effect tube effect followed by source region lithography and ion implantation.
- a layer of insulating dielectric is deposited, and the material of the insulating dielectric layer may be silicon glass, borophosphosilicate glass or phosphorous silicon glass; then photolithographically defining the position of the contact hole, and then etching the insulating dielectric layer to be in the insulating medium A contact hole is formed inside the layer; then a second doping type of ion implantation is performed to form a body contact region in the body region, and the body region contact region is a well-known structure for reducing the contact resistance of the subsequently formed ohmic contact.
- a drain region of a first doping type is formed in the epitaxial layer of the substrate, and an electrode contact of the drain region is formed by depositing a metal layer.
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Abstract
Description
Claims (17)
- 一种半导体超级结功率器件,包括终端区和元胞区,所述元胞区包括衬底外延层内的漏区、JFET区和多个柱状外延掺杂区,所述多个柱状外延掺杂区中的每个柱状外延掺杂区的顶部分别设有体区,其特征在于,所述体区设有两种或两种以上不相等的宽度,所述体区内设有源区,所述体区和JFET区之上设有栅氧化层,所述栅氧化层之上设有栅极。
- 根据权利要求1所述的一种半导体超级结功率器件,其特征在于,所述体区的宽度依次设为:C、C+1D、C、C+1D、C、…;或者依次设为:C、C+1D、…、C+nD、C+(n-1)D、…、C、C+1D、…、C+nD、C+(n-1)D、…、C、…;或者依次设为:C、C、…、C+1D、C+1D、…、C+nD、C+nD、…、C+(n-1)D、C+(n-1)D、…、C、C、…,其中:n≥2。
- 根据权利要求1所述的一种半导体超级结功率器件,其特征在于,所述多个柱状外延掺杂区中的每个柱状外延掺杂区的宽度相等,且相邻的柱状外延掺杂区之间的间距相等。
- 根据权利要求1所述的一种半导体超级结功率器件,其特征在于,所述多个柱状外延掺杂区中的相邻的柱状外延掺杂区之间设有两种或两种以上不相等宽度的间距。
- 根据权利要求4所述的一种半导体超级结功率器件,其特征在于,所述相邻的柱状外延掺杂区之间的间距依次设为:A、A+1B、A、A+1B、A、…;或者依次设为:A、A+1B、…、A+nB、A+(n-1)B、…、A、A+1B、…、A+nB、A+(n-1)B、…、A、…,或者依次设为:A、A、…、A+1B、A+1B、…、A+nB、A+nB、…、A+(n-1)B、A+(n-1)B、…、A、A、…,其中:n≥2。
- 根据权利要求1所述的一种半导体超级结功率器件,其特征在于,所述栅极是覆盖沟道区和所述JFET区的全栅栅极。
- 根据权利要求1所述的一种半导体超级结功率器件,其特征在于,所述栅极是覆盖并超出沟道区且在所述JFET区之上断开的分栅栅极。
- 根据权利要求1所述的一种半导体超级结功率器件,其特征在于,在所述JFET区之上的栅极与栅氧化层之间设有场氧化层,该场氧化层的厚度是所述栅氧化层厚度的2~10倍。
- 根据权利要求1所述的一种半导体超级结功率器件,其特征在于,所述衬底外延层、漏区和源区分别具有第一掺杂类型,所述柱状外延掺杂区和体区分别具有第二掺杂类型。
- 根据权利要求9所述的一种半导体超级结功率器件,其特征在于,所述第一掺杂类型为n型掺杂,所述第二掺杂类型为p型掺杂。
- 根据权利要求9所述的一种半导体超级结功率器件,其特征在于,所述第一掺杂类型为p型掺杂,所述第二掺杂类型为n型掺杂。
- 根据权利要求1所述的一种半导体超级结功率器件,其特征在于,所述体区和衬底外延层之上设有栅极电阻,该栅极电阻与所述体区和衬底外延层之间设有介质层,所述栅极通过所述栅极电阻与外部电路连接。
- 一种半导体超级结功率器件的制造方法,其特征在于,包括如下基本步骤:步骤一:对第一掺杂类型的衬底外延层进行刻蚀,形成凹陷在衬底外延层内的用于与衬底外延层杂质形成电荷平衡的第二掺杂类型的柱状外延掺杂区;步骤二:在所述柱状外延掺杂区的顶部形成第二掺杂类型的具有两种或两种以上不相等宽度的体区,该体区超出相对应的柱状外延掺杂区的两侧并延伸至所述衬底外延层内;步骤三:在所述体区和衬底外延层之上形成栅氧化层,并在该栅氧化层之上形成多晶硅介质层;步骤四:对所述多晶硅介质层和栅氧化层进行刻蚀,刻蚀后剩余的多晶硅介质层形成栅极;步骤五:进行源区光刻,然后进行第一掺杂类型的离子注入,在所述体区 内形成源区;步骤六:淀积绝缘介质层并刻蚀所述绝缘介质层形成接触孔,然后淀积金属层并刻蚀所述金属层以形成源区的电极接触体和栅极的电极接触体;步骤七:在所述衬底外延层内形成第一掺杂类型的漏区,并淀积金属层形成漏区的电极接触体。
- 根据权利要求13所述的一种半导体超级结功率器件的制造方法,其特征在于,步骤一所述相邻的柱状外延掺杂区之间设有两种或两种以上不同宽度的间距。
- 根据权利要求13所述的一种半导体超级结功率器件的制造方法,其特征在于,步骤三所述栅氧化层的材质为氧化硅、氮化硅、氮氧化硅、氧化铪或具有高介电常数的其它绝缘材料。
- 根据权利要求13所示的一种半导体超级结功率器件的制造方法,其特征在于,步骤四刻蚀所述多晶硅介质层形成所述栅极时,同时形成位于所述体区和衬底外延层之上的栅极电阻。
- 根据权利要求13所示的一种半导体超级结功率器件的制造方法,其特征在于,步骤五所述在进行源区光刻前,先自对准地进行低浓度的第一掺杂类型的离子注入。
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US15/532,530 US10411116B2 (en) | 2015-04-30 | 2016-04-08 | Semiconductor super-junction power device and manufacturing method therefor |
JP2017553301A JP6423110B2 (ja) | 2015-04-30 | 2016-04-08 | 半導体超接合パワーデバイス及びその製造方法 |
CN201680010382.3A CN107408574B (zh) | 2015-04-30 | 2016-04-08 | 一种半导体超级结功率器件及其制造方法 |
KR1020177025929A KR101962834B1 (ko) | 2015-04-30 | 2016-04-08 | 반도체 초접합 전력 소자 및 그 제조방법 |
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2016
- 2016-04-08 JP JP2017553301A patent/JP6423110B2/ja active Active
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US20180269311A1 (en) | 2018-09-20 |
DE112016001988B4 (de) | 2021-10-21 |
KR101962834B1 (ko) | 2019-03-27 |
CN107408574A (zh) | 2017-11-28 |
CN107408574B (zh) | 2021-03-30 |
JP2018505566A (ja) | 2018-02-22 |
JP6423110B2 (ja) | 2018-11-14 |
US10411116B2 (en) | 2019-09-10 |
DE112016001988T5 (de) | 2018-01-04 |
KR20170113668A (ko) | 2017-10-12 |
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