CN107408574A - 一种半导体超级结功率器件及其制造方法 - Google Patents

一种半导体超级结功率器件及其制造方法 Download PDF

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CN107408574A
CN107408574A CN201680010382.3A CN201680010382A CN107408574A CN 107408574 A CN107408574 A CN 107408574A CN 201680010382 A CN201680010382 A CN 201680010382A CN 107408574 A CN107408574 A CN 107408574A
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power device
super junction
junction power
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CN107408574B (zh
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刘磊
袁愿林
王鹏飞
刘伟
龚轶
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Suzhou Oriental Semiconductor Co Ltd
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Abstract

该申请属于半导体功率器件技术领域，特别是涉及一种半导体超级结功率器件及其制造方法。该超级结功率器件包括终端区和元胞区，该元胞区包括衬底外延层(201)内的漏区(200)、JFET区(500)和多个柱状外延掺杂区(202)，该多个柱状外延掺杂区(202)中的每个柱状外延掺杂区(202)的顶部分别设有体区(203)，该体区(203)设有两种或两种以上不相等的宽度，该体区(203)内设有源区(206)，该体区(203)和JFET(500)区之上设有栅氧化层(204)，该栅氧化层(204)之上设有栅极(205)。该超级结功率器件采用不同宽度的体区结构，能够使得超级结功率器件在开启或关断时的栅漏电容突变速度降低，从而降低由栅漏电容突变引起的栅极电压震荡。

Description

一种半导体超级结功率器件及其制造方法 技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种半导体超级结功率器件及其制造方法。
背景技术
超级结功率器件是基于电荷平衡技术，可以降低导通电阻和寄生电容，使得超级结功率器件具有极快的开关特性，可以降低开关损耗，实现更高的功率转换效率。如图1所示，公知的超级结功率器件包括元胞区和终端区，元胞区用于获得低导通电阻，终端区用于提高元胞区中最边缘的元胞的耐压。终端区根据产品具体要求，其柱状外延掺杂区102的个数不同，主要用于不同产品的耐压要求。元胞区包括衬底外延层101的漏区100和用于与衬底外延层101杂质形成电荷平衡的多个柱状外延掺杂区102，柱状外延掺杂区102的宽度以及相邻柱状外延掺杂区的间距都是相等的，用以实现电荷平衡；在柱状外延掺杂区102的顶部设有体区103，体区103超出相对应的柱状外延掺杂区102两侧并延伸至衬底外延层101内；在体区103的内部两侧分别设有源区106；在体区103和衬底外延层101之上设有栅氧化层104和栅极105。
超级结功率器件在开启和关断过程中，米勒电容(Crss)及其所对应的栅漏电容(Cgd)对超级结功率器件的开关速度起主导作用，若能降低Cgd，就可提高超级结功率器件的开关速度、降低开关损耗；同时，公知的超级结功率器件在开启和关断时，栅漏电容(Cgd)会发生突变，如图1b所示，这使得超级结功率器件的栅极电压震荡严重。
发明内容
本发明的目的是为克服现有技术所存在的不足而提供一种半导体超级结功率器件及其制造方法，本发明的超级结功率器件采用具有两种或两种以上不相等宽度的体区结构，能够使得超级结功率器件在开启或关断时的栅漏电容突变速度降低，从而减少超级结功率器件的栅极电压震荡。
根据本发明提出的一种半导体超级结功率器件，包括终端区和元胞区，所述元胞区包括衬底外延层内的漏区、JFET区和多个柱状外延掺杂区，所述多个柱状外延掺杂区中的每个柱状外延掺杂区的顶部分别设有体区，所述体区设有两种或两种以上不相等的宽度，所述体区内设有源区,所述体区和JFET区之上设有栅氧化层，所述栅氧化层之上设有栅极。
本发明提出的一种半导体超级结功率器件的进一步优选方案如下：
本发明所述体区的宽度依次设为：C、C+1D、C、C+1D、C、…；或者依次设为：C、C+1D、…、C+nD、C+(n-1)D、…、C、C+1D、…、C+nD、C+(n-1)D、…、C、…；或者依次设为：C、C、…、C+1D、C+1D、…、C+nD、C+nD、…、C+(n-1)D、C+(n-1)D、…、C、C、…，其中：n≥2。
本发明所述多个柱状外延掺杂区中的每个柱状外延掺杂区的宽度相等，且相邻的柱状外延掺杂区之间的间距相等。
本发明所述多个柱状外延掺杂区中的相邻的柱状外延掺杂区之间设有两种或两种以上不相等宽度的间距，且所述相邻的柱状外延掺杂区之间的间距可依次设为：A、A+1B、A、A+1B、A、…；或者依次设为：A、A+1B、…、A+nB、A+(n-1)B、…、A、A+1B、…、A+nB、A+(n-1)B、…、A、…，或者依次设为：A、A、…、A+1B、A+1B、…、A+nB、A+nB、…、A+(n-1)B、A+(n-1)B、…、A、A、…，其中：n≥2。
本发明所述栅极可以是覆盖沟道区和所述JFET区的全栅栅极，也可以是覆盖并超出沟道区且在所述JFET区之上断开的分栅栅极。
本发明所述JFET区之上的栅极与栅氧化层之间设有场氧化层，该场氧化 层的厚度是所述栅氧化层厚度的2～10倍。
本发明所述衬底外延层、漏区和源区分别具有第一掺杂类型，所述柱状外延掺杂区和体区分别具有第二掺杂类型。其中所述第一掺杂类型为n型掺杂，所述第二掺杂类型为p型掺杂；或者，所述第一掺杂类型为p型掺杂，所述第二掺杂类型为n型掺杂。
本发明所述体区和衬底外延层之上设有栅极电阻，该栅极电阻与所述体区和衬底外延层之间设有介质层，所述栅极通过所述栅极电阻与外部电路连接。
本发明提出的一种半导体超级结功率器件的制造方法，包括如下基本步骤：
步骤一：对第一掺杂类型的衬底外延层进行刻蚀，形成凹陷在衬底外延层内的用于与衬底外延层杂质形成电荷平衡的第二掺杂类型的柱状外延掺杂区；
步骤二：在所述柱状外延掺杂区的顶部形成第二掺杂类型的体区，该体区超出相对应的柱状外延掺杂区的两侧并延伸至所述衬底外延层内，且所述体区设有两种或两种以上不相等的宽度；
步骤三：在所述体区和衬底外延层之上形成栅氧化层，并在该栅氧化层之上形成多晶硅介质层；
步骤四：对所述多晶硅介质层和栅氧化层进行刻蚀，刻蚀后剩余的多晶硅介质层形成栅极；
步骤五：进行源区光刻，然后进行第一掺杂类型的离子注入，在所述体区内形成源区；
步骤六：淀积绝缘介质层并刻蚀所述绝缘介质层形成接触孔，然后淀积金属层并刻蚀所述金属层以形成源区的电极接触体和栅极的电极接触体；
步骤七：在所述衬底外延层内形成第一掺杂类型的漏区，并淀积金属层形成漏区的电极接触体。
本发明提出的一种半导体超级结功率器件的制造方法的进一步优选方案如 下：
本发明步骤一所述相邻的柱状外延掺杂区之间设有两种或两种以上不同宽度的间距。
本发明步骤三所述栅氧化层的材质为氧化硅、氮化硅、氮氧化硅、氧化铪或具有高介电常数的其它绝缘材料。
本发明步骤四刻蚀所述多晶硅介质层形成所述栅极时，同时形成位于所述体区和衬底外延层之上的栅极电阻。
本发明步骤五所述在进行源区光刻前，先自对准地进行低浓度的第一掺杂类型的离子注入。
本发明与现有技术相比其显著优点在于：
第一，本发明的一种半导体超级结功率器件的元胞区内，采用两种或两种以上不同宽度的体区结构，能够使得超级结功率器件在开启或关断时的栅漏电容突变速度降低，从而减少超级结功率器件的栅极电压震荡。
第二，本发明的一种半导体超级结功率器件，还采用不相等间距的柱状外延掺杂区结构与不同宽度的体区结构的协同作用，能够在超级结功率器件中引入更多的缓变，使得栅漏电容突变变得更加平滑，进一步降低了栅极电压震荡。
第三，本发明的一种半导体超级结功率器件，可以方便地在芯片内部集成栅极电阻，能够进一步抑制栅极电压震荡。
附图说明
图1是公知的一种半导体超级结功率器件的剖面结构示意图。
图2是公知的一种半导体超级结功率器件在开启和关断时的栅漏电容(Cgd)变化曲线的示意图。
图3是本发明的一种半导体超级结功率器件的实施例1的剖面结构示意 图。
图4是本发明的一种半导体超级结功率器件的实施例2的剖面结构示意图。
图5是本发明的一种半导体超级结功率器件的实施例3的剖面结构示意图。
图6是本发明的一种半导体超级结功率器件的实施例4的剖面结构示意图。
图7是本发明的一种半导体超级结功率器件在开启和关断时的栅漏电容(Cgd)变化曲线的示意图。
图8是本发明的一种半导体超级结功率器件与现有技术的半导体超级结功率器件的开关波形对比示意图。
图9至图12是本发明的一种半导体超级结功率器件的制造方法的一个实施例的工艺流程示意图。
具体实施方式
下面结合附图和实施例对本发明的具体实施方式作进一步详细的说明。
为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸；说明书附图是示意性的，不应限定本发明的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制造引起的偏差等，如刻蚀得到的曲线通常具有弯曲或圆润的特点，在本发明实施例中均以矩形表示。
本发明的一种半导体超级结功率器件包括元胞区和终端区，元胞区用于获得低导通电阻，终端区用于提高元胞区中最边缘的元胞的耐压。终端区是现有半导体超级结功率器件中的通用结构，根据不同产品的要求有不同的设计结 构，在本发明实施列中不再展示和描述半导体超级结功率器件的终端区的具体结构。
图3是本发明的一种半导体超级结功率器件的实施例1的剖面结构示意图，图3中示出了本发明的半导体超级结功率器件的元胞区的剖面结构，本发明的一种半导体超级结功率器件的元胞区包括：第一掺杂类型的衬底外延层201和衬底外延层201底部的第一掺杂类型的漏区200；衬底外延层201的材质优选为硅，但不局限于硅。衬底外延层201的内部设有凹陷在衬底外延层201内的用于与衬底外延层201杂质形成电荷平衡的多个第二掺杂类型的柱状外延掺杂区202，实施例1中仅示出了3个柱状外延掺杂区202，其数量多少可根据产品设计要求确定；优选的，每个柱状外延掺杂区202的宽度相等，且相邻的柱状外延掺杂区202之间的间距相等，用以实现电荷平衡。
在每个柱状外延掺杂区202的顶部分别设有第二掺杂类型的体区203，且每个体区203超出相对应的柱状外延掺杂区202两侧并延伸至衬底外延层201的内部。本发明的体区203设有两种或两种以上的不同宽度，在实施例1中，示例性的示出了体区具有aa1、aa2、aa3三种不同的宽度，优选的，本发明的体区203的宽度组合可以依次设为：C、C+1D、C、C+1D、C、…；或者依次设为：C、C+1D、…、C+nD、C+(n-1)D、…、C、C+1D、…、C+nD、C+(n-1)D、…、C、…；或者依次设为：C、C、…、C+1D、C+1D、…、C+nD、C+nD、…、C+(n-1)D、C+(n-1)D、…、C、C、…，其中：n≥2；C为体区的基本宽度；D为体区的变化的宽度，n、C、D的具体数值依据产品设计要求确定。不同宽度的体区结构可以使得超级结功率器件在开启和关断时的栅漏电容突变速度降低。
在相邻的体区203之间的衬底外延层部分是器件的JFET区500，JFET区500是超级结功率器件内寄生的结型场效应管区域。
在每个体区203的内部分别设有第一掺杂类型的源区206，在体区203和 JFET区之上还设有栅氧化层204，在栅氧化层204之上设有栅极205，本实施列中，栅极完全覆盖JFET区500之上的栅氧化层204，为全栅结构的栅极。
在本发明的半导体超级结功率器件中，栅极之间由绝缘介质层隔离，在所述绝缘介质层的内部还设有接触孔，该接触孔内填充有金属层，该金属层应覆盖栅极并且同时与体区203和源区206形成欧姆接触。凡现有技术中的通用结构，在本发明实施列中不再进行示意和详细描述。
本发明中描述的第一掺杂类型和第二掺杂类型为相反的掺杂类型，即若所述第一掺杂类型为n型掺杂，则所述第二掺杂类型为p型掺杂；若所述第一掺杂类型为p型掺杂，则所述第二掺杂类型为n型掺杂。
图4是本发明提出的一种半导体超级结功率器件的实施例2的剖面结构示意图，与图3所示的半导体超级结功率器件相比较，实施例2的一种半导体超级结功率器件，栅极205覆盖沟道区(沟道区是器件在工作时在体区内形成的反型层，图4中未示出)并超出覆盖沟道区来确保对沟道区的全覆盖,在JFET区500之上断开形成分栅结构的栅极205，分栅结构的栅极205可以降低栅漏电容，从而降低器件在开启和关断时的栅漏电容突变。
图5是本发明提出的一种半导体超级结功率器件的实施例3的剖面结构示意图，与图3所示的半导体超级结功率器件相比较，实施例3的一种半导体超级结功率器件，在JFET区500之上设置有位于栅极205和栅氧化层204之间的场氧化层300，用以降低栅漏电容，从而降低器件在开启和关断时的栅漏电容突变。优选的，场氧化层300的厚度是所述栅氧化层204厚度的2倍至10倍。
图6是本发明提出的一种半导体超级结功率器件的实施例4的剖面结构示意图，与图3所示的半导体超级结功率器件相比较，实施例4的一种半导体超级结功率器件，在采用不同宽度的体区结构的同时，还使得相邻的柱状外延掺杂区202之间具有两种或两种以上不相等的间距，在实施例4中示出了两种不 同的间距bb1和bb2。优选的，相邻的柱状外延掺杂区202之间的间距可以依次设为：A、A+1B、A、A+1B、A、…；或者依次设为：A、A+1B、…、A+nB、A+(n-1)B、…、A、A+1B、…、A+nB、A+(n-1)B、…、A、…，或者依次设为：A、A、…、A+1B、A+1B、…、A+nB、A+nB、…、A+(n-1)B、A+(n-1)B、…、A、A、…，其中：n≥2；A为相邻柱状外延掺杂区的基本间距尺寸；B为相邻柱状外延掺杂区的变化的间距尺寸，n、A、B的具体数值依据具体产品设计要求确定。
图7是本发明的一种半导体超级结功率器件在开启和关断时的栅漏电容(Cgd)变化曲线的示意图。由图7可知，本发明的一种半导体超级结功率器件能够在开启和关断时使得栅漏电容突变速度降低，进而能够降低由栅漏电容突变引起的栅极电压震荡。
图8是本发明的一种半导体超级结功率器件与现有技术的半导体超级结功率器件的开关波形对比示意图，由图8可知，本发明的一种半导体超级结功率器件在开关时的Vds过冲明显减小。
图9至图12是本发明的一种半导体超级结功率器件的制造方法的一个实施例的工艺流程示意图，具体以制造实施例2所示的超级结功率器件为例。
首先，如图9所示，先在第一掺杂类型的衬底外延层201的表面淀积硬掩膜层，再进行光刻和刻蚀以在硬掩膜层内形成多个硬掩膜层开口，然后以硬掩膜层为掩膜刻蚀衬底外延层201以在衬底外延层201内形成多个柱状凹槽，刻蚀掉硬掩膜层后淀积第二掺杂类型的外延层并使得第二掺杂类型的外延层填满所述柱状凹槽，最后进行平坦化处理以在衬底外延层201内形成凹陷在衬底外延层201内的用于与衬底外延层的杂质形成电荷平衡的多个第二掺杂类型的柱状外延掺杂区202。
接下来，如图10所示，先通过光刻工艺定义体区的位置，然后进行第二掺杂类型的离子注入，在每个柱状外延掺杂区202的顶部形成第二掺杂类型的 体区203，体区203超出相对应的柱状外延掺杂区202两侧以延伸至衬底外延层201的内部。本实施例中，示例性的示出了体区203具有aa1、aa2、aa3三种不同宽度。
接下来，如图11所示，在体区203和衬底外延层201的表面形成栅氧化层204，并在栅氧化层204之上形成多晶硅介质层；接着进行光刻以定义出超结功率器件的栅极位置，然后刻蚀所述多晶硅介质层和栅氧化层204，刻蚀后剩余的多晶硅介质层形成器件的栅极205，本实施例中为分栅结构的栅极205；栅氧化层204的材质为氧化硅、氮化硅、氮氧化硅、氧化铪或具有高介电常数的其它绝缘材料。
可选的，在形成栅极205时，还可以通过控制光刻掩膜版的图形同时形成位于衬底外延层和体区之上的栅极电阻，栅极电阻可以通过栅氧化层与体区、衬底外延层隔离。
接下来，如图12所示，进行源区光刻以定义出器件的源区位置，然后进行第一掺杂类型的离子注入，在体区203的内部的两侧形成器件的源区206。优选的，在形成源区206前，可以先自对准地进行低浓度的第一掺杂类型的离子注入，用以调节衬底外延层201表面的杂质掺杂浓度，进而抑制寄生的结型场效应管效应，然后再进行源区光刻和离子注入。
最后，淀积一层绝缘介质层，绝缘介质层的材质可以为硅玻璃、硼磷硅玻璃或磷硅玻璃；之后进行光刻定义出接触孔的位置，然后刻蚀绝缘介质层以在绝缘介质层的内部形成接触孔；之后进行第二掺杂类型的离子注入，在体区内形成体区接触区，体区接触区为业界所熟知的结构，用于降低后续形成的欧姆接触的接触电阻；然后淀积一层金属层，金属层在接触孔内同时与体区和源区形成欧姆接触，然后刻蚀所述金属层以形成源区的电极接触体和栅极的电极接触体；最后，在衬底外延层内形成第一掺杂类型的漏区，并淀积金属层形成漏区的电极接触体。以上工艺均为业界所熟知的，本发明实施列中不再详细描 述。
本发明的具体实施方式中凡未涉到的说明属于本领域的公知技术，可参考公知技术加以实施。
以上具体实施方式及实施例是对本发明提出的一种半导体超级结功率器件及其制造方法的技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (17)

  1. 一种半导体超级结功率器件，包括终端区和元胞区，所述元胞区包括衬底外延层内的漏区、JFET区和多个柱状外延掺杂区，所述多个柱状外延掺杂区中的每个柱状外延掺杂区的顶部分别设有体区，其特征在于，所述体区设有两种或两种以上不相等的宽度，所述体区内设有源区,所述体区和JFET区之上设有栅氧化层，所述栅氧化层之上设有栅极。
  2. 根据权利要求1所述的一种半导体超级结功率器件，其特征在于，所述体区的宽度依次设为：C、C+1D、C、C+1D、C、…；或者依次设为：C、C+1D、…、C+nD、C+(n-1)D、…、C、C+1D、…、C+nD、C+(n-1)D、…、C、…；或者依次设为：C、C、…、C+1D、C+1D、…、C+nD、C+nD、…、C+(n-1)D、C+(n-1)D、…、C、C、…，其中：n≥2。
  3. 根据权利要求1所述的一种半导体超级结功率器件，其特征在于，所述多个柱状外延掺杂区中的每个柱状外延掺杂区的宽度相等，且相邻的柱状外延掺杂区之间的间距相等。
  4. 根据权利要求1所述的一种半导体超级结功率器件，其特征在于，所述多个柱状外延掺杂区中的相邻的柱状外延掺杂区之间设有两种或两种以上不相等宽度的间距。
  5. 根据权利要求4所述的一种半导体超级结功率器件，其特征在于，所述相邻的柱状外延掺杂区之间的间距依次设为：A、A+1B、A、A+1B、A、…；或者依次设为：A、A+1B、…、A+nB、A+(n-1)B、…、A、A+1B、…、A+nB、A+(n-1)B、…、A、…，或者依次设为：A、A、…、A+1B、A+1B、…、A+nB、A+nB、…、A+(n-1)B、A+(n-1)B、…、A、A、…，其中：n≥2。
  6. 根据权利要求1所述的一种半导体超级结功率器件，其特征在于，所述栅极是覆盖沟道区和所述JFET区的全栅栅极。
  7. 根据权利要求1所述的一种半导体超级结功率器件，其特征在于，所述栅极是覆盖并超出沟道区且在所述JFET区之上断开的分栅栅极。
  8. 根据权利要求1所述的一种半导体超级结功率器件，其特征在于，在所述JFET区之上的栅极与栅氧化层之间设有场氧化层，该场氧化层的厚度是所述栅氧化层厚度的2～10倍。
  9. 根据权利要求1所述的一种半导体超级结功率器件，其特征在于，所述衬底外延层、漏区和源区分别具有第一掺杂类型，所述柱状外延掺杂区和体区分别具有第二掺杂类型。
  10. 根据权利要求9所述的一种半导体超级结功率器件，其特征在于，所述第一掺杂类型为n型掺杂，所述第二掺杂类型为p型掺杂。
  11. 根据权利要求9所述的一种半导体超级结功率器件，其特征在于，所述第一掺杂类型为p型掺杂，所述第二掺杂类型为n型掺杂。
  12. 根据权利要求1所述的一种半导体超级结功率器件，其特征在于，所述体区和衬底外延层之上设有栅极电阻，该栅极电阻与所述体区和衬底外延层之间设有介质层，所述栅极通过所述栅极电阻与外部电路连接。
  13. 一种半导体超级结功率器件的制造方法，其特征在于，包括如下基本步骤：
    步骤一：对第一掺杂类型的衬底外延层进行刻蚀，形成凹陷在衬底外延层内的用于与衬底外延层杂质形成电荷平衡的第二掺杂类型的柱状外延掺杂区；
    步骤二：在所述柱状外延掺杂区的顶部形成第二掺杂类型的具有两种或两种以上不相等宽度的体区，该体区超出相对应的柱状外延掺杂区的两侧并延伸至所述衬底外延层内；
    步骤三：在所述体区和衬底外延层之上形成栅氧化层，并在该栅氧化层之上形成多晶硅介质层；
    步骤四：对所述多晶硅介质层和栅氧化层进行刻蚀，刻蚀后剩余的多晶硅介质层形成栅极；
    步骤五：进行源区光刻，然后进行第一掺杂类型的离子注入，在所述体区 内形成源区；
    步骤六：淀积绝缘介质层并刻蚀所述绝缘介质层形成接触孔，然后淀积金属层并刻蚀所述金属层以形成源区的电极接触体和栅极的电极接触体；
    步骤七：在所述衬底外延层内形成第一掺杂类型的漏区，并淀积金属层形成漏区的电极接触体。
  14. 根据权利要求13所述的一种半导体超级结功率器件的制造方法，其特征在于，步骤一所述相邻的柱状外延掺杂区之间设有两种或两种以上不同宽度的间距。
  15. 根据权利要求13所述的一种半导体超级结功率器件的制造方法，其特征在于，步骤三所述栅氧化层的材质为氧化硅、氮化硅、氮氧化硅、氧化铪或具有高介电常数的其它绝缘材料。
  16. 根据权利要求13所示的一种半导体超级结功率器件的制造方法，其特征在于，步骤四刻蚀所述多晶硅介质层形成所述栅极时，同时形成位于所述体区和衬底外延层之上的栅极电阻。
  17. 根据权利要求13所示的一种半导体超级结功率器件的制造方法，其特征在于，步骤五所述在进行源区光刻前，先自对准地进行低浓度的第一掺杂类型的离子注入。
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