WO2023087684A1 - 半导体超结功率器件 - Google Patents

半导体超结功率器件 Download PDF

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WO2023087684A1
WO2023087684A1 PCT/CN2022/098643 CN2022098643W WO2023087684A1 WO 2023087684 A1 WO2023087684 A1 WO 2023087684A1 CN 2022098643 W CN2022098643 W CN 2022098643W WO 2023087684 A1 WO2023087684 A1 WO 2023087684A1
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刘磊
刘伟
袁愿林
王睿
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苏州东微半导体股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the present application belongs to the technical field of semiconductor power devices, for example, it relates to a semiconductor superjunction power device.
  • Semiconductor super-junction power devices are based on charge balance technology, which can reduce on-resistance and parasitic capacitance, so that semiconductor super-junction power devices have extremely fast switching characteristics, which can reduce switching losses and achieve higher power conversion efficiency.
  • Miller capacitance (Crss) and its corresponding gate-drain capacitance (Cgd) play an important role in the switching process of semiconductor super-junction power devices.
  • the gate-to-drain capacitance (Cgd) changes abruptly, which makes the electrical performance of the semiconductor super-junction power devices also change suddenly.
  • the present application provides a semiconductor super-junction power device capable of adjusting the variation curve of the gate-drain capacitance, so as to avoid sudden changes in the gate-drain capacitance of semiconductor super-junction power devices in the related art.
  • an n-type drift region located above the n-type drain region
  • a first p-type body region is provided on the top of each p-type column, and the widths of the plurality of first p-type body regions are the same, and a first n-type source region is provided in the first p-type body region;
  • Two gate trenches between two adjacent first p-type body regions, a gate dielectric layer and a gate are arranged in the gate trenches;
  • the gate trenches have at least two different widths, so that the distance between two gate trenches between two adjacent first p-type body regions has at least two different distance values.
  • Fig. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor superjunction power device provided by the present application
  • FIG. 2 is a schematic cross-sectional structure diagram of another embodiment of the semiconductor superjunction power device provided by the present application.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor super-junction power device provided by the present application.
  • a semiconductor super-junction power device provided by an embodiment of the present application includes an n-type drain region 20, The n-type drain region 20 may be externally connected to the drain voltage through a metal layer.
  • the p-type columns 23 and the adjacent n-type drift region 21 form a charge-balanced pn junction
  • FIG. 1 For the convenience of display and description, only three p-type pillars 23 are shown in FIG. 1 .
  • a first p-type body region 24 is disposed on the top of each p-type column 23 , and the first p-type body regions 24 have the same width, and a first n-type source region 25 is disposed in the first p-type body region 24 .
  • the spacing between two gate trenches between two adjacent first p-type body regions 24 has two different spacing values c1 and c2, and the difference between c1 and c2 is equal to b1 and b2 difference.
  • a gate dielectric layer 26 and a gate 27 are disposed in the gate trench 22 , and the gate 27 usually controls the opening and closing of the first current channel of the first p-type body region 24 by externally connecting a gate voltage.
  • the gate-drain capacitance will suddenly drop at this voltage point, by having at least two different values of the width of the region, the region with a small width value will be depleted first, and the gate-drain capacitance will suddenly drop at this source-drain voltage point; then, with With the further increase of the source-drain voltage, the regions with large width values will be depleted sequentially, and the gate-drain capacitance will suddenly decrease at these source-drain voltage points in sequence.
  • the sudden change point of the gate-drain capacitance of the product is divided into several different source-drain voltage points, which reduces the speed of the sudden change of the gate-drain capacitance of the product, and also reduces the gate voltage oscillation caused by the sudden change of the gate-drain capacitance.
  • the semiconductor super-junction power device of the present application adopts a double-groove gate structure between adjacent first p-type body regions, and the gate-drain can be adjusted by adjusting the width of the gate trench and the distance between adjacent gate trenches.
  • the variation curve of the capacitance can reduce the gate voltage oscillation.
  • Fig. 2 is a schematic cross-sectional structure diagram of the second embodiment of the semiconductor super-junction power device provided by the present application.
  • the semiconductor super-junction power device of the present application shown in Fig. 2 also includes a second The p-type body region 44, the second p-type body region 44 is arranged between the two gate trenches between two adjacent first p-type body regions 24 and is located above the n-type drift region 21, at this time, the second p-type body region 44
  • the p-type body region 44 width has at least two different width values.
  • a second n-type source region 45 is disposed in the second p-type body region 44, and at this time, the gate 27 can simultaneously control the opening and closing of the second current channel in the second p-type body region 44 through a gate voltage. At this time, the number of current channels in the semiconductor super-junction power device is increased, which can reduce the on-resistance of the semiconductor super-junction power device.
  • the semiconductor superjunction power device of the present application can also make the thickness of the gate dielectric layer 26 at the bottom of the gate trench 22 greater than the thickness of the gate dielectric layer 26 at the sidewall of the gate trench 22, which can reduce the value of the gate-to-drain capacitance, To further reduce the degree of sudden change in the gate-to-drain capacitance, this structure is not specifically shown in the embodiments of the present application.
  • the semiconductor super-junction power device of the embodiment of the present application adopts a double-trench gate structure between adjacent first p-type body regions, and adjusts the width of the gate trench and the distance between adjacent gate trenches. At the same time, the on-resistance of semiconductor super-junction power devices can be reduced by increasing the number of current channels.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本申请实施例提供的一种半导体超结功率器件，包括：n型漏区；位于所述n型漏区之上的n型漂移区；多个宽度相同的p型柱，相邻的两个所述p型柱之间的间距相同；每个p型柱顶部设有第一p型体区，多个第一p型体区的宽度相同，所述第一p型体区内设有第一n型源区；介于相邻两个所述第一p型体区之间的两个栅沟槽，所述栅沟槽内设有栅介质层和栅极；所述栅沟槽具有至少两种不同的宽度，使得相邻两个所述第一p型体区之间的两个所述栅沟槽之间的间距具有至少两种不同的间距值。

Description

半导体超结功率器件
本申请要求在2021年11月17日提交中国专利局、申请号为202111359722.2的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于半导体功率器件技术领域，例如涉及一种半导体超结功率器件。
背景技术
半导体超结功率器件是基于电荷平衡技术，可以降低导通电阻和寄生电容，使得半导体超结功率器件具有极快的开关特性，可以降低开关损耗，实现更高的功率转换效率。半导体超结功率器件在开启和关断过程中，米勒电容(Crss)及其所对应的栅漏电容(Cgd)对半导体超结功率器件的开关过程起到重要的作用。公知的半导体超结功率器件在开启和关断时，栅漏电容(Cgd)会发生突变，这使得半导体超结功率器件的电学性能也发生突变。
发明内容
有鉴于此，本申请提供一种可以调节栅漏电容的变化曲线的半导体超结功率器件，以避免相关技术中的半导体超结功率器件的栅漏电容突变情况。
本申请实施例提供的一种半导体超结功率器件，包括：
n型漏区；
位于所述n型漏区之上的n型漂移区；
多个宽度相同的p型柱，相邻的两个所述p型柱之间的间距相同；
每个p型柱顶部设有第一p型体区，多个第一p型体区的宽度相同，所述第一p型体区内设有第一n型源区；
介于相邻两个所述第一p型体区之间的两个栅沟槽，所述栅沟槽内设有栅介质层和栅极；
所述栅沟槽具有至少两种不同的宽度，使得相邻两个所述第一p型体区之间的两个所述栅沟槽之间的间距具有至少两种不同的间距值。
附图说明
下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本申请提供的半导体超结功率器件的一个实施例的剖面结构示意图；
图2是本申请提供的半导体超结功率器件的另一个实施例的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列图形大小并不代表实际尺寸，说明书附图是示意性的，不应限定本申请的范围。
图1是本申请提供的半导体超结功率器件的第一个实施例的剖面结构示意图，如图1所示，本申请实施例提供的一种半导体超结功率器件，包括n型漏区20，n型漏区20可以通过金属层外接漏极电压。位于n型漏区20之上的n型漂移区21。
多个p型柱23，p型柱23的宽度相同，且相邻的两个p型柱23之间的间距相同，p型柱23与相邻的n型漂移区21形成电荷平衡的pn结结构，为了方便展示和说明，图1中仅示例性的示出了三个p型柱23。
在每个p型柱23的顶部设有第一p型体区24，第一p型体区24的宽度均相同，第一p型体区24内设有第一n型源区25。
介于相邻两个第一p型体区24之间的两个栅沟槽，所述栅沟槽具有至少两种不同的宽度，示例性的，图1中示出了3个栅沟槽22和1个栅沟槽22a，3个栅沟槽22的栅宽度设定为b2，栅沟槽22a的宽度设定为b1(b1≠b2)，由于p型柱23的宽度相同且相邻的p型柱23之间的间距相同，同时第一p型体区24的宽度均相同，这使得相邻两个第一p型体区24之间的两个栅沟槽之间的间距具有至少两种不同的间距值。在图1中，相邻两个第一p型体区24之间的两个栅沟槽之间的间距具有c1和c2两种不同的间距值，c1和c2的差值为b1和b2的差值。
在栅沟槽22内设有栅介质层26和栅极27，栅极27通常通过外接栅极电压来控制第一p型体区24的第一电流沟道的开启和关断。
本申请的半导体超结功率器件在开启和关断时，当源漏电压使得相邻两个第一p型体区之间的两个栅沟槽之间的区域被全部耗尽时，栅漏电容会在这个电压点突然下降，通过将该区域的宽度具有至少两种不同的值，宽度值小的区域会被先耗尽，栅漏电容会在这个源漏电压点突然下降；然后，随着源漏电压 的进一步上升，宽度值大的区域会被依次耗尽，栅漏电容会在这些源漏电压点依次突然下降。从而，产品的栅漏电容的突变点被分到几个不同的源漏电压点上，这使得产品的栅漏电容突变速度降低，也就降低了由栅漏电容突变引起的栅极电压震荡。
本申请的半导体超结功率器件在相邻的第一p型体区之间采用双沟槽栅极结构，通过调节栅沟槽的宽度和相邻的栅沟槽之间的间距来调节栅漏电容的变化曲线，可以降低栅极电压震荡。
图2是本申请提供的半导体超结功率器件的第二个实施例的剖面结构示意图，与图1所示实施例相比较，图2所示的本申请的半导体超结功率器件还包括第二p型体区44，第二p型体区44设于相邻两个第一p型体区24之间的两个栅沟槽之间且位于n型漂移区21上方，此时，第二p型体区44宽度具有至少两种不同的宽度值。与图1相对应的，图2中的第二p型体区44的宽度设有c1和c2(c1≠c2)两种不同的宽度值。第二p型体区44内设有第二n型源区45，此时栅极27还可以通过栅极电压来同时控制第二p型体区44内的第二电流沟道的开启和关断，此时，增加了半导体超结功率器件中的电流沟道数量，这可以降低半导体超结功率器件的导通电阻。
本申请的半导体超结功率器件，还可以使得栅沟槽22底部处的栅介质层26的厚度大于栅沟槽22侧壁处的栅介质层26的厚度，这可以降低栅漏电容的值，进一步降低栅漏电容突变的程度，该结构在本申请实施例中不再具体展示。
本申请实施例的半导体超结功率器件在相邻的第一p型体区之间采用双沟槽栅极结构，通过调节栅沟槽的宽度和相邻的栅沟槽之间的间距来调节栅漏电容的变化曲线，同时，还可以通过增加电流沟道数量来降低半导体超结功率器件的导通电阻。

Claims (3)

  1. 一种半导体超结功率器件，包括：
    n型漏区；
    位于所述n型漏区之上的n型漂移区；
    多个宽度相同的p型柱，相邻的两个所述p型柱之间的间距相同；
    每个p型柱顶部设有第一p型体区，多个第一p型体区的宽度相同，所述第一p型体区内设有第一n型源区；
    介于相邻两个所述第一p型体区之间的两个栅沟槽，所述栅沟槽内设有栅介质层和栅极；
    所述栅沟槽具有至少两种不同的宽度，使得相邻两个所述第一p型体区之间的两个所述栅沟槽之间的间距具有至少两种不同的间距值。
  2. 如权利要求1所述的半导体超结功率器件，还包括介于相邻两个所述第一p型体区之间的两个所述栅沟槽之间的第二p型体区，所述第二p型体区内设有第二n型源区，所述第二p型体区的宽度具有至少两种不同的宽度值。
  3. 如权利要求1所述的半导体超结功率器件，其中，所述栅沟槽底部处的栅介质层的厚度大于所述栅沟槽侧壁处的栅介质层的厚度。
PCT/CN2022/098643 2021-11-17 2022-06-14 半导体超结功率器件 WO2023087684A1 (zh)

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CN205488137U (zh) * 2016-03-30 2016-08-17 无锡同方微电子有限公司 栅槽交错变化的沟槽栅超结mosfet器件
CN106229343A (zh) * 2016-08-12 2016-12-14 上海鼎阳通半导体科技有限公司 超结器件
CN107464837A (zh) * 2017-08-07 2017-12-12 电子科技大学 一种超结功率器件
CN109166926A (zh) * 2018-08-29 2019-01-08 电子科技大学 一种屏蔽栅功率器件
CN112447822A (zh) * 2019-09-03 2021-03-05 苏州东微半导体股份有限公司 一种半导体功率器件

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