WO2016123968A1 - 移位寄存器单元、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2016123968A1
WO2016123968A1 PCT/CN2015/088646 CN2015088646W WO2016123968A1 WO 2016123968 A1 WO2016123968 A1 WO 2016123968A1 CN 2015088646 W CN2015088646 W CN 2015088646W WO 2016123968 A1 WO2016123968 A1 WO 2016123968A1
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Prior art keywords
transistor
shift register
register unit
node
clock signal
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PCT/CN2015/088646
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English (en)
French (fr)
Inventor
胡理科
祁小敬
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US15/122,265 priority Critical patent/US10417983B2/en
Publication of WO2016123968A1 publication Critical patent/WO2016123968A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the driving circuit of the display device mainly includes a gate driving circuit (scanning driving circuit) and a data driving circuit (or source driving circuit), wherein the gate driving circuit includes a cascaded shift register unit, and the input clock signal CLK is shifted
  • the conversion of the register unit is sequentially applied to the gate line of each pixel row of the display device to control the display of the display device line by line.
  • a circuit of a conventional shift register unit includes four transistors and a capacitor, that is, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a capacitor C.
  • the gate of the first transistor M1 is connected to the source and is connected to the first input terminal 1.
  • the first input terminal 1 receives an input signal INPUT, and the input signal INPUT is derived from an output signal OUTPUT of the shift register unit of the previous stage.
  • the gate of the second transistor M2 is connected to the second input terminal 2 and receives a reset signal RESET.
  • the drain of the second transistor M2 is connected to a constant low level terminal 5 for receiving the low level signal VGL.
  • the source of the third transistor M3 is connected to the clock terminal 6, and the clock terminal 6 is for receiving the clock signal CLK.
  • the gate of the third transistor M3 is connected to the output terminal 8 via a capacitor C.
  • the gate of the fourth transistor M4 is connected to the second input terminal 2, the drain is connected to the constant low level terminal VGL, and the source is connected to the output terminal 8.
  • the node between the drain of the first transistor M1 and the source of the second transistor M2 is a pull-up node PU.
  • the output signal OUTPUT outputted by the output terminal 8 is the gate scan signal of the shift register unit of this stage.
  • the input signal INPUT of the shift register unit of the current stage is at a high level, and the first transistor M1 is turned on to precharge the pull-up node PU.
  • the clock signal CLK of the shift register unit of the current stage is at a high level, and the third transistor M3 is turned on so that the output terminal 8 is at a high level, that is, the output signal OUTPUT is at a high level.
  • the pull-up The potential of the point PU is raised again.
  • the output signal outputted by the shift register unit of the next stage is at a high level, that is, the reset signal RESET of the second input terminal 2 is at a high level, and the second transistor M2 and the fourth transistor M4 are turned on, and the pull-up node is connected.
  • the PU and the output terminal 8 are discharged to be reset.
  • the technical problem to be solved by the present invention is to realize the bidirectional scanning function of the gate driving circuit of the display device and to reduce the circuit size.
  • an embodiment of the present invention provides a shift register unit, including:
  • the input module provides the first input signal to the first node according to the first clock signal
  • a first control module coupled to the input module, to the first node, and providing the third clock signal to an output node of the shift register unit according to the first input signal and the third clock signal Implementing a pull-up output, and then implementing a pull-down output by providing a supply voltage to the output node according to a second input signal, wherein the second input signal is provided by the input module to the First node;
  • the second control module maintains the level of the output node at the power supply voltage according to the fourth clock signal
  • the first control module includes a first transistor, the first transistor continues to be turned on for pull-down output after the pull-up output, and the second control module includes a second transistor for maintaining the output node Level.
  • a gate driving circuit comprising the shift register unit described above.
  • N shift register units according to an embodiment of the present invention are cascaded, and N is large The natural number of 1 in which
  • each shift register unit is coupled to the output node of the shift register unit of the first stage, and the first input of the first stage shift register unit is first turned on. Signal connected
  • each shift register unit is coupled to the output node of the next stage shift register unit, and the second input of the last stage shift register unit is enabled. Signal connected
  • the shift register unit When the shift register unit performs a forward shift, a high level pulse of the first clock signal precedes the third clock signal, and a waveform of the first clock signal and a shift register of a previous stage The voltage waveform of the output node of the unit is the same;
  • a display device comprising a gate driving circuit according to an embodiment of the present invention.
  • the shift register unit of the present invention realizes bidirectional scanning by a simple design, so that the structure of the gate driving circuit is simplified, which is advantageous in reducing cost.
  • only the timing of the control signal and the input signal can be matched to switch between forward scan and reverse scan, which reduces the control signal of the circuit (most of the other existing shift registers require additional two directional control signals). ), which facilitates narrow borders and high-resolution display panel wiring.
  • 1 is a circuit diagram of a conventional shift register unit
  • FIG. 2 is a circuit configuration diagram of a shift register unit of a first embodiment of the present invention
  • FIG. 3 is a timing chart showing signals of a shift register unit of the first embodiment of the present invention.
  • FIG. 4 shows a cascade diagram of a gate driving circuit of a first embodiment of the present invention
  • Figure 6 is a timing chart showing signals when the embodiment of Figure 4 is reverse scanned
  • Figure 9 is a circuit configuration diagram of a shift register unit of a third embodiment of the present invention.
  • Figure 10 is a circuit configuration diagram of a shift register unit of a fourth embodiment of the present invention.
  • the shifting of the signal can be achieved by cascading the shift register units.
  • the shift register unit receives the output of the shift register unit of the previous stage as a shift trigger signal of the shift register unit of the stage to output a signal such as a high level in the next period (a period of one half clock period) ).
  • the shift register unit can also receive the output of the shift register unit of the next stage as a reset signal of the shift register unit of the stage to resume outputting the low level signal in the next period and subsequent periods.
  • the output of the shift register unit of the embodiment of the invention is still provided with a drive level by the clock signal. That is, the clock signal received on the first clock terminal is at a high level in the next period of the period in which the upper stage (forward) or the next stage (reverse) shift register unit outputs a high level (the The "upper level” and “lower level” refer to the “upper level” and “lower level” of the spatially cascading order of the plurality of shift register units when cascading. Since the shift operation period (i.e., one period) of the shift register unit is half a clock cycle, the timing of the clock signal accessed by the first clock terminal of the shift register unit of the adjacent stage should be reversed.
  • the first embodiment is a basic implementation circuit of the shift register unit of the present invention, and a basic cascode circuit from which the gate drive circuit is constructed.
  • Fig. 2 is a circuit diagram showing a shift register unit of the first embodiment.
  • the switching transistors are all "N" type transistors will be described as an example. It is of course possible to implement embodiments of the invention using "P" type transistors.
  • the shift register unit may include:
  • An input module according to the first clock signal (one of ck4 and ck2), providing the input signal OUT_N-1 to the first node PU (pull-up node);
  • a first control module according to the input signal OUT_N-1 and the third clock signal ck1, implementing a pull-up output by providing the third clock signal to an output node OUT_N of the shift register unit, and then according to the input A signal OUT_N+1 is implemented by providing a supply voltage (VGL) to the output node, wherein the input signal OUT_N+1 is used by the input module according to a second clock signal (the other of ck4 and ck2) Provided to the first node PU;
  • the second control module maintains the level of the output node at the power supply voltage (VGL) according to the fourth clock signal ck3;
  • the first control module includes a first transistor T1, the first transistor T1 continues to be turned on for pull-down output after the pull-up output, and the second control module includes a second transistor T2 for maintaining the The level of the output node.
  • the input module may include: a third transistor T3 having a gate connected to the clock signal ck4, a source connected to the input signal OUT_N-1, and a drain connected to the first node PU;
  • the transistor T4, the gate of the fourth transistor T4 is connected to the clock signal ck2, the drain is connected to the input signal OUT_N+1, and the source is connected to the first (pull-up) node PU.
  • the input signal OUT_N-1 is the output signal of the previous stage of the current stage output signal OUT_N of the shift register unit, and its initial value is STV, for example, the signal SIU in the case of forward shift and the signal SID in the case of reverse shift. .
  • the input signal OUT_N+1 is the next-stage output signal of the shift register unit current stage output signal OUT_N.
  • the first control module may include: a first transistor T1, the gate of the first transistor T1 is connected to the first node PU, the source is connected to the clock signal ck1, and the drain is connected to the output node OUT_N of the shift register unit; the seventh transistor T7, the gate of the seventh transistor T7 is connected to the first node PU, and one end of the source and the second capacitor C2 is connected at the second node PD (pull-down node), and the drain and the power supply voltage (VGL Connected, the other end of the second capacitor C2 is connected to the power supply voltage (VGL), and the second capacitor C2 is used as a voltage holding capacitor of the second node PD.
  • first capacitor C1 and the second capacitor C2 may be inherent parasitic capacitances between transistors, or may be additional additional capacitors.
  • the second control module may include: a second transistor T2 having a gate connected to the pull-down node PD, a drain connected to the power supply negative voltage VGL, a source connected to the output node OUT_N, and a fifth transistor T5 a gate and a drain of the fifth transistor T5 are connected to the clock signal ck3, a source is connected to the pull-down node PD, and a gate of the sixth transistor T6, the sixth transistor T6 is connected to the second node (PD), the source The pole is connected to the first node (PU) and the drain is connected to the supply voltage (VGL).
  • the shift register unit of this embodiment is controlled by four clock signals ck1-ck4.
  • the two-way scanning function can be realized by the third transistor T3 and the fourth transistor T4.
  • the conduction of the first transistor T1 can pull down the output point voltage after the output point voltage is pulled up
  • the second transistor T2 is a pull-down holding transistor
  • the fifth transistor T5 controls the voltage of the pull-down node PD to realize the pulling of the pull-down node PD.
  • the sixth transistor T6 controls the voltage of the pull-up node PU. When the PD is high, the PU point is continuously pulled down, the first transistor T1 is turned off, and the seventh transistor T7 is the control transistor of the pull-down node PD.
  • the first transistor T1 continues to conduct after the pull-up output, and acts as a pull-down, so that the second transistor T2 is only used to keep the output of the shift register unit low.
  • the voltage is such that the output of the shift register unit is controlled only by the first transistor T1. Therefore, the size of the second transistor T2 can be appropriately reduced to facilitate narrow-frame wiring.
  • the size ratio of the first transistor T1 and the second transistor T2 is about 30:1 to 1:1, preferably 6:1 to 3:1.
  • Fig. 3 shows the signal timing when the shift register unit of the present embodiment performs forward shift. Next, the operation principle of the shift register unit of this embodiment will be described with reference to Figs. 2 and 3.
  • ck4 is synchronized with the pulse of the SIU, SIU and ck4 are at a high level, and the remaining clock signals are at a low level.
  • the third transistor T3 controlled by ck4 is turned on, and the high level signal of the SIU is transmitted to the gate of the first transistor T1, the first transistor T1 is turned on and charges the first capacitor C1.
  • the signal also turns on the seventh transistor T7.
  • the second phase (t2): ck1 is high, the remaining clock signals are low, and the SIU signal goes low.
  • the voltage Out1 of the output node OUT_N transitions from a low level to a high level.
  • the bootstrap effect of the first capacitor C1 pumps the voltage at the PU point high, at which point the first transistor T1 can fully output the high level of ck1 to the output node OUT_N.
  • the seventh transistor T7 since the seventh transistor T7 is turned on, the voltage of the pull-down node PD is pulled low.
  • the third stage (t3): ck2 is high, the remaining clock signals are low voltage, and the SIU signal is kept low.
  • Ck2 is at a high level, and the fourth transistor T4 is turned on. Since the fourth transistor T4 is turned on, the voltage of the pull-up node PU is no longer bootstrapped, but the conduction of the first transistor T1 can still be maintained, and the voltage Out1 of the output node OUT_N transitions from a high level to a low level. Therefore, during the high level of the clock signals ck4, ck1, and ck2, the first transistor T1 is turned on, the voltage point of the pull-down node PD is both low level, and the second transistor T2 is turned off.
  • the fourth stage (t4): ck3 is high, the remaining clock signals are low voltage, and the SIU signal is kept low.
  • Ck3 is at a high level, and the fifth transistor T5 is turned on, thereby pulling the level of the pull-down node PD high while charging the second capacitor C2, and the second transistor T2 is turned on to maintain the low level of the output node.
  • the sixth transistor T6 pulls down the voltage of the pull-up node PU, thereby causing the first transistor T1 to be in an off state.
  • the fifth stage (t5): ck4 is high, the remaining clock signals are low voltage, and the SIU signal goes high.
  • the third transistor T3 controlled by ck4 is turned on, repeating the above steps of the first stage, thereby starting the operation of the next period of the shift register unit.
  • Fig. 4 shows a cascade diagram of the gate driving circuit of the first embodiment.
  • the shift register unit of this embodiment constitutes a gate drive circuit in a cascade manner, whereby progressive scanning of each pixel row is realized by shifting of the shift register unit.
  • the SIU and SID are the input start pulse signals for the forward and reverse scans, respectively.
  • the first input terminal OUT_N-1 of each shift register unit SRn is connected to the upper stage shift register unit SRn-1.
  • the output, the first input terminal OUT_N-1 of the first stage shift register unit SR1 is connected to the enable signal SIU; the second input of each shift register unit SRn except the last stage shift register unit SRN OUT_N+1 is connected to the output of the next stage shift register unit SRn+1, and the second input terminal OUT_N+1 of the last stage shift register unit SRN is connected to the enable signal SID.
  • the output signal timing of the shift register unit of the subsequent stage is delayed by one cycle from the output signal timing of the shift register unit of the previous stage.
  • the clock signals of the shift register units of the adjacent four shift register units satisfy the following relationship:
  • the clock signals input to the clock signal input terminals CK1, CK2, CK3, and CK4 are ck1, ck2, ck3, and ck4, respectively;
  • the clock signals input to the clock signal input terminals CK1, CK2, CK3, and CK4 are ck2, ck3, ck4, and ck1, respectively;
  • the clock signals input to the clock signal input terminals CK1, CK2, CK3, and CK4 are ck3, ck4, ck1, and ck2, respectively;
  • the clock signals input to the clock signal input terminals CK1, CK2, CK3, and CK4 are ck4, ck1, ck2, and ck3, respectively.
  • the input of the clock signal is the same as the i-th shift register, that is, the clock signals input by the clock signal input terminals CK1, CK2, CK3, and CK4. They are ck1, ck2, ck3, and ck4, and so on.
  • i is an integer greater than or equal to 1, and i+3 ⁇ n.
  • the input terminal OUT_N-1 receives the output signal OUTi-1 or the turn-on signal SIU from the shift register unit SRn-1 of the upper stage as an enable signal to control The operation of the shift register.
  • the input terminal OUT_N+1 receives the output signal OUTi+1 or the turn-on signal SID from the next-stage shift register unit SRn+1 as the enable signal.
  • cascaded shift registers can be designed as needed, and can be any level greater than or equal to 2 as long as the clock signals are rotated in the above order.
  • the shift register cascade structure of the embodiment only the timings of the control signal and the input signal need to be matched to switch between the forward scan and the reverse scan, and the control signal of the circuit is reduced (other existing shift registers are mostly Two additional directional control signals are required) to facilitate narrow border and high resolution display panel wiring.
  • Fig. 5 and Fig. 6 respectively show signal timing charts of the first embodiment at the time of forward shift and reverse shift.
  • the signal timing diagram shown in FIG. 5 when the gate driver is forward shifted to forward scan a pixel row is described in conjunction with FIGS. 1 and 4.
  • the shift register unit is sequentially referred to as a first-stage shift register unit, a second-stage shift register unit, a third-stage shift register unit, and the fourth stage in order from top to bottom in FIG. a shift register unit and a fifth shift register unit respectively corresponding to the above The i-th i+4th shift register unit.
  • the turn-on signal SIU connected to the input terminal OUT_N-1 of the first-stage shift register unit SR1 and the clock signal ck4 connected to the input terminal CK4 are at a high level, other clock signals and signals connected to the input terminal OUT_N+1 To be low, this period is referred to herein as the first period (1 in Fig. 5).
  • the third transistor T3 is turned on, and the high level signal of the SIU is transmitted to the gate of the first transistor T1, and the first transistor T1 is turned on, and charges the first capacitor C1.
  • the seventh transistor T7 is turned on.
  • the voltage of the pull-up node PU is pulled high, and the voltage of the pull-down node PD is slowly pulled down by the PU voltage, and both ends of the second capacitor C2 are at a low level.
  • the clock signal ck1 connected to the input terminal CK1 is at a low level, and the voltage Out1 of the output node is at a low level. This period can also be referred to as the current pre-charging period.
  • the clock signal ck1 connected to the input terminal CK1 becomes a high level
  • the turn-on signal SIU becomes a low level
  • the third transistor T3 is turned off
  • the pull-up node PU continues to remain high.
  • the clock signal ck1 connected to the input terminal CK1 becomes a high level
  • the voltage of the output node transitions from a low level to a high level, that is, OUT1 in FIG. 4 outputs a high level.
  • the bootstrap effect of the first capacitor C1 pumps the voltage at the PU point high, at which point the first transistor T1 can fully output the high level of the clock signal ck1 to the output node.
  • the clock signal ck2 is at a high level, the remaining clock signals are at a low level, and the fourth transistor T4 is turned on. Since the fourth transistor T4 is turned on, the voltage of the pull-up node PU is no longer bootstrapped, but the conduction of the first transistor T1 can be maintained, and the voltage of the output node changes from a high level to a low level.
  • This period can be referred to as the local reset period.
  • OUT1 input to the input terminal OUT_N-1 of the second-stage shift register unit SR2 is at a low level, and a clock signal ck2 connected to the second-stage input terminal CK1 is at a high level.
  • the second-stage shift register unit SR2 the same operation as that of the first-stage shift register unit SR1 in the second period is performed, and OUT2 is a high level, which is the second-stage scanning period.
  • the high level OUT2 is input to the input terminal OUT_N-1 of the third stage shift register unit SR3, and the clock signal ck2 connected to the input terminal CK4 of the third stage shift register unit SR3 is at the high level. Therefore, for the third stage shift register unit SR3, the first stage shift register unit SR1 is executed in the first period. The same operation.
  • the high level OUT3 is input to the input terminal OUT_N-1 of the fourth stage shift register unit SR4, and the high level clock signal ck3 is connected to the input terminal CK4 of the fourth stage shift register unit SR4. Therefore, for the fourth-stage shift register unit SR4, the same operation as in the first-stage shift register unit SR1 in the first period is performed.
  • the access positions of the clock signal ck4 and the clock signal ck2 can be exchanged without changing the input terminal OUT_N-1 and the input terminal OUT_N+. 1 connection relationship.
  • the first transistor T1 and the second transistor T2 can precharge the pull-up node PU in a period before the shift register unit performs the line scan, and in the shift register. The cell is discharged to the pull-up node PU at a time period after the cell performs the scan of the line.
  • the input terminal OUT_N-1 receives a valid start signal in a period before the current shift register unit performs the scan of the line to control
  • the shift register unit of this stage outputs a signal of a high level signal during the current period, and the shift register unit outputs a low level signal after the line scan.
  • the timing chart in the reverse scan is shown in FIG. 6 and will not be described here.
  • the SIU and SID can be the same signal, and only the timing matching of the corresponding clock control signal needs to be adjusted. It should be noted that when the SIU and the SID are the same signal, if the forward and reverse scans are required to work normally, the clock signals of the first and last stages of the shift register unit circuit must be different, so that the first The phenomenon of the start pulse is input simultaneously in the first stage and the last stage circuit.
  • the first embodiment employs a simple circuit that uses only seven transistors and two capacitors to achieve bidirectional shifting. At the same time, when the shift register unit of this stage performs scanning, the pull-up node PU maintains a high voltage due to the bootstrap effect, thereby ensuring the stability of the output.
  • the second embodiment is an improvement made on the basis of the first embodiment.
  • the cascade manner of the gate driving circuit of this embodiment is the same as that of the first embodiment except for the structure of each shift register unit.
  • 7 and 8 show the circuit configuration of the shift register unit of the second embodiment.
  • the first embodiment employs a diode connection.
  • the drain of the fifth transistor T5 in the second embodiment is connected to the high level VGH.
  • the pull-down module of the shift register unit of the second embodiment further includes an eighth transistor T8 and a ninth transistor T9.
  • the drain of the eighth transistor T8 is connected to the gate and connected to the clock signal ck2, the source and the pull-down The node PD is connected, the gate of the ninth transistor T9 is connected to the clock signal ck4, the source is connected to the pull-down node PD, and the drain is connected to the power supply positive voltage VGH.
  • the input signals of the third transistor T3 and the fourth transistor T4 are interchanged, and the circuit function is unchanged.
  • clock signals ck4 and ck2 are respectively input to the gates of the third transistor and the fourth transistor, whereby the PU can be continuously pulled down after the normal output without leakage. If OUT_N-1 and OUT_N+1 are input to the gate and ck2 and ck4 are respectively connected to the source or the drain, there is a risk that the potential of the PU point is pulled high by the leakage of T3 and T4.
  • the present invention also provides an image display device including the above-described gate driver.
  • the display device may be a liquid crystal display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, an electronic reader, a liquid crystal display, or the like.

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Abstract

公开了一种移位寄存器单元、一种双向扫描栅极驱动电路以及一种显示装置。该移位寄存器单元包括输入模块，将输入信号（OUT_N-1）提供至第一节点（PU）；第一控制模块，根据输入信号（OUT_N-1）和第三时钟信号（ck1）实现上拉输出，并随后实现下拉输出；第二控制模块，根据第四时钟信号（ck3），将输出节点（OUT_N）的电平保持在电源电压；第一控制模块包括第一晶体管（T1），在上拉输出后继续导通以进行下拉输出，第二控制模块包括第二晶体管（T2），用于保持输出节点（OUT_N）的电平。该移位寄存器单元通过简单的设计实现了双向扫描，利于窄边框和高分辨率的显示面板布线。此外，由于第二晶体管（T2）仅用于下拉保持，可以使用较小尺寸的晶体管，从而进一步缩小了电路尺寸。

Description

移位寄存器单元、栅极驱动电路及显示装置 技术领域
本发明涉及一种电路驱动技术，具体地，涉及一种移位寄存器单元，以及使用移位寄存器单元的栅极驱动电路(栅极驱动IC)及显示装置。
背景技术
显示装置的驱动电路主要包括栅极驱动电路(扫描驱动电路)和数据驱动电路(或源驱动电路)，其中，栅极驱动电路包括级联的移位寄存器单元，输入的时钟信号CLK通过移位寄存器单元的转换后会依次加在显示装置的每一像素行的栅线上，以逐行控制显示装置的显示。
如图1所示，一种传统的移位寄存器单元的电路包括四个晶体管和一个电容，即第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、电容C。
第一晶体管M1的栅极和源极相连，并连接至第一输入端1。该第一输入端1接收输入信号INPUT，输入信号INPUT来自于上一级移位寄存器单元的输出信号OUTPUT。
第二晶体管M2的栅极连接第二输入端2，接收复位信号RESET。第二晶体管M2的漏极与一个恒低电平端5连接，用于接收低电平信号VGL。
第三晶体管M3的源极与时钟端6连接，时钟端6用于接收时钟信号CLK。第三晶体管M3的栅极经由电容C与输出端8连接。
第四晶体管M4的栅极连接到第二输入端2，漏极连接到恒低电平端VGL，源极则连接到输出端8。
第一晶体管M1的漏极与第二晶体管M2的源极之间的节点为上拉节点PU。输出端8输出的输出信号OUTPUT即为本级移位寄存器单元的栅极扫描信号。
当上一级移位寄存器单元进行栅极扫描时，本级移位寄存器单元的输入信号INPUT为高电平，第一晶体管M1导通以对上拉节点PU预充电。在下一个时段，本级移位寄存器单元的时钟信号CLK为高电平，第三晶体管M3导通使得输出端8为高电平，即输出信号OUTPUT为高电平。同时，由于自举效应，上拉节 点PU的电位被再次升高。在下一个时段，下一级移位寄存器单元输出的输出信号为高电平，即第二输入端2复位信号RESET为高电平，第二晶体管M2和第四晶体管M4导通，对上拉节点PU和输出端8进行放电从而复位。
这种移位寄存器单元的不足之处在于，向第四晶体管M4施加高电平的时间很短，并不会在直流偏压下产生漂移，大部分时间内PU和OUTPUT是悬空状态，容易受寄生电容等影响，产生误操作。这将导致显示器件的亮度不均，影响产品的质量。同时，这种移位寄存器单元不能实现双向扫描，且电路尺寸较大。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是实现显示装置的栅极驱动电路的双向扫描功能，并减小电路尺寸。
(二)技术方案
根据本发明的一方面，本发明实施例提供了一种移位寄存器单元，包括：
输入模块，根据第一时钟信号，将第一输入信号提供至第一节点；
第一控制模块，与所述输入模块连接于所述第一节点，根据所述第一输入信号和第三时钟信号，通过将所述第三时钟信号提供至所述移位寄存器单元的输出节点来实现上拉输出，并随后根据第二输入信号，通过将电源电压提供至所述输出节点来实现下拉输出，其中所述第二输入信号由所述输入模块根据第二时钟信号提供至所述第一节点；
第二控制模块，根据第四时钟信号，将所述输出节点的电平保持在所述电源电压；
其中，所述第一控制模块包括第一晶体管，所述第一晶体管在上拉输出后继续导通以进行下拉输出，所述第二控制模块包括第二晶体管，用于保持所述输出节点的电平。
根据本发明的另一方面，提供了一种栅极驱动电路，包括上述所述的移位寄存器单元。
进一步地，由N个根据本发明实施例的移位寄存器单元级联而成，N为大 于1的自然数，其中，
除了第1级移位寄存器单元之外，每个移位寄存器单元的第一输入端连接上一级移位寄存器单元的输出节点，第1级移位寄存器单元的第一输入端与第一开启信号相连；
除了最后1级移位寄存器单元之外，每个移位寄存器单元的第二输入端连接下一级移位寄存器单元的输出节点，最后1级移位寄存器单元的第二输入端与第二开启信号相连；
当所述移位寄存器单元进行正向移位时，所述第一时钟信号的高电平脉冲在所述第三时钟信号之前，并且所述第一时钟信号的波形与上一级移位寄存器单元的输出节点的电压波形相同；
当所述移位寄存器单元反向移位时，所述第二时钟信号的高电平脉冲在所述第三时钟信号之前，并且所述第二时钟信号的波形与下一级移位寄存器单元的输出节点的电压波形相同。
根据本发明的另一方面，提供了一种显示装置，包括根据本发明实施例所述的栅极驱动电路。
(三)有益效果
本发明的移位寄存器单元通过简单的设计实现了双向扫描，使得栅极驱动电路的结构简化，有利于降低成本。此外，只需要匹配控制信号和输入信号的时序便可实现正向扫描和反向扫描的切换，减少了电路的控制信号(其他现有移位寄存器中的大多数需要额外的两个方向控制信号)，利于窄边框和高分辨率的显示面板布线。
此外，由于第二晶体管仅用于下拉保持，可以使用较小尺寸的晶体管，从而进一步缩小了电路尺寸。
附图说明
图1是一种传统移位寄存器单元的电路图；
图2是本发明的第一实施例的移位寄存器单元的电路结构图；
图3示出了本发明的第一实施例的移位寄存器单元的信号时序图；
图4示出了本发明的第一实施例的栅极驱动电路级联图；
图5示出了图4中实施例正向扫描时的信号时序图；
图6示出了图4中实施例反向扫描时的信号时序图；
图7和图8是本发明的第二实施例的移位寄存器单元的电路结构图；
图9是本发明的第三实施例的移位寄存器单元的电路结构图；
图10是本发明的第四实施例的移位寄存器单元的电路结构图。
具体实施方式
通过将移位寄存器单元级联能够实现信号的移位。通常移位寄存器单元通过接收前一级移位寄存器单元的输出，作为本级移位寄存器单元的移位触发信号，以在下一时段输出一个例如高电平的信号(一个时段为半个时钟周期)。同时，移位寄存器单元也可以接收下一级移位寄存器单元的输出，作为本级移位寄存器单元的复位信号，以在下一时段及之后的时段恢复输出低电平信号。
在本发明实施例中，为了实现双向扫描，需要级联的移位寄存器单元能够以正、反两个方向进行移位。
本发明实施例的移位寄存器单元的输出仍由时钟信号提供驱动电平。即，在上一级(正向)或下一级(反向)移位寄存器单元输出高电平的时段的下一时段，该第一时钟端上接收的时钟信号为高电平(所述的“上一级”和“下一级”指的是多个移位寄存器单元在级联时，在空间上的级联顺序的“上一级”和“下一级”)。因为移位寄存器单元的移位操作周期(即一个时段)为半个时钟周期，相邻级的移位寄存器单元的第一时钟端接入的时钟信号的时序应当相反。这里所说的“时序”是指信号的高电平时段和低电平时段在时域上的分布；两个信号的“时序相反”指的是当一个信号为高电平时，另一个信号为低电平，当一个信号为低电平时，另一个信号为高电平；两个信号的“时序相同”则指的是当一个信号为高电平时，另一个信号同为高电平，当一个信号为低电平时，另一个信号同为低电平。
移位寄存器单元的实现经常需要高电平信号或低电平信号。因此针对双向扫描，需要同时提供高电平信号和低电平信号，并且在正向移位和反向移位之间切换时，将高电平信号和低电平信号的输入端也进行交换。
在本发明实施例中，为区分晶体管除栅极之外的两极，将其中一个电极称为源极，另一电极称为漏极。按附图中的形态规定晶体管的中间端为栅极、信号 输入端为源极、信号输出端为漏极。本领域技术人员可以理解，本发明实施例所采用的单极型晶体管可以是P型开关晶体管或N型开关晶体管，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
[第一实施例]
第一实施例是本发明的移位寄存器单元的一种基本实现电路，以及由其构成栅极驱动电路的基本级联电路。图2示出了第一实施例的移位寄存器单元的电路图。以下实施例以开关晶体管均为“N”型晶体管为例进行说明。当然可以使用“P”型晶体管来实现本发明实施例。
接下来参考图2来详细描述根据本发明第一实施例的移位寄存器单元的结构。如图2所示，移位寄存器单元可以包括：
输入模块，根据第一时钟信号(ck4和ck2中的一个)，将输入信号OUT_N-1提供至第一节点PU(上拉节点)；
第一控制模块，根据所述输入信号OUT_N-1和第三时钟信号ck1，通过将所述第三时钟信号提供至所述移位寄存器单元的输出节点OUT_N来实现上拉输出，并随后根据输入信号OUT_N+1，通过将电源电压(VGL)提供至所述输出节点来实现下拉输出，其中所述输入信号OUT_N+1由所述输入模块根据第二时钟信号(ck4和ck2中的另一个)提供至第一节点PU；
第二控制模块，根据第四时钟信号ck3，将所述输出节点的电平保持在所述电源电压(VGL)；
其中，所述第一控制模块包括第一晶体管T1，所述第一晶体管T1在上拉输出后继续导通以进行下拉输出，所述第二控制模块包括第二晶体管T2，用于保持所述输出节点的电平。
以下结合图2对本实施例移位寄存器的各个组成部分分别进行详细说明。
如图2所示，输入模块可以包括：第三晶体管T3，第三晶体管T3的栅极连接至时钟信号ck4，源极连接至输入信号OUT_N-1，漏极连接至第一节点PU；第四晶体管T4，第四晶体管T4的栅极连接至时钟信号ck2，漏极连接至输入信号OUT_N+1，源极连接至第一(上拉)节点PU。这里需要注意的是，在第一晶体管T1的栅极和漏极之间具有第一电容C1，作为上拉节点PU的电压保持电容。输入信号OUT_N-1是移位寄存器单元当前级输出信号OUT_N的上一级输出信号，其初始值为STV，例如在正向移位情况下为信号SIU，在反向移位情况下为信号SID。输入信号OUT_N+1是移位寄存器单元当前级输出信号OUT_N的下一级输出信号。
第一控制模块可以包括：第一晶体管T1，第一晶体管T1的栅极与第一节点PU相连，源极与时钟信号ck1相连，漏极与移位寄存器单元的输出节点OUT_N相连；第七晶体管T7，所述第七晶体管T7的栅极与所述第一节点PU相连，源极与第二电容C2的一端在第二节点PD(下拉节点)处相连，漏极与所述电源电压(VGL)相连，所述第二电容C2的另一端与所述电源电压(VGL)相连，所述第二电容C2用作第二节点PD的电压保持电容。
本领域技术人员可以理解，第一电容C1和第二电容C2可以是晶体管之间的固有寄生电容，也可以是额外的附加电容器。
第二控制模块可以包括：第二晶体管T2，第二晶体管T2的栅极连接至下拉节点PD，其漏极连接至电源负极电压VGL，其源极连接至所述输出节点OUT_N；第五晶体管T5，第五晶体管T5的栅极和漏极连接至时钟信号ck3，源极与下拉节点PD相连；以及第六晶体管T6，第六晶体管T6的栅极与所述第二节点(PD)相连，源极与第一节点(PU)相连，漏极与所述电源电压(VGL)相连。
如图2所示，本实施例的移位寄存器单元由4个时钟信号ck1-ck4控制。利用第三晶体管T3和第四晶体管T4可以实现双向扫描功能。第一晶体管T1的导通能够在实现输出点电压上拉之后下拉该输出点电压，第二晶体管T2为下拉保持晶体管，第五晶体管T5控制下拉节点PD的电压，实现对下拉节点PD的拉高，第六晶体管T6控制上拉节点PU的电压，当PD为高时持续下拉PU点，使第一晶体管T1管截止，第七晶体管T7为下拉节点PD的控制晶体管，当PU为 高时保持PD点为低，使下拉晶体管T2截止。利用上述电路结构与时钟信号的时序相结合，第一晶体管T1在上拉输出后还继续导通，起着下拉的作用，这样第二晶体管T2仅用于将移位寄存器单元的输出保持在低电压，使得移位寄存器单元的输出仅由第一晶体管T1控制。因此，可以适当缩小第二晶体管T2的尺寸，有利于窄边框布线。第一晶体管T1和第二晶体管T2的尺寸比率约为30∶1～1∶1，优选是6∶1～3∶1。
对于在长期正向偏压下工作的第二晶体管T2的可靠性而言，具有较小尺寸是非常有益的。这是因为在95％以上高占空比工作的只有第六晶体管T6和第二晶体管T2，它们都可以在最小尺寸下保持电路的正常功能，而且下拉节点PD的电压低于电路中的高电平(对于NMOS电路)，该电路的可靠性得到了提高。
本领域技术人员应当清楚，上述的晶体管尺寸是与移位寄存器连接负载的大小相关联的，因此不能直接就以某个数值作为代表。本发明中采用这种结构可以减小下拉晶体管T2的尺寸，是指在相同负载状态下，相对不采用这种结构的移位寄存器而言，可以减小下拉晶体管T2的尺寸，只是个对比结果，其不能是具体数值，特此解释。
图3示出了本实施例的移位寄存器单元进行正向移位时的信号时序。接下来将结合图2和图3来描述本实施例移位寄存器单元的工作原理。
如图3所示，在第一阶段(t1)中，ck4与SIU的脉冲同步，SIU和ck4为高电平，其余时钟信号为低电平。当输入有效的SIU(在NMOS晶体管的情况下为高电平)时，由ck4控制的第三晶体管T3导通，将SIU的高电平信号传输到第一晶体管T1的栅极，第一晶体管T1导通，并对第一电容C1充电。同时该信号还将第七晶体管T7导通。此时，上拉节点PU的电压拉高，下拉节点PD的电压则由PU电压慢慢拉低，第二电容C2两端都为低电平。此时，ck1为低电平，第一晶体管T1导通，从而对第一电容C1充电，输出节点OUT_N的电压Out1为低电平。
第二阶段(t2)：ck1为高电平，其余时钟信号为低电平，SIU信号变为低电平。输出节点OUT_N的电压Out1由低电平跳变到高电平。第一电容C1的自举效应将PU点的电压泵高，此时便可使第一晶体管T1完全输出ck1的高电平到输出节点OUT_N。这时，由于第七晶体管T7导通，下拉节点PD的电压被拉低。
第三阶段(t3)：ck2为高电平，其余时钟信号为低电压，SIU信号保持低电平。ck2为高电平，第四晶体管T4导通。由于第四晶体管T4导通，上拉节点PU的电压不再自举，但仍可以维持第一晶体管T1的导通，输出节点OUT_N的电压Out1由高电平跳变到低电平。因此，在时钟信号ck4、ck1和ck2的高电平期间，第一晶体管T1均导通，下拉节点PD的电压点均为低电平且第二晶体管T2均截止。
第四阶段(t4)：ck3为高电平，其余时钟信号为低电压，SIU信号保持低电平。ck3为高电平，第五晶体管T5导通，由此将下拉节点PD的电平拉高，同时对第二电容C2充电，第二晶体管T2导通，维持输出节点的低电平。第六晶体管T6将上拉节点PU的电压拉低，从而使第一晶体管T1处于截止状态。
第五阶段(t5)：ck4为高电平，其余时钟信号为低电压，SIU信号变为高电平。此时，由ck4控制的第三晶体管T3导通，重复以上第一阶段的步骤，从而开始该移位寄存器单元下一个周期的操作。
图4示出了第一实施例的栅极驱动电路的级联图。该实施例的移位寄存器单元通过级联的方式构成栅极驱动电路，由此，通过移位寄存器单元的移位而实现对各像素行的逐行扫描。图中，SIU和SID分别为正向和反向扫描的输入启动脉冲信号。
如图4所示，在该实施例中，除了第一级移位寄存器单元SR1之外，每个移位寄存器单元SRn的第一输入端OUT_N-1连接上一级移位寄存器单元SRn-1的输出，第一级移位寄存器单元SR1的第一输入端OUT_N-1则与启动信号SIU相连；除了最后一级移位寄存器单元SRN之外，每个移位寄存器单元SRn的第二输入端OUT_N+1连接下一级移位寄存器单元SRn+1的输出，而最后一级移位寄存器单元SRN的第二输入端OUT_N+1与启动信号SID相连。
如图4所示，在该移位寄存器中，后一级移位寄存器单元的输出信号时序相比于前一级移位寄存器单元的输出信号时序，高电平信号向后顺延一个周期。具体地，相邻的四个移位寄存器单元(第i、i+1、i+2、i+3级)的移位寄存器单元的时钟信号满足以下关系：
(1)对于第i个移位寄存器单元，其时钟信号输入端CK1、CK2、CK3和CK4输入的时钟信号分别为ck1、ck2、ck3和ck4；
(2)对于第i+1个移位寄存器单元，其时钟信号输入端CK1、CK2、CK3和CK4输入的时钟信号分别为ck2、ck3、ck4和ck1；
(3)对于第i+2个移位寄存器单元，其时钟信号输入端CK1、CK2、CK3和CK4输入的时钟信号分别为ck3、ck4、ck1和ck2；
(4)对于第i+3个移位寄存器单元，其时钟信号输入端CK1、CK2、CK3和CK4输入的时钟信号分别为ck4、ck1、ck2和ck3。
本领域技术人员应当清楚，对于第i+4个移位寄存器单元而言，其时钟信号的输入与第i个移位寄存器相同，即时钟信号输入端CK1、CK2、CK3和CK4输入的时钟信号分别为ck1、ck2、ck3和ck4，依次类推。
需要说明的是，上述i为大于等于1的整数，且i+3≤n。
对于其中的一个移位寄存器单元SRn，在正向移位时，输入端OUT_N-1接收来自上一级移位寄存器单元SRn-1的输出信号OUTi-1或开启信号SIU作为启动信号，以控制移位寄存器的操作。在反向移位时，输入端OUT_N+1接收来自下一级移位寄存器单元SRn+1的输出信号OUTi+1或开启信号SID作为启动信号。
本领域技术人员可以清楚，级联的该移位寄存器个数可以根据需要进行设计，其可以为大于等于2的任意级，只要其时钟信号按照上述顺序进行轮换即可。
根据本实施例的移位寄存器级联结构，只需要匹配控制信号和输入信号的时序便可实现正向扫描和反向扫描的切换，减少了电路的控制信号(其他现有的移位寄存器大都需要外加两根方向控制信号)，利于窄边框和高分辨率的显示面板布线。
图5和图6分别显示了该第一实施例在正向移位和反向移位时的信号时序图。
结合图1和图4，来描述当栅极驱动器正向移位以对像素行进行正向扫描时图5所示的信号时序图。为了便于描述，在图4中按照从上到下的顺序将移位寄存器单元依次称作第1级移位寄存器单元、第2级移位寄存器单元、第3级移位寄存器单元、第4级移位寄存器单元和第5级移位寄存器单元，分别对应于上述 第i个-第i+4个移位寄存器单元。
首先，与第1级移位寄存器单元SR1的输入端OUT_N-1相连的开启信号SIU和与输入端CK4相连的时钟信号ck4为高电平，其他时钟信号以及与输入端OUT_N+1相连的信号为低电平，该时段在此称为第一时段(图5中的①)。此时，第三晶体管T3导通，将SIU的高电平信号传输到第一晶体管T1的栅极，第一晶体管T1导通，并对第一电容C1充电。同时第七晶体管T7导通。此时，上拉节点PU的电压拉高，下拉节点PD的电压则由PU电压慢慢拉低，第二电容C2两端都为低电平。此时，与输入端CK1相连的时钟信号ck1为低电平，输出节点的电压Out1为低电平。也可以将该时段称作本级预充电时段。
在第二个时段(图5中的②)，与输入端CK1相连的时钟信号ck1变为高电平，开启信号SIU变为低电平，第三晶体管T3截止，上拉节点PU继续保持高电平。与输入端CK1相连的时钟信号ck1变为高电平，输出节点的电压由低电平跳变到高电平，即，图4中的OUT1输出高电平。第一电容C1的自举效应将PU点的电压泵高，此时便可使第一晶体管T1完全输出时钟信号ck1的高电平到输出节点。这时，由于第七晶体管T7导通，下拉节点PD的电压被拉低。该时段是本级移位寄存器单元进行扫描的时段，也可称为本级扫描时段。同时，OUT1输入到第2级(即下一级)移位寄存器单元SR2的输入端OUT_N-1，与第2级移位寄存器单元SR2的输入端CK4相连的时钟信号ck1为高电平。因此，对于第2级移位寄存器单元SR2，执行与第1级移位寄存器单元SR1在第一个时段中相同的操作。
在第三个时段(图5中的③)，时钟信号ck2为高电平，其余时钟信号为低电平，第四晶体管T4导通。由于第四晶体管T4导通，上拉节点PU的电压不再自举，但仍可以维持第一晶体管T1的导通，输出节点的电压由高电平变到低电平。可以将此时段称作本级复位时段。输入到第2级移位寄存器单元SR2的输入端OUT_N-1的OUT1为低电平，与第2级输入端CK1相连的时钟信号ck2为高电平。因此，对于第2级移位寄存器单元SR2，执行与第1级移位寄存器单元SR1在第二个时段中相同的操作，OUT2为高电平，此时段是第2级扫描时段。同时，高电平的OUT2输入到第3级移位寄存器单元SR3的输入端OUT_N-1，与第3级移位寄存器单元SR3的输入端CK4相连的时钟信号ck2为高电平。因此，对于第3级移位寄存器单元SR3，执行与第1级移位寄存器单元SR1在第一个时段 中相同的操作。
在接下来的第四个时段(图5中的④)，时钟信号ck3为高电平，其余时钟信号为低电压。第五晶体管T5导通，由此将下拉节点PD的电平拉高，同时对第二电容C2充电，第二晶体管T2导通，维持OUT1输出的低电平。此时段仍称作本级复位时段。第六晶体管T6将上拉节点PU的电压拉低，从而使第一晶体管T1处于截止状态。输入到第2级移位寄存器单元SR2的输入端OUT_N-1的OUT1为低电平，与第2级输入端CK2相连的时钟信号ck3为高电平。因此，对于第2级移位寄存器单元SR2，执行与第1级移位寄存器单元SR1在第三个时段中相同的操作，OUT2为低电平。同时，OUT2输入到第3级移位寄存器单元SR3的输入端OUT_N-1，高电平时钟信号ck3与第3级移位寄存器单元SR3的输入端CK1相连。因此，对于第3级移位寄存器单元SR3，执行与第1级移位寄存器单元SR1在第二个时段中相同的操作，OUT3为高电平，此时段是第3级的扫描时段。同时，高电平的OUT3输入到第4级移位寄存器单元SR4的输入端OUT_N-1，高电平的时钟信号ck3与第4级移位寄存器单元SR4的输入端CK4相连。因此，对于第4级移位寄存器单元SR4，执行与第1级移位寄存器单元SR1在第一个时段中相同的操作。
在接下来的第五个时段(图5中的⑤)，开启信号SIU和时钟信号ck4为高电平，重复与第一个时段相同的操作。
为了实现反向移位以进行反向扫描，在该实施例中，只需将时钟信号ck4与ck2交换。当时钟信号ck4的高电平脉冲在时钟信号ck1前时为正向扫描，同时时钟信号ck4与OUT_N-1同步；当时钟信号ck2的高电平脉冲在时钟信号ck1前时为反向扫描，同时时钟信号ck2与OUT_N+1同步。匹配波形示意图可参考图5和图6，其中反向扫描时的启动信号为SID。
即，为了实现在正向移位与反向移位之间进行切换，将时钟信号ck4和时钟信号ck2的接入位置进行交换即可，而不需要改变输入端OUT_N-1和输入端OUT_N+1的连接关系。这样，无论在正向扫描还是反向扫描，第一晶体管T1和第二晶体管T2都能在移位寄存器单元进行本行扫描之前的一个时段对上拉节点PU进行预充电，以及在移位寄存器单元进行本行扫描之后的一个时段开始对上拉节点PU进行放电。无论是正向扫描还是反向扫描，所述输入端OUT_N-1均在本级移位寄存器单元进行本行扫描的前一个时段接收有效启动信号，以控制 本级移位寄存器单元在当前时段输出高电平信号的信号，并且移位寄存器单元在本行扫描之后输出低电平信号。反向扫描时的时序图如图6所示，在此不再赘述。
本领域技术人员可以理解，SIU和SID可以是相同的信号，只需调节相应的时钟控制信号的时序匹配。需要说明的是，在SIU和SID是相同的信号时，如果需要正反扫描正常工作，移位寄存器单元电路的第1级和最后一级的时钟信号接入必须不同，这样才不会出现第1级和最后一级电路同时输入启动脉冲的现象。
第一实施例采用的电路简单，只采用了七个晶体管和两个电容就实现了双向移位的功能。同时，在本级移位寄存器单元进行扫描时使上拉节点PU因自举效应而保持较高的电压，保证了输出的稳定性。
[第二实施例]
第二实施例是在第一实施例的基础上进行的改进。该实施例的栅极驱动电路的级联方式与第一实施例相同，所不同的是各个移位寄存器单元的结构。图7和图8示出了第二实施例的移位寄存器单元的电路结构。
变型1
根据第一实施例的技术方案，只采用了时钟信号ck3控制第五晶体管T5，利用电容保持就可以维持电路正常工作。如图1所示，第一实施例采用了二极管接法。如图7所示，第二实施例中的第五晶体管T5的漏极接高电平VGH。
变型2
如图8所示，与第一实施例相比，在第二实施例的移位寄存器单元的输入模块21中，第三晶体管T3的栅极与输入信号OUT_N-1相连，源极与时钟信号ck4相连，第四晶体管T4的栅极与输入信号OUT_N+1相连，漏极与时钟信号ck2相连。
变型3
第二实施例的移位寄存器单元的下拉模块还包括第八晶体管T8和第九晶体管T9。第八晶体管T8的漏极和栅极相连并连接至时钟信号ck2，源极与下拉 节点PD相连，第九晶体管T9的栅极与时钟信号ck4相连，源极与下拉节点PD相连，且漏极与电源正压VGH相连。
根据第二实施例的技术方案，与第一实施例的技术方案相比较，在输入模块21中，将第三晶体管T3和第四晶体管T4的输入信号互换，而电路功能不变。这里需要注意的是，优选地如图2所示，将时钟信号ck4和ck2分别输入到第三晶体管和第四晶体管的栅极，由此可以在正常输出后继续下拉PU且不会存在漏电。如果OUT_N-1和OUT_N+1输入到栅极且ck2和ck4分别与源极或漏极相连，可能会产生由T3和T4的漏电使PU点电位被拉高的风险。
其次，添加了第九晶体管T9接收时钟信号ck4以拉高下拉节点PD的电平，由此可以减小第二电容C2的值或只采用寄生电容。此外，添加了第八晶体管T8并向其施加时钟信号ck2以进一步拉高下拉节点PD的电平。
可以实现以上3种变型中的任意一种或其组合，以构成更多的变型作为第一实施例的备选方案。
[第三实施例]
第三实施例是移动寄存器单元的另一种改进，其中使用PMOS晶体管来替代第一实施例中的NMOS晶体管。如图9所示，可以采用与第一实施例NMOS相同的结构来实现第三实施例，只需要将电源电压由VGL改为VGH。
[第四实施例]
第三实施例是移动寄存器单元的另一种改进，其中使用PMOS晶体管来替代第二实施例中的NPOS晶体管。如图10所示，可以采用与第二实施例NMOS相同的结构来实现第四实施例，只需要将电源电压由VGL改为VGH。
上面已经详细说明了本发明提供的移位寄存器单元及栅极驱动器。除此之外，本发明还提供包括上述栅极驱动器的图像显示装置，具体地，所述显示装置可以为液晶显示装置，例如液晶面板、液晶电视、手机、电子阅读器、液晶显示器等。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于 限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种移位寄存器单元，其特征在于，包括，
    输入模块，根据第一时钟信号，将第一输入信号提供至第一节点；
    第一控制模块，与所述输入模块连接于所述第一节点，根据所述第一输入信号和第三时钟信号，通过将所述第三时钟信号提供至所述移位寄存器单元的输出节点来实现上拉输出，并随后根据第二输入信号，通过将电源电压提供至所述输出节点来实现下拉输出，其中所述第二输入信号由所述输入模块根据第二时钟信号提供至所述第一节点；
    第二控制模块，根据第四时钟信号，将所述输出节点的电平保持在所述电源电压；
    其中，所述第一控制模块包括第一晶体管，所述第一晶体管在上拉输出后继续导通以进行下拉输出，所述第二控制模块包括第二晶体管，用于保持所述输出节点的电平。
  2. 如权利要求1所述的移位寄存器单元，其特征在于，所述第一晶体管与所述第二晶体管的尺寸比率为30∶1～1∶1。
  3. 如权利要求2所述的移位寄存器单元，其特征在于，所述第一晶体管与所述第二晶体管的尺寸比率为6∶1～3∶1。
  4. 如权利要求2或3所述的移位寄存器单元，其特征在于，所述第一晶体管的栅极与第一节点相连，源极与所述第三时钟信号相连，漏极与所述输出节点相连，在所述第一晶体管的栅极和漏极之间具有第一电容，作为第一节点的电压保持电容；
    所述第一控制模块还包括第七晶体管，所述第七晶体管的栅极与所述第一节点相连，源极与第二电容的一端在第二节点处相连，漏极与所述电源电压相连，所述第二电容的另一端与所述电源电压相连，所述第二电容用作第二节点的电压保持电容。
  5. 如权利要求4所述的移位寄存器单元，其特征在于，所述第一电容和第二电容是所述晶体管之间的固有寄生电容，或是附加电容器。
  6. 如权利要求4所述的移位寄存器单元，其特征在于，所述第二晶体管的栅极连接至所述第二节点，漏极连接至所述电源电压，源极连接至所述输出节点；
    所述第二控制模块还包括第五晶体管，所述第五晶体管的栅极和漏极连接至所述第四时钟信号，源极与所述第二节点相连；以及第六晶体管，第六晶体管的栅极与所述第二节点相连，源极与第一节点相连，漏极与所述电源电压相连。
  7. 如权利要求6所述的移位寄存器单元，其特征在于，所述第二控制模块还包括第八晶体管，所述第八晶体管的栅极和漏极连接至所述第二时钟信号，源极与所述第二节点相连；以及第九晶体管，第九晶体管的栅极与所述第一时钟信号相连，源极与所述第二节点相连，漏极与第二电源电压相连，所述第二电源电压与所述电源电压的极性相反。
  8. 如权利要求4所述的移位寄存器单元，其特征在于，所述第二晶体管的栅极连接至所述第二节点，漏极连接至所述电源电压，源极连接至所述输出节点；
    所述第二控制模块还包括第五晶体管，所述第五晶体管的栅极连接至所述第四时钟信号，源极与所述第二节点相连，漏极与第二电源电压相连，所述第二电源电压与所述电源电压的极性相反；以及第六晶体管，第六晶体管的栅极与所述第二节点相连，源极与第一节点相连，漏极与所述电源电压相连。
  9. 如权利要求6-8之一所述的移位寄存器单元，其特征在于，所述输入模块包括：
    第三晶体管，所述第三晶体管的栅极连接至所述第一时钟信号，源极连接至所述第一输入信号，漏极连接至所述第一节点；以及
    第四晶体管，所述第四晶体管的栅极连接至所述第四时钟信号，漏极连接至所述第二输入信号，源极连接至所述第一节点。
  10. 如权利要求6-8之一所述的移位寄存器单元，其特征在于，所述输入模块包括：
    第三晶体管，所述第三晶体管的栅极连接至所述第一输入信号，源极连接至所述第一时钟信号，漏极连接至所述第一节点；以及
    第四晶体管，所述第四晶体管的栅极连接至所述第二输入信号，漏极连接至所述第四时钟信号，源极连接至所述第一节点。
  11. 如权利要求9所述的移位寄存器单元，其特征在于，所述第一晶体管到第九晶体管均为NMOS晶体管，所述电源电压为负电压，所述第二电源电压为正电压。
  12. 如权利要求10所述的移位寄存器单元，其特征在于，所述第一晶体管到 第九晶体管均为PMOS晶体管，所述电源电压为正电压，所述第二电源电压为负电压。
  13. 一种栅极驱动电路，其特征在于，包括权利要求1至12中任一项所述的移位寄存器单元。
  14. 如权利要求13所述的栅极驱动电路，其特征在于，由N个所述移位寄存器单元级联而成，N为大于1的自然数，
    除了第1级移位寄存器单元之外，每个移位寄存器单元的第一输入端连接上一级移位寄存器单元的输出节点，第1级移位寄存器单元的第一输入端与第一开启信号相连；
    除了最后1级移位寄存器单元之外，每个移位寄存器单元的第二输入端连接下一级移位寄存器单元的输出节点，最后1级移位寄存器单元的第二输入端与第二开启信号相连；
    当所述移位寄存器单元进行正向移位时，所述第一时钟信号的高电平脉冲在所述第三时钟信号之前，并且所述第一时钟信号的波形与上一级移位寄存器单元的输出节点的电压波形相同；
    当所述移位寄存器单元反向移位时，所述第二时钟信号的高电平脉冲在所述第三时钟信号之前，并且所述第二时钟信号的波形与下一级移位寄存器单元的输出节点的电压波形相同。
  15. 一种显示装置，其特征在于，包括权利要求13或14所述的栅极驱动电路。
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