WO2016114320A1 - 多層基板 - Google Patents

多層基板 Download PDF

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Publication number
WO2016114320A1
WO2016114320A1 PCT/JP2016/050877 JP2016050877W WO2016114320A1 WO 2016114320 A1 WO2016114320 A1 WO 2016114320A1 JP 2016050877 W JP2016050877 W JP 2016050877W WO 2016114320 A1 WO2016114320 A1 WO 2016114320A1
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WIPO (PCT)
Prior art keywords
semiconductor substrate
conductive particles
substrate
holes
hole
Prior art date
Application number
PCT/JP2016/050877
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English (en)
French (fr)
Inventor
誠一郎 篠原
恭志 阿久津
朋之 石松
Original Assignee
デクセリアルズ株式会社
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Publication date
Application filed by デクセリアルズ株式会社 filed Critical デクセリアルズ株式会社
Priority to US15/543,113 priority Critical patent/US11901325B2/en
Priority to KR1020177017942A priority patent/KR102094725B1/ko
Priority to CN201680004716.6A priority patent/CN107210287B/zh
Publication of WO2016114320A1 publication Critical patent/WO2016114320A1/ja

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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Definitions

  • the present invention relates to a multilayer substrate.
  • multilayer substrates are used in which semiconductor substrates in which electronic components such as ICs are incorporated are stacked.
  • a through electrode having bumps is formed on each semiconductor substrate, and through electrodes of opposing semiconductor substrates are connected by bump reflow (Patent Document 1) or between opposing semiconductor substrates.
  • Patent Document 2 there is a method (Patent Document 2) in which an anisotropic conductive film in which conductive particles are dispersed is sandwiched in an insulating adhesive layer, and through electrodes are connected by heating and pressing.
  • the through electrode 6 generally includes (a) a (b) through hole 4h formed in the semiconductor substrate 3, and (c) a plated film 4a formed by electroless plating.
  • a through hole is formed by patterning to leave the plating film 4a inside the through hole 4h.
  • D Further, a metal 5 is filled in the through hole by providing a mask in a predetermined pattern and performing electrolytic plating. It is formed by.
  • the method of connecting opposite through electrodes using anisotropic conductive films and laminating semiconductor substrates can simplify the manufacturing process of the multilayer substrate to some extent, but the anisotropic conductive films are insulated. Because conductive particles are randomly dispersed in the adhesive layer, the conductive characteristics of the anisotropic conductive film may not be sufficiently sandwiched between the through electrodes of the semiconductor substrate facing each other, resulting in variation in conduction characteristics. There's a problem. On the other hand, since there are many conductive particles that do not contribute to the connection of the through electrodes between the opposing semiconductor substrates, there is a problem in that unnecessary conductive particles are expensive.
  • an object of the present invention is to provide a multilayer substrate having excellent conduction characteristics by laminating a semiconductor substrate using an anisotropic conductive film at a low cost with a simple manufacturing process.
  • the present inventor in manufacturing a multilayer substrate by laminating a semiconductor substrate using an anisotropic conductive film, in the insulating adhesive of the anisotropic conductive film with respect to the through-hole formed in the previous stage of the formation of the through electrode
  • the opposing through holes can be reliably connected with the conductive particles. It has been found that the number of conductive particles that do not contribute can be reduced, the manufacturing process of the multilayer substrate can be significantly simplified, and the manufacturing cost of the multilayer substrate can be reduced, and the present invention has been conceived.
  • the present invention is a multilayer substrate in which a semiconductor substrate having a through hole is laminated, and in the plan view of the multilayer substrate, conductive particles are selectively present at positions where the through holes are opposed to each other,
  • a multilayer substrate having a connection structure in which opposing through holes are connected by conductive particles, and semiconductor substrates on which the through holes are formed are bonded to each other with an insulating adhesive.
  • the multilayer substrate is a multilayer substrate in which a first semiconductor substrate having a through hole and a second semiconductor substrate having a through hole are laminated, The through hole of the first semiconductor substrate and the through hole of the second semiconductor substrate are opposed to each other and connected by conductive particles selectively disposed between them.
  • the present invention also relates to a method for manufacturing a multilayer substrate in which through-holes formed in a semiconductor substrate are opposed to each other, wherein the conductive particles correspond to the positions in a plan view of the multilayer substrate where the through-holes are opposed to each other.
  • An anisotropic conductive film selectively disposed on the insulating adhesive layer is sandwiched between semiconductor substrates having through holes, and the anisotropic conductive film is heated and pressed to anisotropically conduct these semiconductor substrates.
  • a method for manufacturing a multi-layer substrate that is electrically connected.
  • this multilayer substrate a method of manufacturing a multilayer substrate in which a first semiconductor substrate having a through hole and a second semiconductor substrate having a through hole are joined with the through holes facing each other.
  • An anisotropic conductive film having conductive particles selectively disposed on an insulating adhesive layer corresponding to the arrangement of through holes is sandwiched between a first semiconductor substrate and a second semiconductor substrate, and the anisotropic conductive film
  • a method of manufacturing a multi-layer substrate in which a first semiconductor substrate and a second semiconductor substrate are anisotropically conductively connected by heating and pressing is provided.
  • the present invention provides an anisotropic conductive film used in the above-described method for producing a multilayer substrate, wherein conductive particles are selectively arranged on the insulating adhesive layer in correspondence with the arrangement of through holes connected by the anisotropic conductive film.
  • An anisotropic conductive film is provided.
  • an anisotropic conductive film useful for the above-mentioned method for producing a multilayer substrate, an anisotropic conductive film including an insulating adhesive layer and conductive particles arranged in the insulating adhesive layer, two or more An anisotropic conductive film in which a plurality of conductive particles having different sizes or types is contained in the conductive particle unit is provided.
  • the conduction characteristics are stabilized because the through holes of the semiconductor substrate are reliably connected by the conductive particles.
  • through holes are connected to each other with conductive particles without filling the through holes with metal in the semiconductor substrate, and conductive particles that do not contribute to the connection are reduced between the semiconductor substrates. Therefore, the manufacturing cost of the multilayer substrate is remarkably suppressed. For the same reason, it is effective in reducing the number of instrumentation steps.
  • the multilayer substrate of the present invention can be manufactured in a simple process by using a specific anisotropic conductive film.
  • the multilayer substrate of the present invention can be provided at a much lower price.
  • FIG. 1 is a cross-sectional view of a multilayer substrate 1A according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a multilayer substrate 1B according to an embodiment of the present invention.
  • FIG. 3A is an explanatory diagram of the manufacturing process of the multilayer substrate 1B.
  • FIG. 3B is an explanatory diagram of the manufacturing process of the multilayer substrate 1B.
  • FIG. 3C is an explanatory diagram of the manufacturing process of the multilayer substrate 1B.
  • FIG. 3D is an explanatory diagram of the manufacturing process of the multilayer substrate 1B.
  • FIG. 4A is an explanatory diagram of arrangement of conductive particles with respect to a through hole before anisotropic conductive connection.
  • FIG. 4A is an explanatory diagram of arrangement of conductive particles with respect to a through hole before anisotropic conductive connection.
  • FIG. 4B is an explanatory diagram of the arrangement of the conductive particles with respect to the through hole after the anisotropic conductive connection.
  • FIG. 5A is an explanatory diagram of arrangement of conductive particles with respect to a through hole before anisotropic conductive connection.
  • FIG. 5B is an explanatory diagram of the arrangement of the conductive particles with respect to the through hole after the anisotropic conductive connection.
  • FIG. 6A is an explanatory diagram of the arrangement of the conductive particles with respect to the through hole before the anisotropic conductive connection.
  • FIG. 6B is an explanatory diagram of the arrangement of the conductive particles with respect to the through hole after the anisotropic conductive connection.
  • FIG. 7A is an explanatory diagram of the arrangement of the conductive particles with respect to the through hole before the anisotropic conductive connection.
  • FIG. 7B is an explanatory diagram of the arrangement of the conductive particles with respect to the through hole after the anisotropic conductive connection.
  • FIG. 8 is an explanatory view of the arrangement of the conductive particles with respect to the through hole before the anisotropic conductive connection.
  • FIG. 9 is a cross-sectional view of a multilayer substrate 1C according to an embodiment of the present invention.
  • FIG. 10 is an arrangement diagram of electrodes and conductive particles on the surface of the semiconductor substrate used for the production of the multilayer substrate of Example 1.
  • FIG. 11 is an arrangement diagram of electrodes and conductive particles on the surface of the semiconductor substrate used for manufacturing the multilayer substrate of Example 4.
  • FIG. 12 is an arrangement diagram of electrodes and conductive particles on the surface of the semiconductor substrate used in the production of the multilayer substrate of Example 5.
  • FIG. 13 is an arrangement diagram of electrodes and conductive particles on the surface of the semiconductor substrate used for manufacturing the multilayer substrate of Example 6.
  • FIG. 14 is a process explanatory diagram of the method for manufacturing the through electrode.
  • FIG. 1 is a cross-sectional view of a multilayer substrate 1A according to an embodiment of the present invention.
  • the multi-layer substrate 1A is formed by stacking three layers of semiconductor substrates 3A, 3B, and 3C on a wiring substrate 2, and each of the semiconductor substrates 3A, 3B, and 3C is a semiconductor wafer on which semiconductor components such as ICs are formed. is there.
  • a through hole 4X is formed in the wiring board 2, and through holes 4A, 4B, and 4C are formed in each of the semiconductor substrates 3A, 3B, and 3C, and a portion where the through hole 4X is exposed on the surface of the wiring board 2, Electrode pads 9 are formed in portions where the through holes 4A, 4B, 4C are exposed on the surface of the semiconductor substrate.
  • semiconductor chips may be used as the semiconductor substrates 3A, 3B, 3C.
  • the number of stacked semiconductor substrates constituting the multilayer substrate is not particularly limited.
  • Through hole 4A of first semiconductor substrate 3A and through hole 4B of second semiconductor substrate 3B are opposed to multilayer substrate 1A, and are electrically connected by conductive particles 11 selectively disposed therebetween.
  • that the conductive particles 11 are selectively disposed between the through holes 4A and 4B is that the conductive particles 11 are present on the opposing surface of the through holes 4A and 4B or in the vicinity thereof even when seen in a plan view. It means that one or more conductive particles 11 are captured in the through holes 4A, 4B. Arrangement so that one to a dozen or more are captured is preferable in terms of both cost and performance.
  • a plurality of conductive particles may overlap in the film thickness direction.
  • size, kind, etc. of the conductive particle may differ.
  • the accuracy of alignment between the semiconductor substrates 3A and 3B and the conductive particles 11 can be relaxed.
  • the opposing surfaces of the first semiconductor substrate 3A and the second semiconductor substrate 3B are bonded to each other with an insulating adhesive 12.
  • the insulating adhesive 12 is formed from an insulating adhesive layer of an anisotropic conductive film described later.
  • the through hole 4B of the second semiconductor substrate 3B connected to the through hole 4A of the first semiconductor substrate 3A is also opposed to the through hole 4C of the third semiconductor substrate 3C on the third semiconductor substrate 3C side.
  • Through holes 4B of the second semiconductor substrate 3B and the through holes 4C of the third semiconductor substrate 3C are electrically connected by the conductive particles 11 selectively disposed therebetween.
  • the opposing surfaces of the second semiconductor substrate 3B and the third semiconductor substrate 3C are also bonded to each other by the insulating adhesive 12. Further, the through holes 4X of the wiring board 2 and the through holes 4A of the first semiconductor substrate 3A are similarly connected by the conductive particles 11.
  • the multilayer substrate 1A has a connection structure in which the through holes 4X of the wiring substrate 2 and the through holes 4A, 4B, and 4C of the three-layer semiconductor substrate are linearly connected in the stacking direction of the multilayer substrate. According to the connection structure in which the through-holes in each layer are connected in a straight line, the electric transmission path is shortened, so that the transmission speed can be improved.
  • 1 A of multilayer substrates are manufactured by connecting each layer which comprises a multilayer substrate using the anisotropic conductive film of this invention in which conductive particles have specific arrangement
  • the number of such conductive particles 11 is as follows: The total number of conductive particles existing between the first semiconductor substrate and the second semiconductor substrate is preferably 5% or less, more preferably 0.5% or less, and particularly almost all of the conductive particles 11 are captured by the through holes 4A and 4B. To be. The same applies to other semiconductor substrates constituting the multilayer substrate 1A.
  • the wiring substrate 2 constituting the multilayer substrate 1A a glass epoxy substrate such as FR4 can be used.
  • the wiring substrate 2 an IC chip or a silicon wafer for IC formation may be used.
  • the wiring board 2 is appropriately selected according to the use of the multilayer board 1A.
  • solder balls 8 may be provided on the electrode portions of the wiring board 2 as necessary.
  • the semiconductor substrates 3A, 3B, and 3C are not particularly limited as long as they have through holes 4A, 4B, and 4C.
  • a general semiconductor material such as silicon can be used.
  • the specifications of the through holes 4A, 4B, 4C can be set as appropriate.
  • the through holes 4A, 4B, and 4C include the electrode pads 9.
  • the through holes 4A, 4B, and 4C of the semiconductor substrates 3A, 3B, and 3C are linearly connected across at least two layers of the semiconductor substrate in the thickness direction of the multilayer substrate 1A.
  • the through holes 4A, 4B, and 4C are arranged so as to be connected linearly across the front and back of the multilayer substrate 1A.
  • the multilayer substrate 1B shown in FIG. 2 has a connection structure in which the through holes 4X, 4A, 4B, and 4C of each layer are connected in a straight line, and has a heat sink 7 for heat dissipation connected to the through hole 4C in the outermost layer. . Therefore, the multilayer substrate 1B can efficiently dissipate the heat released from the electronic components such as the IC formed on the wiring substrate 2 and the semiconductor substrates 3A, 3B, and 3C by the heat sink 7.
  • ⁇ Multilayer substrate manufacturing method> As a method for manufacturing a multilayer substrate of the present invention, for example, in the case of the multilayer substrate 1B of FIG. 2, first, as shown in FIG. 3A, a wiring substrate 2 having a through hole 4X and a semiconductor substrate 3A having a through hole 4A The anisotropic conductive film 10A of the present invention in which the conductive particles 11 are selectively arranged on the insulating adhesive layer 12 corresponding to the arrangement of the through holes 4X and 4A to be connected is sandwiched between the anisotropic conductive films. By heating and pressing 10A, the wiring substrate 2 and the first semiconductor substrate 3A are anisotropically conductively connected to obtain a two-layer connection structure shown in FIG. 3B.
  • the wiring substrate 2 and the anisotropic conductive film 10A are aligned and overlapped so that the through holes 4X to be connected and the conductive particles 11 are aligned, and the first semiconductor substrate 3A is similarly positioned. These are superposed and superposed and heated and pressed to make anisotropic conductive connections.
  • the conductive particles corresponding to the through holes of the anisotropic conductive film (the conductive particles constituting the particle groups when the particle groups are formed as described later) and the through holes are connected to the CCD. Or the like, and may be performed by superimposing them.
  • the first semiconductor substrate 3A and the anisotropic conductive film 10B are aligned and overlapped, and the second semiconductor substrate 3B is aligned and stacked thereon, and heated and pressed to change the difference.
  • the conductive connection is made to obtain a three-layer connection structure shown in FIG. 3D.
  • the anisotropic conductive film and the third semiconductor substrate 3C are aligned and superimposed on the second semiconductor substrate 3B, and heated and pressed.
  • the heat sink 7 is connected to the third semiconductor substrate 3C with a heat conductive tape or the like, solder balls 8 are formed on the electrode pads 9 of the wiring substrate 2, and the multilayer substrate 1B is obtained by a conventional method.
  • solder balls 8 may be provided in place of the solder balls 8.
  • an alignment mark having a size of several tens of ⁇ m to several hundreds of ⁇ m is formed on the semiconductor substrate as an example. Alignment is performed.
  • the anisotropic conductive film has conductive particles arranged in a monodisperse or lattice shape, the anisotropic conductive film is not provided with an alignment mark.
  • the anisotropic conductive film used in the present invention is such that the conductive particles 11 are selectively arranged on the insulating adhesive layer 12 corresponding to the arrangement of the through holes to be connected. 11 can be substituted for the alignment mark. It is preferable to provide an alignment mark on the anisotropic conductive film including the arrangement of the conductive particles.
  • the conductive particles 11 are selectively disposed on the insulating adhesive layer 12 corresponding to the arrangement of the through holes to be connected.
  • An alignment mark is formed.
  • the alignment mark is preferably formed by arranging conductive particles. Thereby, the alignment mark can be detected clearly, and the addition of a new process for attaching the alignment mark to the anisotropic conductive film becomes unnecessary.
  • the alignment mark may be formed by partially curing the insulating adhesive layer 12 by laser irradiation or the like. This makes it easy to change the position where the alignment mark is attached.
  • a metal mold having a convex portion corresponding to the arrangement of the conductive particles 11 is subjected to a known processing method such as machining, laser processing, or photolithography on a metal plate.
  • the mold is filled with a curable resin and cured to produce a resin mold in which irregularities are reversed, and conductive particles are placed in the recesses of the resin mold, and an insulating adhesive layer forming composition is formed thereon.
  • the product can be filled, cured, and removed from the mold.
  • a member having through holes formed in a predetermined arrangement is provided on the insulating adhesive layer forming composition layer, and from there
  • the conductive particles 11 may be supplied and passed through the through holes.
  • the conductive particles 11 used in the anisotropic conductive film 10 can be appropriately selected from those used in known anisotropic conductive films. Examples thereof include metal particles such as solder, nickel, cobalt, silver, copper, gold, and palladium, and metal-coated resin particles.
  • the metal coating of the metal-coated resin particles can be formed using a known metal film forming method such as an electroless plating method or a sputtering method. The metal coating is not particularly limited as long as it is formed on the surface of the core resin material.
  • the core resin material may be formed only from a resin, or may contain conductive fine particles in order to improve conduction reliability.
  • the conductive particles among the particles described above, it is preferable to use solder particles in terms of conduction reliability and cost. On the other hand, it is preferable to use metal-coated resin particles when a reflow step is not necessary in the subsequent step.
  • the metal-coated resin particles are used as the conductive particles. This is because, when used, it becomes possible to lower the temperature of heating and pressurization, and the range of materials for the insulating adhesive is widened.
  • conductive particles two or more kinds of particles having different sizes and types can be used in combination.
  • the arrangement, particle diameter, and type of the conductive particles 11 are appropriately selected according to the opening diameter of the through holes from the viewpoint of the stability of bonding between the through holes.
  • the particle diameter of the conductive particles 11 is usually set to the opening of the through holes 4A and 4X. It is preferable to make it larger than the aperture.
  • the conductive particles 11 are formed of solder particles, as shown in FIGS. 4A and 4B, the plated film 4a of the through hole is easily wetted by the solder particles melted by heating and pressing at the time of anisotropic conductive connection.
  • the particle diameter of the conductive particles 11 be equal to or larger than the opening diameters of the through holes 4A and 4B. Thereby, the conductive particles 11 are pressed by the through holes 4A and 4B, and the through holes 4A and 4B can be reliably connected by the conductive particles 11.
  • the particle group 11 a composed of a plurality of conductive particles 11 may be arranged so as to overlap in the thickness direction of the anisotropic conductive film 10.
  • the electrically-conductive particle 11 can be made to approach to the deeper position of the through holes 4A and 4B.
  • the plurality of conductive particles may be different in size and type.
  • the large-diameter conductive particles 11p are opposed to the through holes 4A and 4B, and the small-diameter conductive particles 11q are used as electrode pads around the large-diameter conductive particles 11p. Place it at the location where it will be captured. In this case, it is preferable that the large-diameter conductive particles 11p are more easily deformed than the small-diameter conductive particles 11q.
  • the large-diameter conductive particles 11p are sandwiched between the through holes 4A and 4B as in the connection structure shown in FIG.
  • the conductive particles 11q can fill the gaps between the through holes 4A, 4B and the large-diameter conductive particles 11p, thereby improving the conductivity between the through holes 4A, 4B and the conductive particles.
  • the particle group 11a by making the conductive particles contact each other, the through holes 4A and 4B and the conductive particles are easily brought into contact with each other.
  • the anisotropic conductive film 10p having the large-diameter conductive particles 11p is temporarily bonded to one semiconductor substrate 3A to have the small-diameter conductive particles 11q.
  • the anisotropic conductive film 10q may be temporarily bonded to the other semiconductor substrate 3B, and then the semiconductor substrates 3A and 3B may be heated and pressurized.
  • the conductive particles may be exposed from the insulating adhesive layer 12, and in particular, the large-diameter conductive particles 11p sandwiched between the through holes 4A and 4B are as follows. It is preferable to expose. By exposing the conductive particles from the insulating adhesive layer, the alignment between the conductive particles and the through holes is facilitated, and since the insulating adhesive layer 12 is not interposed between the conductive particles and the through holes, the conductive particles and Conductivity with the through hole is improved.
  • the exposed surface of the conductive particles of the anisotropic conductive film may be protected by covering with a separator film or the like, and the conductive particles may be exposed when the anisotropic conductive film is used.
  • an insulating resin layer used in a known anisotropic conductive film can be appropriately employed.
  • a photo radical polymerization type resin layer containing an acrylate compound and a photo radical polymerization initiator a heat radical polymerization type resin layer containing an acrylate compound and a heat radical polymerization initiator, a heat containing an epoxy compound and a heat cationic polymerization initiator
  • a cationic polymerization type resin layer, a thermal anion polymerization type resin layer containing an epoxy compound and a thermal anion polymerization initiator, or the like can be used.
  • these resin layers can be polymerized as necessary.
  • the insulating adhesive layer 12 may be formed from a plurality of resin layers.
  • the insulating adhesive layer 12 may have flexibility and adhesiveness to withstand cutting. preferable.
  • an insulating filler such as silica fine particles, alumina, or aluminum hydroxide may be added to the insulating adhesive layer 12.
  • the blending amount of the insulating filler is preferably 3 to 40 parts by mass with respect to 100 parts by mass of the resin forming the insulating adhesive layer.
  • an insulating spacer having a particle diameter that can be filled into the through hole may be added to the insulating adhesive layer 12 as necessary. Thereby, it becomes easy to ensure the uniformity of indentation at the time of anisotropic conductive connection.
  • a part of the resin of the insulating adhesive layer near the conductive particles may be polymerized in advance. This facilitates alignment between the through hole and the conductive particles, and can reduce the risk of occurrence of a short circuit.
  • ⁇ Deformation mode> In the anisotropic conductive film 10 described above, there are almost no conductive particles other than a predetermined position. On the other hand, there may be conductive particles that are not captured by the opposing through holes 4A and 4B even if they exist at predetermined positions. Therefore, after this anisotropic conductive film 10 is used for connecting the semiconductor substrates 3A and 3B, the number of conductive particles 11 not captured by the through holes 4A and 4B between the opposing semiconductor substrates 3A and 3B is as follows. The total number of the conductive particles 11 existing between the semiconductor substrates 3A and 3B facing each other is preferably 5% or less.
  • the multilayer substrate 1C shown in FIG. 9 includes an anisotropic conductive film that connects the through hole 4X of the wiring substrate 2 and the through hole 4A of the first semiconductor substrate 3A in the multilayer substrate 1A shown in FIG.
  • the conductive particles 11 are insulated corresponding to the portions where the through holes of the wiring substrate 2 or each of the semiconductor substrates 3A, 3B, 3C face each other. Those selectively disposed on the adhesive layer 12 are used. As a result, the conductive particles 11 and 11x are present at portions where the through holes 4X, 4A, 4B, and 4C are opposed to each other in a plan view of the multilayer substrate 1C. In other words, the conductive particles that are selectively disposed only with respect to the through holes do not necessarily exist between the opposing through holes.
  • the conductive particles 11 are selectively disposed at positions where the through holes 4A and 4B formed in the semiconductor substrate 3A are opposed to each other, and the through holes of the semiconductor substrate 3A.
  • the conductive particles 11x between the semiconductor substrate 3A and the semiconductor substrate 3B that do not contribute to these connections contribute to the connection between the through hole 4X of the wiring substrate 2 and the through hole 4A of the first semiconductor substrate 3A.
  • the conductive particles are not disposed or substantially not present at positions where the through holes do not face each other.
  • the conductive particles can be arranged as a particle group in which a plurality of conductive particles are close to each other.
  • positioned on one surface May be used to manufacture multilayer substrates.
  • the number of conductive particles constituting each particle group 11a is 3 or more, preferably 10 or more, more preferably 12 or more.
  • the interval between the particle groups 11a is set to be equal to or larger than the conductive particle diameter in order to avoid the occurrence of a short circuit, and is appropriately determined according to the through-hole interval of the semiconductor substrate.
  • the anisotropic conductive films in which the particle groups 11a are arranged on one surface at appropriate intervals are commonly used. By using it, the manufacturing cost of the multilayer substrate can be greatly reduced.
  • the arrangement, particle diameter, and type of the plurality of conductive particles constituting the particle group are appropriately determined from the viewpoint of the stability of bonding between the through holes as described above.
  • a plurality of conductive particles having different sizes or types may be included in one particle group, and the plurality of conductive particles overlap each other in the film thickness direction of the anisotropic conductive film.
  • the plurality of conductive particles may be arranged in the surface direction of the anisotropic conductive film in one particle group, and at least a part of the conductive particles contained in the particle group is exposed from the insulating adhesive layer. It may be.
  • the conductive particles are selectively present at positions where the through holes are opposed in a plan view of the multilayer substrate. And the through-hole which opposes is connected by the electrically-conductive particle arrange
  • the opposing through holes may be connected by the conductive particles 11 that are selectively disposed only between the opposing through holes, and the semiconductor substrate 3A on which the opposing through holes are formed. Conductive particles 11x that do not contribute to the connection of the opposing through holes may be included between 3B and 3C.
  • the multilayer substrate of the present invention can be used for various applications such as high-density semiconductor packages and various semiconductors that require high-density mounting. Further, the multilayer substrate may be cut into a predetermined size and used.
  • Examples 1 to 6 Comparative Example 1
  • Semiconductor substrate The semiconductor substrate 3 constituting the multilayer substrate is a rectangle having an outer shape of 7 mm ⁇ and a thickness of 100 ⁇ m. As shown in FIG. 7, the through-holes 4 having chromium electrode pads are arranged in a peripheral ( ⁇ 30 ⁇ m, 85 ⁇ m pitch). 280 pins). On the semiconductor substrate, a 200 ⁇ m square mark is formed as an alignment mark.
  • Example 1 In this case, in Examples 1, 2, and 3, one conductive particle 11 is disposed per one end electrode of the through hole 4 as shown in FIG. 10, and in Example 4, insulation is performed as shown in FIG.
  • the adhesive layer 12 is divided into two layers, and the conductive particles 11 are arranged on each adhesive layer 12 so that two conductive particles are arranged in the film thickness direction per one place of the end electrode of the through hole 4
  • Example 5 two conductive particles 11 are arranged side by side in the film surface direction as shown in FIG. 12 per one end electrode of the through hole 4, and in Example 6, 1 of the end electrode of the through hole 4 is arranged.
  • Nine conductive particles per place were arranged side by side in the film surface direction as shown in FIG.
  • the alignment mark was formed of conductive particles. In this case, the outline of the arrangement of the conductive particles was made to substantially coincide with the outline of the alignment mark of the semiconductor substrate 3.
  • a nickel plate having a thickness of 2 mm is prepared, and the protrusions (diameter 30 to 45 ⁇ m, height 25 ⁇ m to 40 ⁇ m.
  • the diameter 45 ⁇ m and height 40 ⁇ m) are arranged on the conductive particles described above.
  • a transfer master was produced by patterning so that Also, 50 parts by mass of phenoxy resin (YP-50, Nippon Steel & Sumikin Chemical Co., Ltd.), 30 parts by mass of a microencapsulated imidazole compound latent curing agent (Novacure HX3941HP, Asahi Kasei E-Materials Co., Ltd.), and fumed silica ( A binder mixed with 20 parts by mass of Aerosil RY200 and Nippon Aerosil Co., Ltd. was applied on a PET (polyethylene terephthalate) film so that the dry thickness was 50 ⁇ m, and this binder was superimposed on the above-mentioned transfer master, After drying at 80 ° C. for 5 minutes, a transfer mold having recesses was prepared by irradiating with 1000 mJ light with a high-pressure mercury lamp.
  • phenoxy resin YP-50, Nippon Steel & Sumikin Chemical Co., Ltd.
  • phenoxy resin YP-50, Nippon Steel & Sumikin Chemical Co., Ltd.
  • epoxy resin jER828, Mitsubishi Chemical Corporation
  • cationic curing agent SI-60L, Sanshin Chemical Industry Co., Ltd.
  • the transfer mold having the above-mentioned concave portions was filled with conductive particles, and the above-mentioned insulating resin adhesive layer was covered thereon, and ultraviolet rays were irradiated to cure the curable resin contained in the insulating resin. Then, the insulating resin was peeled from the mold and pushed in such a way that the ends of the conductive particles were aligned with the interface, whereby the anisotropic conductive films of Examples 1 to 3 were manufactured.
  • the thickness of the pressure-sensitive adhesive layer was changed to 25 ⁇ m, the same was peeled off from the mold, and the peeled pieces were laminated at 60 ° C.
  • the insulating adhesive layer had two layers of anisotropic conductive film Manufactured.
  • the thickness of the pressure-sensitive adhesive layer was changed to 15 ⁇ m, and the insulating resin layer (thickness 15 ⁇ m) prepared in the same manner as the pressure-sensitive adhesive layer was peeled off from the mold in the same manner.
  • An anisotropic conductive film was manufactured by laminating on the conductive particle side of the layer.
  • the anisotropic conductive film of Comparative Example 1 in which the conductive particles are randomly dispersed is obtained by stirring the conductive particles and the insulating resin with a rotation / revolution mixer (Sinky Co., Ltd.). Obtained and produced by forming a coating film of the dispersion at 30 ⁇ m.
  • the multilayer substrate of Comparative Example 1 had many through holes that caused poor filling, whereas the multilayer substrates of Examples 1 to 6 all had good filling, and the through holes were connected by conductive particles. I was able to confirm that it was possible. In particular, in Example 6, the allowable width of the positional deviation between the arrangement of the through holes and the conductive particles was large.

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Abstract

　内表面にメッキ膜が形成された貫通孔（以下、スルーホールという）を有する半導体基板が積層されている多層基板であって、導通特性に優れ、かつ低コストに製造できる多層基板が提供される。多層基板の平面視には、スルーホールが対向する位置に導電粒子が選択的に存在する。多層基板は、対向するスルーホールが導電粒子により接続され、該スルーホールが形成されている半導体基板同士が絶縁接着剤により接着している接続構造を有する。

Description

多層基板
　本発明は、多層基板に関する。
　ＩＣの高密度実装分野では、ＩＣ等の電子部品が組み込まれた半導体基板を積層した多層基板が使用されている。
　多層基板の製造方法としては、バンプを有する貫通電極を個々の半導体基板に形成し、対向する半導体基板の貫通電極同士をバンプのリフローにより接続する方法（特許文献１）や対向する半導体基板の間に、絶縁接着剤層中に導電粒子が分散している異方導電性フィルムを挟み、加熱加圧して貫通電極同士を接続する方法（特許文献２）がある。
　この場合、図１４に示したように、貫通電極６は、一般に（ａ）半導体基板３に（ｂ）貫通孔４ｈを形成し、（ｃ）無電解メッキによりメッキ膜４ａを形成し、それをパターニングして貫通孔４ｈの内部にメッキ膜４ａを残すことでスルーホールを形成し、（ｄ）さらに所定のパターンにマスクを設けて電解メッキを行うことでスルーホール内に金属５を充填することにより形成される。
特開２０１０－２７２７３７号公報 特開平８－３３０７３６号公報
　しかしながら、個々の半導体基板の貫通電極にバンプを形成し、対向する半導体基板の貫通電極をハンダのリフローにより接続し、半導体基板を積層していく方法は製造工程が煩雑である。
　対向する貫通電極を、異方導電性フィルムを使用して接続し、半導体基板を積層していく方法では、多層基板の製造工程をある程度簡略化することができるが、異方導電性フィルムが絶縁接着剤層に導電粒子をランダムに分散させたものであるため、対向する半導体基板の貫通電極間に異方導電性フィルムの導電粒子が十分に挟まれない場合があることにより導通特性がばらつくという問題がある。一方で、貫通電極の接続に寄与しない導電粒子が、対向する半導体基板間に多数存在することにより無用な導電粒子にコストがかかるという問題もある。
　そこで、本発明は、異方導電性フィルムを用いて半導体基板を積層し、導通特性に優れた多層基板を簡便な製造工程で低コストに提供することを課題とする。
　本発明者は、異方導電性フィルムを用いて半導体基板を積層し多層基板を製造するにあたり、貫通電極の形成の前段で形成するスルーホールに対して異方導電性フィルムの絶縁接着剤中の導電粒子を選択的に配置し、かかる異方導電性フィルムを用いて、対向する半導体基板のスルーホールを接続すると、対向するスルーホールを導電粒子で確実に接続することができ、また、接続に寄与しない導電粒子数を低減させ、多層基板の製造工程も顕著に簡略化し、多層基板の製造コストを下げられることを見出し、本発明を想到した。
　即ち、本発明は、スルーホールを有する半導体基板が積層されている多層基板であって、多層基板の平面視において、スルーホールが対向する位置に導電粒子が選択的に存在し、
対向するスルーホールが導電粒子により接続され、該スルーホールが形成されている半導体基板同士が絶縁接着剤により接着している接続構造を有する多層基板を提供する。
　特に、この多層基板として、スルーホールを有する第１半導体基板と、スルーホールを有する第２半導体基板とが積層されている多層基板であって、
第１半導体基板のスルーホールと第２半導体基板のスルーホールが対向し、それらの間に選択的に配置された導電粒子により接続され、
第１半導体基板と第２半導体基板が絶縁接着剤により接着している接続構造を有する多層基板を提供する。
　また、本発明は、半導体基板に形成されたスルーホール同士を対向させて接合する多層基板の製造方法であって、スルーホールが対向する部分の多層基板の平面視における位置に対応して導電粒子が絶縁接着剤層に選択的に配置された異方導電性フィルムを、スルーホールを有する半導体基板同士の間に挟み、該異方導電性フィルムを加熱加圧することによりこれら半導体基板を異方導電性接続する多層基板の製造方法を提供する。
　特に、この多層基板の製造方法として、スルーホールを有する第１半導体基板と、スルーホールを有する第２半導体基板を、それらのスルーホール同士を対向させて接合する多層基板の製造方法であって、第１半導体基板と第２半導体基板との間に、スルーホールの配置に対応して導電粒子が絶縁接着剤層に選択的に配置された異方導電性フィルムを挟み、該異方導電性フィルムを加熱加圧することにより第１半導体基板と第２半導体基板を異方導電性接続する多層基板の製造方法を提供する。
　さらに、本発明は上述の多層基板の製造方法に使用する異方導電性フィルムとして、異方導電性フィルムで接続するスルーホールの配置に対応して導電粒子が絶縁接着剤層に選択的に配置されている異方導電性フィルムを提供する。
　また、上述の多層基板の製造方法に有用な異方導電性フィルムとして、絶縁接着剤層と、該絶縁接着剤層に配置された導電粒子を含む異方導電性フィルムであって、２個以上の導電粒子が近接している導電粒子ユニットが形成されており、導電粒子ユニットに、少なくとも大きさ又は種類が異なる複数の導電粒子が含まれている異方導電性フィルムを提供する。
　本発明の多層基板によれば、半導体基板のスルーホール同士が導電粒子により確実に接続されているので導通特性が安定する。
　また、半導体基板に、スルーホール内に金属を充填して貫通電極を形成することなく、スルーホール同士を導電粒子で接続し、かつ、接続に寄与しない導電粒子が半導体基板間で低減しているので多層基板の製造コストが顕著に抑制される。また、同様の理由で、計装工数の削減にも効果がある。
　さらに、本発明の多層基板は、特定の異方導電性フィルムの使用により簡便な工程で製造することができる。
　特に半導体基板が３つ以上積層されている多層基板の場合に、積層する半導体基板間に、共通する異方導電性フィルムを使用すると、多層基板のトータルの製造コストを大きく削減することができる。したがって、本発明の多層基板をより一層低価格で提供することが可能となる。
図１は、本発明の一実施態様の多層基板１Ａの断面図である。 図２は、本発明の一実施態様の多層基板１Ｂの断面図である。 図３Ａは、多層基板１Ｂの製造工程の説明図である。 図３Ｂは、多層基板１Ｂの製造工程の説明図である。 図３Ｃは、多層基板１Ｂの製造工程の説明図である。 図３Ｄは、多層基板１Ｂの製造工程の説明図である。 図４Ａは、異方導電性接続前の、スルーホールに対する導電粒子の配置の説明図である。 図４Ｂは、異方導電性接続後の、スルーホールに対する導電粒子の配置の説明図である。 図５Ａは、異方導電性接続前の、スルーホールに対する導電粒子の配置の説明図である。 図５Ｂは、異方導電性接続後の、スルーホールに対する導電粒子の配置の説明図である。 図６Ａは、異方導電性接続前の、スルーホールに対する導電粒子の配置の説明図である。 図６Ｂは、異方導電性接続後の、スルーホールに対する導電粒子の配置の説明図である。 図７Ａは、異方導電性接続前の、スルーホールに対する導電粒子の配置の説明図である。 図７Ｂは、異方導電性接続後の、スルーホールに対する導電粒子の配置の説明図である。 図８は、異方導電性接続前の、スルーホールに対する導電粒子の配置の説明図である。 図９は、本発明の一実施態様の多層基板１Ｃの断面図である。 図１０は、実施例１の多層基板の製造に使用した半導体基板の表面における電極と導電粒子の配置図である。 図１１は、実施例４の多層基板の製造に使用した半導体基板の表面における電極と導電粒子の配置図である。 図１２は、実施例５の多層基板の製造に使用した半導体基板の表面における電極と導電粒子の配置図である。 図１３は、実施例６の多層基板の製造に使用した半導体基板の表面における電極と導電粒子の配置図である。 図１４は、貫通電極の製造方法の工程説明図である。
　以下、図面を参照しつつ本発明を詳細に説明する。なお、各図中、同一符号は、同一又は同等の構成要素を表している。
＜多層基板における接続構造＞
　図１は、本発明の一実施態様の多層基板１Ａの断面図である。
　この多層基板１Ａは、配線基板２に３層の半導体基板３Ａ、３Ｂ、３Ｃが積層されたものであり、各半導体基板３Ａ、３Ｂ、３Ｃは、ＩＣ等の半導体部品が形成された半導体ウエハである。また、配線基板２にはスルーホール４Ｘが形成され、各半導体基板３Ａ、３Ｂ、３Ｃにはスルーホール４Ａ、４Ｂ、４Ｃが形成され、配線基板２の表面でスルーホール４Ｘが露出する部分や、スルーホール４Ａ、４Ｂ、４Ｃが半導体基板の表面に露出する部分には、それぞれ電極パッド９が形成されている。なお、本発明において半導体基板３Ａ、３Ｂ、３Ｃとしては、半導体チップを使用してもよい。また、本発明において、多層基板を構成する半導体基板の積層数に特に制限はない。
　多層基板１Ａには、第１半導体基板３Ａのスルーホール４Ａと第２半導体基板３Ｂのスルーホール４Ｂが対向し、それらの間に選択的に配置された導電粒子１１により電気的に接続されている接続構造がある。この接続構造において、スルーホール４Ａ、４Ｂの対向する間に導電粒子１１が選択的に配置されたとは、導電粒子１１が平面視にてもっぱらスルーホール４Ａ、４Ｂの対向面又はその近傍に存在し、スルーホール４Ａ、４Ｂに１個以上の導電粒子１１が捕捉されるように配置されていることをいう。１～十数個捕捉されるように配置されていることが、コストと性能の両立の上では好ましい。フィルム厚方向には複数の導電粒子が重畳していてもよい。また、スルーホール４Ａ、４Ｂの対向面に複数の導電粒子１１が存在する場合に、その導電粒子の大きさ、種類等が異なっていてもよい。なお、スルーホール４Ａ、４Ｂの対向面に複数の導電粒子１１を配置する場合に、半導体基板３Ａ、３Ｂと導電粒子１１との位置合わせの精度を緩和することができる。
　第１半導体基板３Ａと第２半導体基板３Ｂの対向面同士は絶縁接着剤１２により接着されている。絶縁接着剤１２は、後述する異方導電性フィルムの絶縁接着剤層から形成される。
　また、第１半導体基板３Ａのスルーホール４Ａと接続した第２半導体基板３Ｂのスルーホール４Ｂは、第３半導体基板３Ｃ側において、第３半導体基板３Ｃのスルーホール４Ｃとも対向しており、それらの間に選択的に配置された導電粒子１１により第２半導体基板３Ｂのスルーホール４Ｂと第３半導体基板３Ｃのスルーホール４Ｃとが電気的に接続されている。この第２半導体基板３Ｂと第３半導体基板３Ｃの対向面同士も絶縁接着剤１２により接着されている。また、配線基板２のスルーホール４Ｘと第１半導体基板３Ａのスルーホール４Ａも導電粒子１１により同様に接続されている。このように、多層基板１Ａは、配線基板２のスルーホール４Ｘと、３層の半導体基板のスルーホール４Ａ、４Ｂ、４Ｃが多層基板の積層方向に直線状に繋がった接続構造を有する。この各層のスルーホールが直線状に繋がった接続構造によれば電気伝送の経路が短くなるので、伝送速度を向上させることができる。
　なお、多層基板１Ａは、後述するように多層基板を構成する各層を、導電粒子が特定の配置を有する本発明の異方導電性フィルムを用いて接続することにより製造される。その場合、第１半導体基板３Ａと第２半導体基板３Ｂの間には、対向するスルーホール４Ａ、４Ｂに捕捉されていない導電粒子１１が存在するとしても、そのような導電粒子１１の数は、第１半導体基板と第２半導体基板の間に存在する導電粒子の総数の好ましくは５％以下、より好ましくは０．５％以下、特に導電粒子１１の略すべてがスルーホール４Ａ、４Ｂで捕捉されているようにする。多層基板１Ａを構成するその他の半導体基板間においても同様である。このようにスルーホール４Ａ、４Ｂ、４Ｃの接続に寄与しない導電粒子１１を低減させることにより、性能をシミュレーション解析しやすくなり、改善工数を削減することができる。
＜配線基板＞
　ここで、多層基板１Ａを構成する配線基板２としては、ＦＲ４等のガラスエポキシ基板等を使用することができる。配線基板２として、ＩＣチップもしくはＩＣ形成用のシリコンウェーハーを用いてもよい。配線基板２は、多層基板１Ａの用途等に応じて適宜選択される。
　また、配線基板２の電極部分には、必要に応じてハンダボール８を設けてもよい。
＜半導体基板＞
　半導体基板３Ａ、３Ｂ、３Ｃとしては、スルーホール４Ａ、４Ｂ、４Ｃを有するものであれば特に制限は無く、例えば、シリコン等一般的半導体材料等を使用することができる。
　スルーホール４Ａ、４Ｂ、４Ｃの仕様は適宜設定できる。例えば、スルーホール４Ａ、４Ｂ、４Ｃは、電極パッド９を備えていることが好ましい。また、半導体基板３Ａ、３Ｂ、３Ｃを積層した場合に、各半導体基板３Ａ、３Ｂ、３Ｃのスルーホール４Ａ、４Ｂ、４Ｃが多層基板１Ａの厚み方向に少なくとも２層の半導体基板にわたって直線状に繋がるように、好ましくは多層基板１Ａの表裏に渡って直線状に繋がるように、スルーホール４Ａ、４Ｂ、４Ｃが配置されるものが好ましい。
＜搭載部品＞
　本発明の多層基板には、必要に応じて種々の部品を搭載することができる。
　例えば図２に示す多層基板１Ｂは、各層のスルーホール４Ｘ、４Ａ、４Ｂ、４Ｃが直線状に繋がった接続構造を有し、最外層にはスルーホール４Ｃに接続した放熱用のヒートシンク７を有する。したがって、多層基板１Ｂは、配線基板２や半導体基板３Ａ、３Ｂ、３Ｃに形成されたＩＣ等の電子部品等から放出される熱をヒートシンク７により効率的に放熱することが可能となる。
＜多層基板の製造方法＞
　本発明の多層基板の製造方法としては、例えば、図２の多層基板１Ｂの場合、まず、図３Ａに示すように、スルーホール４Ｘを有する配線基板２とスルーホール４Ａを有する半導体基板３Ａとの間に、接続すべきスルーホール４Ｘ、４Ａの配置に対応して導電粒子１１が絶縁接着剤層１２に選択的に配置された本発明の異方導電性フィルム１０Ａを挟み、異方導電性フィルム１０Ａを加熱加圧することにより配線基板２と第１半導体基板３Ａを異方導電性接続し、図３Ｂに示す２層の接続構造体を得る。より具体的には、配線基板２と異方導電性フィルム１０Ａを、接続すべきスルーホール４Ｘと導電粒子１１の配置が合うように位置合わせして重ね、さらに第１半導体基板３Ａも同様に位置合わせして重ね合わせ、加熱加圧してこれらを異方導電性接続する。この位置合わせは、異方性導電フィルムのスルーホールに対応する導電粒子（後述するように粒子群が形成されている場合には、その粒子群を構成する導電粒子）と、スルーホールとをＣＣＤなどを用いて観測し、それらを重ね合わせることにより行ってもよい。
　同様にして、図３Ｃに示すように、第１半導体基板３Ａと異方導電性フィルム１０Ｂを位置合わせして重ね、その上に第２半導体基板３Ｂを位置合わせして重ね、加熱加圧して異方導電性接続し、図３Ｄに示す３層の接続構造を得る。さらに同様にして第２半導体基板３Ｂの上に異方導電性フィルムと第３半導体基板３Ｃを位置合わせして重ね、加熱加圧する。
　なお、異方導電性フィルムを用いて配線基板と半導体基板を接続する場合、あるいは、半導体基板同士を接続する場合に、まず、一方の基板と異方導電性フィルムを位置合わせして重ね、加熱加圧して異方導電性フィルムの導電粒子をその基板のスルーホールと接合することにより導電粒子をスルーホール内に進入させ、次に対向する基板を重ね合わせ、その基板を、先の基板のスルーホール及び導電粒子と接合することができる。
　その後、第３半導体基板３Ｃ上にヒートシンク７を熱伝導性テープ等により接続し、配線基板２の電極パッド９にハンダボール８を形成し、常法により多層基板１Ｂを得る。あるいは、ハンダボール８に代えて導電粒子を設けてもよい。
　なお、配線基板２又は半導体基板３Ａ、３Ｂ、３Ｃと異方導電性フィルム１０Ａ、１０Ｂとの位置合わせの方法としては、配線基板２、半導体基板３Ａ、３Ｂ、３Ｃ及び異方導電性フィルム１０Ａ、１０Ｂに、それぞれアライメントマークをつけておき、それらのアライメントマークを合わせることにより位置合わせを行うこともできる。
　即ち、従来、半導体基板を積層して多層基板を製造する場合、半導体基板には一例として数十μｍ～数百μｍの大きさのアライメントマークが形成され、ＣＣＤ又はレーザーを用いて半導体基板同士の位置合わせが行われている。一方、異方導電性フィルムには導電粒子が単分散又は格子状に配置されているため異方導電性フィルムにアライメントマークはつけられていない。これに対し、本発明で使用する異方導電性フィルムは、接続すべきスルーホールの配置に対応して導電粒子１１が絶縁接着剤層１２に選択的に配置されたものであるから、導電粒子１１の配置をアライメントマークの代替とすることができる。このような導電粒子の配置も含めて異方導電性フィルムには、何らかのアライメントマークを設けることが好ましい。
＜異方導電性フィルム＞
　本発明の多層基板の製造方法に使用する本発明の異方導電性フィルムは、接続すべきスルーホールの配置に対応して導電粒子１１が絶縁接着剤層１２に選択的に配置され、好ましくはアライメントマークが形成されたものである。アライメントマークとしては、導電粒子の配置により形成したものが好ましい。これにより、アライメントマークを明確に検出することができ、かつ異方導電性フィルムにアライメントマークをつけるための新たな工程の追加が不要となる。一方、アライメントマークは、レーザー照射などで絶縁接着剤層１２を部分的に硬化させることにより形成してもよい。これによりアライメントマークを付する位置の変更が容易となる。
　このような異方導電性フィルムの製造方法としては、導電粒子１１の配置に対応した凸部を有する金型を、金属プレートに機械加工、レーザー加工、フォトリソグラフィなどの公知の加工方法を行うことで作製し、その金型に硬化性樹脂を充填し、硬化させることにより凹凸が反転した樹脂型を製造し、その樹脂型の凹部に導電粒子を入れ、その上に絶縁接着剤層形成用組成物を充填し、硬化させ、型から取り出せばよい。
　また、絶縁接着剤層１２に導電粒子１１を特定の配置におくために、絶縁接着剤層形成組成物層の上に、貫通孔が所定の配置で形成されている部材を設け、その上から導電粒子１１を供給し、貫通孔を通過させるなどの方法でもよい。
＜異方導電性フィルムを形成する導電粒子＞
　異方導電性フィルム１０に使用する導電粒子１１としては、公知の異方導電性フィルムに用いられているものの中から適宜選択して使用することができる。例えば、ハンダ、ニッケル、コバルト、銀、銅、金、パラジウムなどの金属粒子、金属被覆樹脂粒子などが挙げられる。金属被覆樹脂粒子の金属被覆は、無電解メッキ法、スパッタリング法等の公知の金属膜形成方法を利用して形成することができる。金属被覆は、コア樹脂材の表面に形成されていれば特に制限はない。コア樹脂材は、樹脂のみから形成してもよく、導通信頼性の向上のために導電微粒子を含有させたものとしてもよい。
　導電粒子としては、上述した粒子のうち、導通信頼性とコストの点でハンダ粒子を使用することが好ましい。一方、後工程でリフロー工程が不要の場合等においては、金属被覆樹脂粒子を使用することが好ましい。本発明ではスルーホール同士の接続や半導体基板同士の接着を、絶縁性接着剤層に導電粒子が配置されている異方導電性フィルムの加熱加圧により行うため、導電粒子として金属被覆樹脂粒子を使用すると、加熱加圧を低温化することが可能になり、絶縁性接着剤の材料選択の幅が広がるためである。
　また、導電粒子としては、大きさ、種類等が異なる２種以上の粒子を併用することもできる。
＜異方導電性フィルムにおける導電粒子の配置＞
　異方導電性フィルムにおいて、導電粒子１１の配置、粒子径及び種類は、スルーホール同士の接合の安定性の点からスルーホールの開口径等に応じて適宜選択される。
　例えば、図３Ｃ、図３Ｄに示したように、スルーホール４Ａ、４Ｂの対向部位に１個の導電粒子１１を配置する場合、導電粒子１１の粒子径は、通常、スルーホール４Ａ、４Ｘの開口径よりも大きくすることが好ましい。導電粒子１１がハンダ粒子から形成されている場合には、図４Ａ、図４Ｂに示すように、異方導電性接続時の加熱加圧により溶融したハンダ粒子でスルーホールのメッキ膜４ａが濡れやすいが、この場合も導電粒子１１の粒子径をスルーホール４Ａ、４Ｂの開口径以上にすることが好ましい。これにより、スルーホール４Ａ、４Ｂで導電粒子１１が押圧され、スルーホール４Ａ、４Ｂを導電粒子１１で確実に接続することができる。
　また、導電粒子の粒子径がスルーホールの開口径よりも小さい場合には、図５Ａに示す異方導電性フィルム１０のように、複数の導電粒子１１を隣接させた粒子群１１ａの径をスルーホール４Ａ、４Ｂの開口径よりも大きくし、図５Ｂに示すように、対向するスルーホール４Ａ、４Ｂが導電粒子１１で確実に接続されるようにすることが好ましい。複数の導電粒子からなる粒子群１１ａで、スルーホール４Ａ、４Ｂを接続することにより、一つずつの導電粒子で接続する場合に比して、接続後の導通抵抗をロバスト化させることもできる。
　図６Ａに示す異方導電性フィルム１０のように、複数の導電粒子１１からなる粒子群１１ａが、異方導電性フィルム１０の厚み方向に重畳するように配置してもよい。これにより、図６Ｂに示すように、スルーホール４Ａ、４Ｂのより深い位置まで導電粒子１１を進入させることができる。
　スルーホールに対応させて複数の導電粒子１１を隣接させた粒子群を形成する場合に、複数個の導電粒子は、大きさや種類が異なっていても良い。例えば、図７Ａに示す異方導電性フィルム１０のように、大径の導電粒子１１ｐをスルーホール４Ａ、４Ｂに対向させ、小径の導電粒子１１ｑを大径の導電粒子１１ｐの周りで電極パッドに捕捉される位置に配置する。この場合に、大径の導電粒子１１ｐは小径の導電粒子１１ｑよりも変形しやすいものが好ましい。この異方導電性フィルム１０を介して半導体基板３Ａ、３Ｂを加熱加圧することにより、図７Ｂに示す接続構造のように、大径の導電粒子１１ｐをスルーホール４Ａ、４Ｂ間に挟持させ、小径の導電粒子１１ｑでスルーホール４Ａ、４Ｂと大径の導電粒子１１ｐとの間隙を埋めることができ、スルーホール４Ａ、４Ｂと導電粒子との導通性を向上させることができる。また、粒子群１１ａにおいて、導電粒子同士を接触させておくことにより、スルーホール４Ａ、４Ｂと導電粒子とが接触し易くなる。
　図７Ｂの接続構造を得るために、図８に示すように、予め大径の導電粒子１１ｐを有する異方導電性フィルム１０ｐを一方の半導体基板３Ａと仮接着し、小径の導電粒子１１ｑを有する異方導電性フィルム１０ｑを他方の半導体基板３Ｂと仮接着し、その後半導体基板３Ａ、３Ｂを加熱加圧してもよい。
　また、図７Ａに示したように、異方導電性フィルムにおいて、導電粒子は絶縁接着剤層１２から露出していてもよく、特に、スルーホール４Ａ、４Ｂに挟持させる大径の導電粒子１１ｐは露出させることが好ましい。導電粒子を絶縁接着剤層から露出させることにより、導電粒子とスルーホールとのアライメントが容易となり、また、導電粒子とスルーホールとの間に絶縁接着剤層１２が介在しないことにより、導電粒子とスルーホールとの導通性が向上する。
　なお、異方導電性フィルムの導電粒子の露出面は、セパレータフィルムでカバーするなどにより保護しておき、異方導電性フィルムの使用時に導電粒子を露出させるようにしてもよい。
＜絶縁接着剤層＞
　異方導電性フィルムを形成する絶縁接着剤層１２としては、公知の異方導電性フィルムで使用される絶縁性樹脂層を適宜採用することができる。例えば、アクリレート化合物と光ラジカル重合開始剤とを含む光ラジカル重合型樹脂層、アクリレート化合物と熱ラジカル重合開始剤とを含む熱ラジカル重合型樹脂層、エポキシ化合物と熱カチオン重合開始剤とを含む熱カチオン重合型樹脂層、エポキシ化合物と熱アニオン重合開始剤とを含む熱アニオン重合型樹脂層等を使用することができる。また、これらの樹脂層は、必要に応じて、それぞれ重合したものとすることができる。また、絶縁接着剤層１２を、複数の樹脂層から形成してもよい。
　ただし、多層基板１Ａからチップが切り出される等の用途により、多層基板１Ａの製造後に多層基板１Ａが切断される場合には、絶縁接着剤層１２は切断に耐える柔軟性と接着性を有することが好ましい。
　また、絶縁接着剤層１２には、必要に応じてシリカ微粒子、アルミナ、水酸化アルミ等の絶縁性フィラーを加えても良い。絶縁性フィラーの配合量は、絶縁接着剤層を形成する樹脂１００質量部に対して３～４０質量部とすることが好ましい。これにより、異方導電性接続時に絶縁接着剤層１２が溶融しても、溶融した樹脂で導電粒子１１が不用に移動することを抑制することができる。
　また、絶縁接着剤層１２には、必要に応じてスルーホールへの充填可能な粒子径の絶縁性スペーサーを加えても良い。これにより、異方導電性接続時の押込の均一性が確保しやすくなる。
　異方導電性接続の前に、導電粒子近傍の絶縁接着剤層の樹脂の一部を予め重合させてもよい。これにより、スルーホールと導電粒子とのアライメントが容易となり、ショートの発生リスクを低減させることができる。
＜変形態様＞
　上述した異方導電性フィルム１０では、所定の位置以外に存在する導電粒子はほとんど存在しない。一方、所定の位置に存在しても対向するスルーホール４Ａ、４Ｂに捕捉されない導電粒子は存在しえる。したがって、この異方導電性フィルム１０を半導体基板３Ａ、３Ｂの接続に使用した後において、対向する半導体基板３Ａ、３Ｂの間で、スルーホール４Ａ、４Ｂに捕捉されていない導電粒子１１の数は、対向する半導体基板３Ａ、３Ｂの間に存在する導電粒子１１の総数の好ましくは５％以下となる。
　一方、図９に示す多層基板１Ｃは、図１に示した多層基板１Ａにおいて、配線基板２のスルーホール４Ｘと第１半導体基板３Ａのスルーホール４Ａとを接続する異方導電性フィルムと、第１半導体基板３Ａのスルーホール４Ａと第２半導体基板３Ｂのスルーホール４Ｂとを接続する異方導電性フィルムと、第２半導体基板３Ｂのスルーホール４Ｂと第３半導体基板３Ｃのスルーホール４Ｃとを接続する異方導電性フィルムとして、共通する異方導電性フィルムを使用することにより製造したものである。即ち、異方導電性フィルムとして、製造しようとする多層基板１Ｃの平面視において、配線基板２又は各半導体基板３Ａ、３Ｂ、３Ｃのスルーホール同士が対向する部分に対応して導電粒子１１が絶縁接着剤層１２に選択的に配置されたものが使用される。これにより、多層基板１Ｃの平面視において、スルーホール４Ｘ、４Ａ、４Ｂ、４Ｃが対向する部分に導電粒子１１、１１ｘが存在することになる。言い換えると、対向するスルーホールの間には、必ずしも該スルーホールのみに対して選択的に配置された導電粒子が存在するわけではない。例えば、半導体基板３Ａと半導体基板３Ｂとの間には、これらに形成されているスルーホール４Ａ、４Ｂが対向する位置に導電粒子１１が選択的に配置されている他、半導体基板３Ａのスルーホール４Ａと半導体基板のスルーホール４Ｂとの接続には寄与しない導電粒子１１ｘも存在する。よって、半導体基板３Ａと半導体基板３Ｂとの間に存在する全導電粒子に対し、半導体基板３Ａと半導体基板３Ｂとの間でスルーホールに捕捉されない導電粒子が５％を超えて存在し得る。しかし、半導体基板３Ａと半導体基板３Ｂの間にあってこれらの接続に寄与していない導電粒子１１ｘは、配線基板２のスルーホール４Ｘと第１半導体基板３Ａのスルーホール４Ａとの接続に寄与している。また、多層基板１Ｃの平面視において、スルーホール同士が対向しない位置には、導電粒子は配置されていない、あるいは実質的に存在していない。
　このように各半導体基板を、共通する異方導電性フィルムを用いて接続すると、多層基板の製造に要するトータルコストを削減することができる。また、多層基板のラインアップの増加（仕様変更）にも容易に対応することができる。なお、この異方導電性フィルムにおいても、導電粒子を、複数の導電粒子が近接した粒子群として配置することができる。
　また、各半導体基板を、共通する異方導電性フィルムを用いて接続することにより多層基板の製造に要するトータルコストを削減する場合に、粒子群１１ａが一面に配置されている異方導電性フィルムを使用して多層基板を製造してもよい。この場合、各粒子群１１ａを構成する導電粒子数は３個以上、好ましくは１０個以上、より好ましくは１２個以上とする。粒子群１１ａ同士の間隔は、ショートの発生を回避するため、導電粒子径の１倍以上とし、半導体基板のスルーホール間隔に応じて適宜定める。接続する半導体基板ごとに、導電粒子の配置が異なる異方導電性フィルムを使用する場合に比して、粒子群１１ａが適当な間隔で一面に配置されている異方導電性フィルムを共通して用いることにより、多層基板の製造コストを大きく低減させることができる。
　各半導体基板に共通して使用する異方導電性フィルムにおいて、粒子群を構成する複数の導電粒子の配置、粒子径及び種類は、前述のようにスルーホール同士の接合の安定性の点から適宜選択され、一つの粒子群に、少なくとも大きさ又は種類が異なる複数の導電粒子が含まれていてもよく、一つの粒子群で複数の導電粒子が異方導電性フィルムのフィルム厚方向に重畳していてもよく、一つの粒子群で複数の導電粒子が異方導電性フィルムの面方向に配置されていてもよく、粒子群に含まれる導電粒子の少なくとも一部が絶縁接着剤層から露出していてもよい。
　以上のように、本発明の多層基板では、多層基板の平面視において、スルーホールが対向する位置に導電粒子が選択的に存在する。そして、そのように配置された導電粒子により、対向するスルーホールが接続され、該スルーホールが形成されている半導体基板同士が絶縁接着剤により接着している。この場合に、対向するスルーホールは、該対向するスルーホールの間のみに選択的に配置された導電粒子１１により接続されていてもよく、また、対向するスルーホールが形成されている半導体基板３Ａ、３Ｂ、３Ｃ間に、該対向するスルーホールの接続に寄与しない導電粒子１１ｘが含まれていてもよい。
　本発明の多層基板は、高密度半導体パッケージ等を初めとして、高密実装が要求される各種半導体等の種々の用途に使用することができる。また、多層基板を所定のサイズにカットして使用してもよい。
　以下、実施例により本発明を具体的に説明する。
　実施例１～６、比較例１
（１）半導体基板
　多層基板を構成する半導体基板３として、外形が７ｍｍ□、厚み１００μｍの矩形で、図７に示すように、クロム製電極パッドを有するスルーホール４がペリフェラル配置（φ３０μｍ、８５μｍピッチ、２８０ピン）に形成されているものを用意した。
　半導体基板には、アライメントマークとして２００μm□の四角形マークが形成されている。
（２）異方導電性フィルムの製造
　表１に示すように、表１に示す粒子径の導電粒子（微粉半田粉、三井金属鉱業（株））を、絶縁接着剤層にランダムに分散させるか（比較例１、粒子密度６０個／ｍｍ2）、又は半導体基板のスルーホール４の配置に対応させて配置した（実施例１～６、８５μｍピッチ、２８０箇所）異方導電性フィルムを製造した。
　この場合、実施例１、２、３では、図１０に示すようにスルーホール４の端部電極１箇所あたり１個の導電粒子１１を配置し、実施例４では、図１１に示すように絶縁接着剤層１２を２層とし、各接着剤層１２に導電粒子１１を配置することにより、スルーホール４の端部電極の１箇所あたり２個の導電粒子をフィルム厚方向に並べて配置し、実施例５では、スルーホール４の端部電極の１箇所あたり２個の導電粒子１１を図１２に示すようにフィルム面方向に並べて配置し、実施例６では、スルーホール４の端部電極の１箇所あたり９個の導電粒子を図１３に示すようにフィルム面方向に並べて配置した。
　また、実施例１～６では、アライメントマークを導電粒子により形成した。この場合、導電粒子の配列の輪郭が半導体基板３のアライメントマークの輪郭と略一致するようにした。
　より具体的には、厚さ２ｍｍのニッケルプレートを用意し、凸部（径３０～４５μｍ、高さ２５μｍ～４０μｍ。例えば、実施例１では径４５μｍ、高さ４０μｍ）が上述の導電粒子の配置となるようにパターニングして転写原盤を作製した。また、フェノキシ樹脂（ＹＰ－５０、新日鉄住金化学（株））５０質量部、マイクロカプセル化イミダゾール化合物潜在性硬化剤（ノバキュアＨＸ３９４１ＨＰ、旭化成イーマテリアルズ（株））３０質量部、及びヒュームドシリカ（アエロジルＲＹ２００、日本アエロジル（株））２０質量部を混合したバインダーを、乾燥厚みが５０μｍとなるようにＰＥＴ（ポリエチレンテレフタレート）フィルム上に塗布し、このバインダーを上述の転写原盤に向けて重ね合わせ、８０℃で５分間乾燥後、高圧水銀ランプにて１０００ｍＪ光照射することにより凹部を有する転写型を作成した。
　一方、フェノキシ樹脂（ＹＰ－５０、新日鉄住金化学（株））６０質量部、エポキシ樹脂（ｊＥＲ８２８、三菱化学(株)）４０質量部、カチオン系硬化剤（ＳＩ－６０Ｌ、三新化学工業(株)）２質量部から絶縁接着剤形成用組成物を調製し、それをフィルム厚５０μｍのＰＥＴフィルム上に塗布し、８０℃のオーブンにて５分間乾燥させ、ＰＥＴフィルム上に絶縁性樹脂からなる粘着層を３０μｍで形成した。
　前述の凹部を有する転写型に導電粒子を充填し、その上に上述の絶縁性樹脂の粘着層を被せ、紫外線を照射して絶縁性樹脂に含まれる硬化性樹脂を硬化させた。そして、型から絶縁性樹脂を剥離し、導電粒子の端部と界面を揃えるように押し込むことで、実施例１～３の異方性導電フィルムを製造した。実施例４では粘着層の厚みを２５μｍに変更し、同様に型から剥離し、剥離したもの同士を６０℃、０．５ＭＰａで積層することで絶縁接着剤層が２層の異方性導電フィルムを製造した。実施例５、６では粘着層の厚みを１５μｍに変更し、同様に型から剥離し、その上に粘着層と同様に作製した絶縁性樹脂層（厚み１５μｍ）を６０℃、０．５ＭＰａで粘着層の導電粒子側に積層することで異方導電性フィルムを製造した。
　一方、導電粒子がランダムに分散している比較例１の異方導電性フィルムは、導電粒子と絶縁性樹脂を自転公転式混合装置（(株)シンキー）で撹拌して導電粒子の分散物を得、その分散物の塗膜を３０μｍで形成することにより製造した。
（３）多層基板の製造
　（１）で用意した半導体基板を、（２）で製造した異方導電性フィルムを用いて表１に示した積層数で重ね合わせて押圧し、さらに加熱加圧（１８０℃、４０ＭＰａ、２０秒）することにより多層基板を製造した。
（４）評価
　得られた多層基板について、（ａ）充填の評価、（ｂ）溶融の評価、を次のように行った。これらの結果を表１に示す。
（ａ）充填の評価
　半導体基板を重ね合わせ、押圧した状態で、対向するスルーホールの間に導電粒子が存在する場合をＯＫ、存在しない場合をＮＧとした。
（ｂ）溶融の評価
　多層基板の厚さ方向の断面を観察し、対向するスルーホールが導電粒子で接続され、さらにスルーホールの内壁に沿って導電粒子の溶融物が進入している場合をＡ、対向するスルーホールが導電粒子で接続されているが、スルーホールの内壁にそって導電粒子の溶融物が進入していない場合をＢとした。
Figure JPOXMLDOC01-appb-T000001
　比較例１の多層基板には、充填が不良になるスルーホールが多数発生したのに対し、実施例１～６の多層基板は、いずれも充填が良好であり、導電粒子によりスルーホール同士を接続できることが確認できた。特に、実施例６では、スルーホールと導電粒子の配置の位置ズレの許容幅が大きかった。
　１Ａ、１Ｂ　多層基板
　２　　配線基板
　３、３Ａ、３Ｂ、３Ｃ　半導体基板
　４、４Ａ、４Ｂ、４Ｃ　　スルーホール
　４ａ　メッキ膜
　４ｈ　貫通孔
　５　　金属
　６　　貫通電極
　７　　ヒートシンク
　８　　ハンダボール
　９　　電極パッド
１０、１０Ａ、１０Ｂ　　異方導電性フィルム
１１、１１ｐ、１１ｑ　　導電粒子
１１ａ　粒子群
１２　　絶縁接着剤又は絶縁接着剤層
 
 

Claims (14)

  1. 　内表面にメッキ膜が形成された貫通孔（以下、スルーホールという）を有する半導体基板が積層されている多層基板であって、
    多層基板の平面視において、スルーホールが対向する位置に導電粒子が選択的に存在し、
    対向するスルーホールが導電粒子により接続され、該スルーホールが形成されている半導体基板同士が絶縁接着剤により接着している接続構造を有する多層基板。
  2. 　スルーホールを有する第１半導体基板と、スルーホールを有する第２半導体基板とが積層されている多層基板であって、第１半導体基板のスルーホールと第２半導体基板のスルーホールが、それらの間に選択的に配置された導電粒子により接続されている請求項１記載の多層基板。
  3. 　スルーホールを有する第３半導体基板が第２半導体基板に積層されており、
    第１半導体基板のスルーホールと接続している第２半導体基板のスルーホールと第３半導体基板のスルーホールとが対向し、それらの間に選択的に配置された導電粒子により接続され、
    第２半導体基板と第３半導体基板が絶縁接着剤により接着している接続構造を有する請求項２記載の多層基板。
  4. 　スルーホール内に導電粒子が進入している請求項１～３のいずれかに記載の多層基板。
  5. 　多層基板の最外層にヒートシンクを有し、ヒートシンクと、導電粒子で接続されることにより多層基板の積層方向に繋がったスルーホールとが接続している請求項１～４のいずれかに記載の多層基板。
  6. 　半導体基板に形成されたスルーホール同士を対向させて接合する多層基板の製造方法であって、スルーホールが対向する部分の多層基板の平面視における位置に対応して導電粒子が絶縁接着剤層に選択的に配置された異方導電性フィルムを、スルーホールを有する半導体基板同士の間に挟み、該異方導電性フィルムを加熱加圧することによりこれら半導体基板を異方導電性接続する多層基板の製造方法。
  7. 　スルーホールを有する第１半導体基板と、スルーホールを有する第２半導体基板を、それらのスルーホール同士を対向させて接合する多層基板の製造方法であって、第１半導体基板と第２半導体基板との間に、スルーホールの配置に対応して導電粒子が絶縁接着剤層に選択的に配置された異方導電性フィルムを挟み、該異方導電性フィルムを加熱加圧することにより第１半導体基板と第２半導体基板を異方導電性接続する請求項６記載の多層基板の製造方法。
  8. 　スルーホールを有する第３半導体基板を第２半導体基板に積層し、第１半導体基板のスルーホールと異方導電性接続した第２半導体基板のスルーホールと、第３半導体基板のスルーホールとの間に、スルーホールの配置に対応して導電粒子が絶縁接着剤層に選択的に配置された異方導電性フィルムを挟み、該異方導電性フィルムを加熱加圧することにより第２半導体基板と第３半導体基板を異方導電性接続する請求項７記載の多層基板の製造方法。
  9. 　絶縁接着剤層と、該絶縁接着剤層に配置された導電粒子を含む異方導電性フィルムであって、異方導電性フィルムで接続するスルーホールの配置に対応して導電粒子が絶縁接着剤層に選択的に配置されている異方導電性フィルム。
  10. 　絶縁接着剤層と、該絶縁接着剤層に配置された導電粒子を含む異方導電性フィルムであって、３個以上の導電粒子が近接した粒子群が形成されており、粒子群に、少なくとも大きさ又は種類が異なる複数の導電粒子が含まれている異方導電性フィルム。
  11. 　粒子群において、複数の導電粒子が異方導電性フィルムのフィルム厚方向に重畳している請求項１０記載の異方導電性フィルム。
  12. 　粒子群において、複数の導電粒子が異方導電性フィルムの面方向に配置されている請求項１０又は１１記載の異方導電性フィルム。
  13. 　粒子群に含まれる導電粒子の少なくとも一部が絶縁接着剤層から露出している請求項１０～１２のいずれかに記載の異方導電性フィルム。
  14. 　粒子群が、異方導電性フィルムで接続するスルーホールの配置に対応して配置されている請求項１０～１３のいずれかに記載の異方導電性フィルム。
     
     
     
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