CN107210287A - 多层基板 - Google Patents

多层基板 Download PDF

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Publication number
CN107210287A
CN107210287A CN201680004716.6A CN201680004716A CN107210287A CN 107210287 A CN107210287 A CN 107210287A CN 201680004716 A CN201680004716 A CN 201680004716A CN 107210287 A CN107210287 A CN 107210287A
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Prior art keywords
hole
semiconductor substrate
conducting particles
anisotropic conductive
base plate
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Granted
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CN201680004716.6A
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English (en)
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CN107210287B (zh
Inventor
筱原诚郎
筱原诚一郎
阿久津恭志
石松朋之
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Dexerials Corp
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Dexerials Corp
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Abstract

提供导通特性优异且能以低成本制造的多层基板，该多层基板是层叠在内表面形成有镀膜的贯通孔（以下，称为通孔）的半导体基板的多层基板。在多层基板的俯视观察中，导电粒子选择性地存在于通孔所对置的位置。多层基板具有对置的通孔通过导电粒子连接、形成有该通孔的半导体基板彼此通过绝缘粘接剂粘接的连接构造。

Description

多层基板
技术领域
本发明涉及多层基板。
背景技术
在IC的高密度安装领域中，使用对装入有IC等的电子部件的半导体基板进行层叠的多层基板。
作为多层基板的制造方法，有这些方法，即将具有凸点的贯通电极形成在各个半导体基板，利用凸点的回流焊来连接对置的半导体基板的贯通电极彼此的方法（专利文献1）；或在对置的半导体基板之间夹着向绝缘粘接剂层中分散了导电粒子的各向异性导电性膜，并加热加压而连接贯通电极彼此的方法（专利文献2）。
在该情况下，如图14所示，贯通电极6一般这样形成，即（a）在半导体基板3（b）形成贯通孔4h，（c）通过非电解镀来形成镀膜4a，对它进行构图而在贯通孔4h的内部留下镀膜4a，从而形成通孔，（d）进而以既定图案设置掩模并进行电解镀而向通孔内填充金属5。
先前技术文献
专利文献
专利文献1：日本特开2010－272737号公报
专利文献2：日本特开平8－330736号公报。
发明内容
发明要解决的课题
然而，在各个半导体基板的贯通电极形成凸点，利用焊锡的回流焊来连接对置的半导体基板的贯通电极，层叠半导体基板的方法，其制造工序复杂。
在使用各向异性导电性膜来连接对置的贯通电极，层叠半导体基板的方法中，虽然能某个程度地简化多层基板的制造工序，但是，由于各向异性导电性膜在绝缘粘接剂层中随机地分散了导电粒子，所以有各向异性导电性膜的导电粒子没有充分地夹在对置的半导体基板的贯通电极间的情况，从而有导通特性出现偏差这一问题。另一方面，在对置的半导体基板间存在许多对贯通电极的连接无贡献的导电粒子，因而还存在无用的导电粒子耗费成本这一问题。
因此，本发明的课题为利用各向异性导电性膜来层叠半导体基板，以简便的制造工序且低成本提供导通特性优异的多层基板。
用于解决课题的方案
本发明人发现了在利用各向异性导电性膜层叠半导体基板，制造多层基板时，若对在形成贯通电极的前面阶段形成的通孔选择性地配置各向异性导电性膜的绝缘粘接剂中的导电粒子，并利用这样的各向异性导电性膜，连接对置的半导体基板的通孔，则能够以导电粒子可靠地连接对置的通孔，另外，减少对连接无贡献的导电粒子数，并且还显著地简化多层基板的制造工序，降低多层基板的制造成本，并想到了本发明。
即，本发明提供多层基板，是层叠具有通孔的半导体基板的多层基板，在多层基板的俯视观察中，导电粒子选择性地存在于通孔所对置的位置，
具有对置的通孔通过导电粒子连接、形成有该通孔的半导体基板彼此通过绝缘粘接剂粘接的连接构造。
特别是，作为该多层基板，提供层叠具有通孔的第1半导体基板和具有通孔的第2半导体基板的多层基板，该多层基板中，
具有这样的连接构造：
第1半导体基板的通孔和第2半导体基板的通孔对置，并通过选择性地配置在它们之间的导电粒子连接，
第1半导体基板和第2半导体基板通过绝缘粘接剂粘接。
另外，本发明提供多层基板的制造方法，是使形成在半导体基板的通孔彼此对置并接合的多层基板的制造方法，在具有通孔的半导体基板彼此之间夹住对应于通孔所对置的部分在多层基板的俯视观察中的位置而对绝缘粘接剂层选择性地配置导电粒子的各向异性导电性膜，对该各向异性导电性膜进行加热加压，从而各向异性导电性连接这些半导体基板。
特别是，作为该多层基板的制造方法，提供对具有通孔的第1半导体基板和具有通孔的第2半导体基板，使它们的通孔彼此对置而接合的多层基板的制造方法，该多层基板的制造方法中，在第1半导体基板与第2半导体基板之间，夹住导电粒子对应于通孔的配置而选择性地配置在绝缘粘接剂层的各向异性导电性膜，对该各向异性导电性膜进行加热加压，从而各向异性导电性连接第1半导体基板与第2半导体基板。
进而，本发明作为使用于上述多层基板的制造方法的各向异性导电性膜，提供导电粒子对应于以各向异性导电性膜连接的通孔的配置而选择性地配置在绝缘粘接剂层的各向异性导电性膜。
另外，作为对上述多层基板的制造方法有用的各向异性导电性膜，提供包含绝缘粘接剂层和配置在该绝缘粘接剂层的导电粒子的各向异性导电性膜，该各向异性导电性膜中，形成有2个以上的导电粒子接近的导电粒子单元，在导电粒子单元中，包含至少大小或种类不同的多个导电粒子。
发明效果
依据本发明的多层基板，由于半导体基板的通孔彼此利用导电粒子可靠地连接，所以导通特性稳定。
另外，半导体基板中，无需向通孔内填充金属而形成贯通电极，而以导电粒子连接通孔彼此，且，减少了在半导体基板间对连接无贡献的导电粒子，因此能显著地抑制多层基板的制造成本。另外，基于同样的理由，对仪表操作工时数的削减也是有效的。
进而，本发明的多层基板，通过使用特定的各向异性导电性膜，能以简便的工序进行制造。
特别是在层叠3个以上半导体基板的多层基板的情况下，若在层叠的半导体基板间使用共同的各向异性导电性膜，则能够大幅削减多层基板的总制造成本。因而，能够以更进一步低价格提供本发明的多层基板。
附图说明
[图1]图1是本发明的一实施方式的多层基板1A的截面图。
[图2]图2是本发明的一实施方式的多层基板1B的截面图。
[图3A]图3A是多层基板1B的制造工序的说明图。
[图3B]图3B是多层基板1B的制造工序的说明图。
[图3C]图3C是多层基板1B的制造工序的说明图。
[图3D]图3D是多层基板1B的制造工序的说明图。
[图4A]图4A是各向异性导电性连接前的、导电粒子对于通孔的配置的说明图。
[图4B]图4B是各向异性导电性连接后的、导电粒子对于通孔的配置的说明图。
[图5A]图5A是各向异性导电性连接前的、导电粒子对于通孔的配置的说明图。
[图5B]图5B是各向异性导电性连接后的、导电粒子对于通孔的配置的说明图。
[图6A]图6A是各向异性导电性连接前的、导电粒子对于通孔的配置的说明图。
[图6B]图6B是各向异性导电性连接后的、导电粒子对于通孔的配置的说明图。
[图7A]图7A是各向异性导电性连接前的、导电粒子对于通孔的配置的说明图。
[图7B]图7B是各向异性导电性连接后的、导电粒子对于通孔的配置的说明图。
[图8]图8是各向异性导电性连接前的、导电粒子对于通孔的配置的说明图。
[图9]图9是本发明的一实施方式的多层基板1C的截面图。
[图10]图10是在实施例1的多层基板的制造中使用的半导体基板的表面中的电极与导电粒子的配置图。
[图11]图11是在实施例4的多层基板的制造中使用的半导体基板的表面中的电极与导电粒子的配置图。
[图12]图12是在实施例5的多层基板的制造中使用的半导体基板的表面中的电极与导电粒子的配置图。
[图13]图13是在实施例6的多层基板的制造中使用的半导体基板的表面中的电极与导电粒子的配置图。
[图14]图14是贯通电极的制造方法的工序说明图。
具体实施方式
以下，一边参照附图，一边对本发明详细地进行说明。此外，各图中，同一标号表示同一或同等的结构要素。
＜多层基板中的连接构造＞
图1是本发明的一实施方式的多层基板1A的截面图。
该多层基板1A在布线基板2层叠了3层的半导体基板3A、3B、3C，各半导体基板3A、3B、3C是形成有IC等的半导体部件的半导体晶圆。另外，在布线基板2形成有通孔4X，在各半导体基板3A、3B、3C形成有通孔4A、4B、4C，在布线基板2的表面露出通孔4X的部分、或在半导体基板的表面露出通孔4A、4B、4C的部分，分别形成有电极焊盘9。此外，本发明中作为半导体基板3A、3B、3C，也可以使用半导体芯片。另外，本发明中，对构成多层基板的半导体基板的层叠数无特别限制。
在多层基板1A具有这样的连接构造：第1半导体基板3A的通孔4A与第2半导体基板3B的通孔4B对置，并通过选择性地配置在它们之间的导电粒子11来电连接。该连接构造中，在通孔4A、4B对置的之间选择性地配置有导电粒子11是指以在俯视观察中导电粒子11主要存在于通孔4A、4B的对置面或其附近，并被通孔4A、4B捕获1个以上的导电粒子11的方式配置。从兼顾成本和性能的方面来说，优选配置成捕获1～十几个。也可以在膜厚方向上重叠多个导电粒子。另外，在通孔4A、4B的对置面存在多个导电粒子11的情况下，该导电粒子的大小、种类等也可以不同。此外，在通孔4A、4B的对置面配置多个导电粒子11的情况下，能够缓和半导体基板3A、3B与导电粒子11的对位精度。
第1半导体基板3A与第2半导体基板3B的对置面彼此，通过绝缘粘接剂12来粘接。绝缘粘接剂12由后述的各向异性导电性膜的绝缘粘接剂层形成。
另外，与第1半导体基板3A的通孔4A连接的第2半导体基板3B的通孔4B，在第3半导体基板3C侧，还与第3半导体基板3C的通孔4C对置，并通过选择性地配置在它们之间的导电粒子11来电连接第2半导体基板3B的通孔4B与第3半导体基板3C的通孔4C。该第2半导体基板3B与第3半导体基板3C的对置面彼此也通过绝缘粘接剂12粘接。另外，布线基板2的通孔4X和第1半导体基板3A的通孔4A也通过导电粒子11同样地连接。这样，多层基板1A具有布线基板2的通孔4X和3层的半导体基板的通孔4A、4B、4C在多层基板的层叠方向上以直线状相连的连接构造。依据该各层的通孔以直线状相连的连接构造，缩短电传输的路径，因此能够提高传输速度。
此外，多层基板1A如后述那样通过利用导电粒子具有特定配置的本发明的各向异性导电性膜来连接构成多层基板的各层而被制造。在此情况下，在第1半导体基板3A与第2半导体基板3B之间，即便存在不被对置的通孔4A、4B捕获的导电粒子11，也优选使那样的导电粒子11的数为存在于第1半导体基板与第2半导体基板之间的导电粒子的总数的5％以下，更优选为0.5％以下，特别是使得导电粒子11的大致全部被通孔4A、4B捕获。在构成多层基板1A的其他的半导体基板间也同样。这样通过减少对通孔4A、4B、4C的连接无贡献的导电粒子11，变得容易对性能进行模拟解析，并能削减改善工时数。。
＜布线基板＞
在此，作为构成多层基板1A的布线基板2，能够使用FR4等的环氧玻璃基板等。作为布线基板2，也可以使用IC芯片或IC形成用的硅晶片。布线基板2可根据多层基板1A的用途等而适当选择。
另外，在布线基板2的电极部分，也可以根据需要设有焊锡球8。
＜半导体基板＞
作为半导体基板3A、3B、3C，只要具有通孔4A、4B、4C就无特别限制，例如，能够使用硅等一般的半导体材料等。
通孔4A、4B、4C的规格能够适当设定。例如，通孔4A、4B、4C优选具备电极焊盘9。另外，在层叠半导体基板3A、3B、3C的情况下，优选以使各半导体基板3A、3B、3C的通孔4A、4B、4C沿多层基板1A的厚度方向至少跨接2层的半导体基板而以直线状相连的方式、优选以跨接多层基板1A的表面和背面而以直线状相连的方式配置通孔4A、4B、4C。
＜搭载部件＞
关于本发明的多层基板，根据需要能够搭载各种部件。
例如图2所示的多层基板1B具有各层的通孔4X、4A、4B、4C以直线状相连的连接构造，在最外层具有与通孔4C连接的散热用的散热器7。因而，多层基板1B能够通过散热器7来有效率地对从形成在散热布线基板2或半导体基板3A、3B、3C的IC等的电子部件等释放的热进行散热。
＜多层基板的制造方法＞
作为本发明的多层基板的制造方法，例如，在图2的多层基板1B的情况下，首先，如图3A所示，在具有通孔4X的布线基板2与具有通孔4A的半导体基板3A之间，夹住导电粒子11对应于应该连接的通孔4X、4A的配置而选择性地配置在绝缘粘接剂层12的本发明的各向异性导电性膜10A，通过对各向异性导电性膜10A进行加热加压来各向异性导电性连接布线基板2与第1半导体基板3A，从而得到图3B所示的2层的连接构造体。更具体而言，将布线基板2和各向异性导电性膜10A，以使应该连接的通孔4X与导电粒子11的配置相匹配的方式对位重叠，进而使第1半导体基板3A也同样地对位叠合，加热加压而将它们各向异性导电性连接。该对位也可以通过利用CCD等观测各向异性导电膜的与通孔对应的导电粒子（如后述那样形成有粒子群的情况下，构成该粒子群的导电粒子）和通孔，使它们叠合来进行。
同样地，如图3C所示，将第1半导体基板3A和各向异性导电性膜10B对位重叠，在其上使第2半导体基板3B对位重叠，加热加压而各向异性导电性连接，从而得到图3D所示的3层的连接构造。进而同样地处理而在第2半导体基板3B上使各向异性导电性膜和第3半导体基板3C对位重叠，并加热加压。
此外，在利用各向异性导电性膜来连接布线基板与半导体基板的情况下，或者，在连接半导体基板彼此的情况下，首先，使一个基板与各向异性导电性膜对位重叠，并加热加压而将各向异性导电性膜的导电粒子与该基板的通孔接合，从而使导电粒子进入到通孔内，接着叠合对置的基板，能够将该基板与先前的基板的通孔及导电粒子接合。
然后，通过导热带等，在第3半导体基板3C上连接散热器7，在布线基板2的电极焊盘9形成焊锡球8，通过常用方法来得到多层基板1B。或者，也可以取代焊锡球8而设置导电粒子。
此外，作为布线基板2或半导体基板3A、3B、3C与各向异性导电性膜10A、10B的对位方法，也可以在布线基板2、半导体基板3A、3B、3C及各向异性导电性膜10A、10B分别先带有对准标记，通过对齐这些对准标记来进行对位。
即，以前，在层叠半导体基板而制造多层基板的情况下，作为一个例子，在半导体基板形成数十μm～数百μm的大小的对准标记，利用CCD或激光来进行半导体基板彼此的对位。另一方面，在各向异性导电性膜以单分散或格子状配置导电粒子，因此在各向异性导电性膜未带有对准标记。相对于此，在本发明所使用的各向异性导电性膜，由于导电粒子11对应于应该连接的通孔的配置而选择性地配置在绝缘粘接剂层12，所以能够将导电粒子11的配置作为对准标记的代替。优选也包括这样的导电粒子的配置在内而在各向异性导电性膜设置一些对准标记。
＜各向异性导电性膜＞
关于在本发明的多层基板的制造方法中使用的本发明的各向异性导电性膜，导电粒子11对应于应该连接的通孔的配置而选择性地配置在绝缘粘接剂层12，优选形成有对准标记。作为对准标记，优选通过导电粒子的配置来形成。由此，能够明确地检测对准标记，且不需要追加用于使各向异性导电性膜带有对准标记的新的工序。另一方面，对准标记也可以通过以激光照射等使绝缘粘接剂层12局部固化而形成。由此带有对准标记的位置的变更变得容易。
作为这样的各向异性导电性膜的制造方法，通过对金属板进行机械加工、激光加工、光刻等的公知的加工方法而制作具有与导电粒子11的配置对应的凸部的模具，向该模具填充固化性树脂，使之固化而制造凹凸反转的树脂模，使导电粒子进入该树脂模的凹部，在其上填充绝缘粘接剂层形成用组合物，并使之固化，从模中取出即可。
另外，为了使导电粒子11在绝缘粘接剂层12处于特定配置，也可以为在绝缘粘接剂层形成组合物层上，设置以既定配置形成贯通孔的构件，从其上供给导电粒子11，使之通过贯通孔等的方法。
＜形成各向异性导电性膜的导电粒子＞
作为使用于各向异性导电性膜10的导电粒子11，能够从公知的各向异性导电性膜所使用的材料中适当选择而使用。可举出例如焊锡、镍、钴、银、铜、金、钯等的金属粒子；金属包覆树脂粒子等。金属包覆树脂粒子的金属包覆，能够利用非电解镀法、溅射法等的公知的金属膜形成方法来形成。金属包覆只要形成在芯（core）树脂材料的表面就无特别限制。芯树脂材料既可以仅由树脂形成，也可以为提高导通可靠性而含有导电微粒。
从导通可靠性和成本的方面来说，作为导电粒子，优选使用上述粒子之中的焊锡粒子。另一方面，在后面工序中不需要回流焊工序的情况等，优选使用金属包覆树脂粒子。这是因为在本发明中通过在绝缘性粘接剂层配置有导电粒子的各向异性导电性膜的加热加压，进行通孔彼此的连接或半导体基板彼此的粘接，因此，如果使用金属包覆树脂粒子作为导电粒子，则能够使加热加压低温化，会扩大绝缘性粘接剂的材料选择范围。
另外，作为导电粒子，也能一并使用大小、种类等不同的2种以上的粒子。
＜各向异性导电性膜中的导电粒子的配置＞
在各向异性导电性膜中，从通孔彼此的接合的稳定性方面来说，根据通孔的开口直径等而适当选择导电粒子11的配置、粒径及种类。
例如，如图3C、图3D所示，在通孔4A、4B的对置部位配置1个导电粒子11的情况下，导电粒子11的粒径通常优选大于通孔4A、4X的开口直径。在导电粒子11由焊锡粒子形成的情况下，如图4A、图4B所示，通孔的镀膜4a容易被因各向异性导电性连接时的加热加压而熔化的焊锡粒子浸润，但是在该情况下也优选使导电粒子11的粒径为通孔4A、4B的开口直径以上。由此，导电粒子11在通孔4A、4B被按压，能够以导电粒子11可靠地连接通孔4A、4B。
另外，在导电粒子的粒径小于通孔的开口直径的情况下，如图5A所示的各向异性导电性膜10那样，优选让使多个导电粒子11邻接的粒子群11a的直径大于通孔4A、4B的开口直径，如图5B所示，使得对置的通孔4A、4B通过导电粒子11可靠地连接。以由多个导电粒子构成的粒子群11a连接通孔4A、4B，从而与由一个一个的导电粒子连接的情况相比，还能够使连接后的导通电阻可靠（robust）。
如图6A所示的各向异性导电性膜10那样，由多个导电粒子11构成的粒子群11a也可以以沿各向异性导电性膜10的厚度方向重叠的方式配置。由此，如图6B所示，能够使导电粒子11进入到通孔4A、4B的更深的位置。
在对应于通孔而形成使多个导电粒子11邻接的粒子群的情况下，多个导电粒子的大小或种类也可以不同。例如，如图7A所示的各向异性导电性膜10那样，使大径的导电粒子11p与通孔4A、4B对置，而将小径的导电粒子11q配置在大径的导电粒子11p的周围且被电极焊盘捕获的位置。在该情况下，优选使大径的导电粒子11p比小径的导电粒子11q容易变形。隔着该各向异性导电性膜10而对半导体基板3A、3B进行加热加压，从而如图7B所示的连接构造那样，能够使大径的导电粒子11p夹于通孔4A、4B间，并以小径的导电粒子11q填埋通孔4A、4B与大径的导电粒子11p的间隙，能够提高通孔4A、4B与导电粒子的导通性。另外，粒子群11a中，使导电粒子彼此先接触，从而通孔4A、4B与导电粒子变得容易接触。
为了得到图7B的连接构造，也可以如图8所示，预先将具有大径的导电粒子11p的各向异性导电性膜10p与一个半导体基板3A临时粘接，将具有小径的导电粒子11q的各向异性导电性膜10q与另一个半导体基板3B临时粘接，然后将半导体基板3A、3B加热加压。
另外，如图7A所示，在各向异性导电性膜中，导电粒子也可以从绝缘粘接剂层12露出，特别优选露出要挟持于通孔4A、4B的大径的导电粒子11p。通过使导电粒子从绝缘粘接剂层露出，使得导电粒子与通孔的对准变得容易，另外，由于绝缘粘接剂层12并未介于导电粒子与通孔之间，所以提高导电粒子与通孔的导通性。
此外，也可以通过以隔离膜覆盖等保护各向异性导电性膜的导电粒子的露出面，在使用各向异性导电性膜时使导电粒子露出。
＜绝缘粘接剂层＞
作为形成各向异性导电性膜的绝缘粘接剂层12，能够适当采用在公知的各向异性导电性膜所使用的绝缘性树脂层。例如，能够使用包含丙烯酸酯化合物和光自由基聚合引发剂的光自由基聚合型树脂层；包含丙烯酸酯化合物和热自由基聚合引发剂的热自由基聚合型树脂层；包含环氧化合物和热阳离子聚合引发剂的热阳离子聚合型树脂层；包含环氧化合物和热阴离子聚合引发剂的热阴离子聚合型树脂层等。另外，这些树脂层可根据需要为分别聚合的树脂。另外，由多个树脂层形成绝缘粘接剂层12也可。
但是，因为从多层基板1A切出芯片等的用途，在制造多层基板1A后切断多层基板1A的情况下，优选绝缘粘接剂层12具有能承受切断的柔软性和粘接性。
另外，根据需要，也可以向绝缘粘接剂层12加入二氧化硅微粒、氧化铝、氢氧化铝等的绝缘性填充物。绝缘性填充物的配合量相对于形成绝缘粘接剂层的树脂100质量份优选为3～40质量份。由此，在各向异性导电性连接时即便绝缘粘接剂层12熔化，也能抑制导电粒子11因熔化的树脂而无用地移动。
另外，根据需要也可以向绝缘粘接剂层12加入能够填充到通孔的粒径的绝缘性隔离物。由此，变得容易确保各向异性导电性连接时的压入的均匀性。
在各向异性导电性连接之前，也可以使导电粒子附近的绝缘粘接剂层的树脂的一部分预先聚合。由此，通孔与导电粒子的对准变得容易，能够降低短路的发生风险。
＜变形方式＞
在上述各向异性导电性膜10中，几乎不存在存在于既定位置以外的导电粒子。另一方面，即便存在于既定位置也能存在不被对置的通孔4A、4B捕获的导电粒子。因而，优选在将该各向异性导电性膜10使用于半导体基板3A、3B的连接之后，使在对置的半导体基板3A、3B之间，不被通孔4A、4B捕获的导电粒子11的数，成为存在于对置的半导体基板3A、3B之间的导电粒子11的总数的5％以下。
另一方面，图9所示的多层基板1C，通过在图1所示的多层基板1A中，作为连接布线基板2的通孔4X与第1半导体基板3A的通孔4A的各向异性导电性膜、连接第1半导体基板3A的通孔4A与第2半导体基板3B的通孔4B的各向异性导电性膜、和连接第2半导体基板3B的通孔4B与第3半导体基板3C的通孔4C的各向异性导电性膜，使用共同的各向异性导电性膜而制造。即，作为各向异性导电性膜，使用在想要制造的多层基板1C的俯视图中，导电粒子11对应于布线基板2或各半导体基板3A、3B、3C的通孔彼此对置的部分而选择性地配置在绝缘粘接剂层12的膜。由此，在多层基板1C的俯视图中，在通孔4X、4A、4B、4C所对置的部分会存在导电粒子11、11x。换言之，在对置的通孔之间未必一定存在仅对该通孔选择性地配置的导电粒子。例如，在半导体基板3A与半导体基板3B之间，除了导电粒子11选择性地配置在形成在这些基板的通孔4A、4B所对置的位置以外，还存在对半导体基板3A的通孔4A与半导体基板的通孔4B的连接无贡献的导电粒子11x。因而，相对于在半导体基板3A与半导体基板3B之间存在的全部导电粒子，在半导体基板3A与半导体基板3B之间不被通孔捕获的导电粒子能够超过5％而存在。然而，在半导体基板3A与半导体基板3B之间对这些连接无贡献的导电粒子11x，对布线基板2的通孔4X与第1半导体基板3A的通孔4A的连接有贡献。另外，在多层基板1C的俯视观察中，在通孔彼此不对置的位置，未配置或者实质上不存在导电粒子。
这样利用共同的各向异性导电性膜来连接各半导体基板时，能够削减制造多层基板所需的总成本。另外，也能容易地对应多层基板的阵列（lineup）的增加（规格变更）。此外，在该各向异性导电性膜中，也能将导电粒子作为多个导电粒子接近的粒子群而配置。
另外，在利用共同的各向异性导电性膜连接各半导体基板，从而削减制造多层基板所需的总成本的情况下，也可以使用在一面配置粒子群11a的各向异性导电性膜来制造多层基板。在该情况下，构成各粒子群11a的导电粒子数为3个以上，优选为10个以上，更优选为12个以上。为了避免发生短路，粒子群11a彼此的间隔设为导电粒子直径的1倍以上，根据半导体基板的通孔间隔而适当决定。与按连接的每个半导体基板使用导电粒子的配置不同的各向异性导电性膜的情况相比，通过共同利用在一面以适当的间隔配置粒子群11a的各向异性导电性膜，能够大幅减少多层基板的制造成本。
在各半导体基板共同使用的各向异性导电性膜中，如前述那样从通孔彼此的接合稳定性的方面来说，适当选择构成粒子群的多个导电粒子的配置、粒径及种类，既可以使一个粒子群包含至少大小或种类不同的多个导电粒子，也可以在一个粒子群中使多个导电粒子沿各向异性导电性膜的膜厚方向重叠，也可以在一个粒子群中使多个导电粒子沿各向异性导电性膜的面方向配置，也可以使粒子群所包含的导电粒子的至少一部分从绝缘粘接剂层露出。
如以上那样，本发明的多层基板中，在多层基板的俯视观察中，导电粒子选择性地存在于通孔所对置的位置。而且，通过这样配置的导电粒子，对置的通孔连接，形成有该通孔的半导体基板彼此通过绝缘粘接剂来粘接。在该情况下，对置的通孔，既可以通过仅在该对置的通孔之间选择性地配置的导电粒子11来连接，另外，也可以在形成有对置的通孔的半导体基板3A、3B、3C间，包含对该对置的通孔的连接无贡献的导电粒子11x。
本发明的多层基板能够在以高密度半导体封装等为首的、要求高密安装的各种半导体等的各种用途中使用。另外，也可以将多层基板以既定尺寸切断而使用。
实施例
以下，利用实施例来具体地对本发明进行说明。
实施例1～6、比较例1
（1）半导体基板
作为构成多层基板的半导体基板3，准备外形为7mm□、厚度100μm的矩形，且如图7所示，具有铬制电极焊盘的通孔4以外围（peripheral）配置（φ30μm、85μm间距、280端子（pin））形成的基板。
作为对准标记，在半导体基板形成有200μm□的四边形标记。
（2）各向异性导电性膜的制造
如表1所示，制造在绝缘粘接剂层使表1所示的粒径的导电粒子（微粉焊锡粉、三井金属矿业（株））随机分散（比较例1、粒子密度60个/mm2）、或对应于半导体基板的通孔4的配置而配置的（实施例1～6、85μm间距、280处）各向异性导电性膜。
在该情况下，实施例1、2、3中，如图10所示，按通孔4的端部电极每1处配置1个导电粒子11，实施例4中，如图11所示，使绝缘粘接剂层12为2层，并在各粘接剂层12配置导电粒子11，从而按通孔4的端部电极的每1处沿膜厚方向使2个导电粒子并排而配置，实施例5中，按通孔4的端部电极的每1处如图12所示沿膜面方向使2个导电粒子11并排而配置，实施例6中，按通孔4的端部电极的每1处如图13所示沿膜面方向使9个导电粒子并排而配置。
另外，实施例1～6中，利用导电粒子来形成对准标记。在该情况下，使得导电粒子的排列的轮廓与半导体基板3的对准标记的轮廓大体一致。
更具体而言，准备厚度2mm的镍板，以使凸部（直径30～45μm，高度25μm～40μm。例如，实施例1中直径45μm、高度40μm）成为上述导电粒子的配置的方式构图而制作转印母版。另外，以使干燥厚度成为50μm的方式在PET（聚对苯二甲酸乙二醇酯）膜上涂敷混合了苯氧基树脂（YP－50、新日铁住金化学（株））50质量份、微胶囊化咪唑化合物潜在性固化剂（NOVACURE HX3941HP、旭化成E-MATERIALS（株））30质量份、及气相二氧化硅（AEROSILRY200、日本AEROSIL（株））20质量份的粘合剂，使该粘合剂朝向上述转印母版而叠合，在80℃干燥5分钟后，利用高压水银灯进行1000mJ光照射，从而作成具有凹部的转印模。
另一方面，由苯氧基树脂（YP－50、新日铁住金化学（株））60质量份、环氧树脂（jER828、三菱化学（株））40质量份、阳离子类固化剂（SI－60L、三新化学工业（株））2质量份调制绝缘粘接剂形成用组合物，将它涂敷到膜厚50μm的PET膜上，以80℃的烤箱干燥5分钟，在PET膜上以30μm形成由绝缘性树脂构成的粘着层。
向具有前述的凹部的转印模填充导电粒子，在其上覆盖上述绝缘性树脂的粘着层，照射紫外线而使绝缘性树脂所包含的固化性树脂固化。然后，从模剥离绝缘性树脂，并以使导电粒子的端部和界面一致的方式压入，从而制造实施例1～3的各向异性导电膜。实施例4中将粘着层的厚度变更为25μm，同样地从模剥离，在60℃、0.5MPa下对剥离后的绝缘性树脂彼此进行层叠从而制造2层绝缘粘接剂层的各向异性导电膜。实施例5、6中将粘着层的厚度变更为15μm，同样地从模剥离，将在其上与粘着层同样制作的绝缘性树脂层（厚度15μm）在60℃、0.5MPa下层叠在粘着层的导电粒子侧，从而制造各向异性导电性膜。
另一方面，随机分散有导电粒子的比较例1的各向异性导电性膜是通过用自转公转式混合装置（（株）THINKY）搅拌导电粒子和绝缘性树脂而得到导电粒子的分散物、以30μm形成该分散物的涂膜而制造的。
（3）多层基板的制造
利用（2）中制造的各向异性导电性膜，以表1所示的层叠数对（1）中准备的半导体基板进行叠合并按压，进一步加热加压（180℃、40MPa、20秒）从而制造多层基板。
（4）评价
对于所得到的多层基板，如下那样进行（a）填充的评价、（b）熔化的评价。将这些结果示于表1中。
（a）填充的评价
在将半导体基板叠合，在按压的状态下，将在对置的通孔之间存在导电粒子的情况设为“OK”、不存在的情况设为“NG”。
（b）熔化的评价
观察多层基板的厚度方向的截面，将对置的通孔以导电粒子连接，进而导电粒子的熔化物沿着通孔的内壁进入的情况设为“A”，将对置的通孔以导电粒子连接，但导电粒子的熔化物没有沿着通孔的内壁进入的情况设为“B”。
[表1]
在比较例1的多层基板中，产生许多填充成为不良的通孔，而实施例1～6的多层基板全都填充良好，能够确认能通过导电粒子来连接通孔彼此。特别是，实施例6中，通孔与导电粒子的配置的位置偏移的容许宽度大。
标号说明
1A、1B 多层基板；2 布线基板；3、3A、3B、3C 半导体基板；4、4A、4B、4C 通孔；4a 镀膜；4h 贯通孔；5 金属；6 贯通电极；7 散热器；8 焊锡球；9 电极焊盘；10、10A、10B 各向异性导电性膜；11、11p、11q 导电粒子；11a 粒子群；12 绝缘粘接剂或绝缘粘接剂层。

Claims (14)

1.一种多层基板，层叠具有在内表面形成有镀膜的贯通孔（以下，称为通孔）的半导体基板，
在多层基板的俯视观察中，导电粒子选择性地存在于通孔所对置的位置，
具有对置的通孔通过导电粒子连接、形成有该通孔的半导体基板彼此通过绝缘粘接剂粘接的连接构造。
2.如权利要求1所述的多层基板，是层叠具有通孔的第1半导体基板和具有通孔的第2半导体基板的多层基板，第1半导体基板的通孔和第2半导体基板的通孔，通过选择性地配置在它们之间的导电粒子连接。
3.如权利要求2所述的多层基板，其中，
具有通孔的第3半导体基板层叠在第2半导体基板，
具有这样的连接构造：
与第1半导体基板的通孔连接的第2半导体基板的通孔和第3半导体基板的通孔对置，并通过选择性地配置在它们之间的导电粒子连接，
第2半导体基板和第3半导体基板通过绝缘粘接剂粘接。
4.如权利要求1～3的任一项所述的多层基板，其中，导电粒子进入通孔内。
5.如权利要求1～4的任一项所述的多层基板，其中，在多层基板的最外层具有散热器，散热器与以导电粒子连接而沿多层基板的层叠方向相连的通孔连接。
6.一种多层基板的制造方法，使形成在半导体基板的通孔彼此对置并接合，其中，在具有通孔的半导体基板彼此之间，夹住对应于通孔所对置的部分在多层基板的俯视观察中的位置而对绝缘粘接剂层选择性地配置导电粒子的各向异性导电性膜，对该各向异性导电性膜进行加热加压，从而各向异性导电性连接这些半导体基板。
7.如权利要求6所述的多层基板的制造方法，是对具有通孔的第1半导体基板和具有通孔的第2半导体基板，使它们的通孔彼此对置而接合的多层基板的制造方法，在第1半导体基板与第2半导体基板之间，夹住导电粒子对应于通孔的配置而选择性地配置在绝缘粘接剂层的各向异性导电性膜，对该各向异性导电性膜进行加热加压，从而各向异性导电性连接第1半导体基板与第2半导体基板。
8.如权利要求7所述的多层基板的制造方法，其中，将具有通孔的第3半导体基板层叠在第2半导体基板，在与第1半导体基板的通孔各向异性导电性连接的第2半导体基板的通孔、和第3半导体基板的通孔之间，夹住导电粒子对应于通孔的配置而选择性地配置在绝缘粘接剂层的各向异性导电性膜，对该各向异性导电性膜进行加热加压，从而各向异性导电性连接第2半导体基板与第3半导体基板。
9.一种各向异性导电性膜，包含绝缘粘接剂层和配置在该绝缘粘接剂层的导电粒子，其中，导电粒子对应于以各向异性导电性膜连接的通孔的配置而选择性地配置在绝缘粘接剂层。
10.一种各向异性导电性膜，包含绝缘粘接剂层和配置在该绝缘粘接剂层的导电粒子，其中，形成有3个以上的导电粒子接近的粒子群，在粒子群中包含至少大小或种类不同的多个导电粒子。
11.如权利要求10所述的各向异性导电性膜，其中，在粒子群中，多个导电粒子沿各向异性导电性膜的膜厚方向重叠。
12.如权利要求10或11所述的各向异性导电性膜，其中，在粒子群中，多个导电粒子沿各向异性导电性膜的面方向配置。
13.如权利要求10～12的任一项所述的各向异性导电性膜，其中，粒子群所包含的导电粒子的至少一部分从绝缘粘接剂层露出。
14.如权利要求10～13的任一项所述的各向异性导电性膜，其中，粒子群对应于以各向异性导电性膜连接的通孔的配置而配置。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0362411A (ja) * 1989-07-31 1991-03-18 Canon Inc 異方性導電フィルムの製造方法
US5965064A (en) * 1997-10-28 1999-10-12 Sony Chemicals Corporation Anisotropically electroconductive adhesive and adhesive film
JP2002110897A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体装置およびその製造方法
US20020076537A1 (en) * 2000-12-16 2002-06-20 Unipac Optoelectronics Corporation Laminated structure
JP2005277112A (ja) * 2004-03-25 2005-10-06 Sony Chem Corp 多層配線基板及びその製造方法
JP2006245311A (ja) * 2005-03-03 2006-09-14 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP2010232492A (ja) * 2009-03-27 2010-10-14 Dainippon Printing Co Ltd 多層プリント配線板組合せ体およびその製造方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0334064Y2 (zh) 1985-08-21 1991-07-18
JP2748713B2 (ja) 1991-03-29 1998-05-13 日立化成工業株式会社 接続部材
JPH05182973A (ja) 1992-01-07 1993-07-23 Fujitsu Ltd 半導体装置の製造方法
TW301843B (en) * 1994-11-15 1997-04-01 Ibm Electrically conductive paste and composite and their use as an electrically conductive connector
JPH08330736A (ja) 1995-06-01 1996-12-13 Toray Ind Inc 多層基板およびその製造方法
JP3296306B2 (ja) 1997-10-28 2002-06-24 ソニーケミカル株式会社 異方導電性接着剤および接着用膜
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
JP2001237365A (ja) 2000-02-23 2001-08-31 Seiko Epson Corp 接続用端子の接合方法、半導体装置の製造方法および半導体装置
US20040177921A1 (en) 2001-06-29 2004-09-16 Akira Yamauchi Joining method using anisotropic conductive adhesive
JP2003282819A (ja) * 2002-03-27 2003-10-03 Seiko Epson Corp 半導体装置の製造方法
JP4340517B2 (ja) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
JP2006310082A (ja) 2005-04-28 2006-11-09 Tokai Rubber Ind Ltd 異方性導電膜およびその製造方法
JP5123664B2 (ja) * 2005-09-28 2013-01-23 スパンション エルエルシー 半導体装置およびその製造方法
DE102006001600B3 (de) * 2006-01-11 2007-08-02 Infineon Technologies Ag Halbleiterbauelement mit Flipchipkontakten und Verfahren zur Herstellung desselben
KR100777255B1 (ko) * 2006-04-18 2007-11-20 중앙대학교 산학협력단 이방성 도전 필름 및 이를 이용한 전자부품의 실장방법
JP2006339160A (ja) 2006-06-02 2006-12-14 Hitachi Chem Co Ltd 熱硬化性回路接続部材及びそれを用いた電極の接続構造、電極の接続方法
JP5010990B2 (ja) * 2007-06-06 2012-08-29 ソニーケミカル＆インフォメーションデバイス株式会社 接続方法
JP5018270B2 (ja) 2007-06-22 2012-09-05 パナソニック株式会社 半導体積層体とそれを用いた半導体装置
KR101193757B1 (ko) * 2007-09-20 2012-10-23 소니 케미카루 앤드 인포메이션 디바이스 가부시키가이샤 이방성 도전막 및 그 제조 방법, 및 그 이방성 도전막을 이용한 접합체
JP5622137B2 (ja) * 2007-10-29 2014-11-12 デクセリアルズ株式会社 電気的接続体及びその製造方法
JP5212118B2 (ja) * 2009-01-05 2013-06-19 日立金属株式会社 半導体装置およびその製造方法
JP2010251547A (ja) * 2009-04-16 2010-11-04 Elpida Memory Inc 半導体装置及びその製造方法
JP2010272737A (ja) 2009-05-22 2010-12-02 Elpida Memory Inc 半導体装置の製造方法
KR101219139B1 (ko) * 2009-12-24 2013-01-07 제일모직주식회사 이방 도전성 페이스트, 필름 및 이를 포함하는 회로접속구조체
CN103155050B (zh) * 2010-10-08 2017-05-03 第一毛织株式会社 各向异性导电膜
US8552567B2 (en) * 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
KR101941995B1 (ko) * 2012-07-11 2019-01-24 에스케이하이닉스 주식회사 반도체 장치 및 이를 갖는 적층 반도체 패키지
KR102254104B1 (ko) * 2014-09-29 2021-05-20 삼성전자주식회사 반도체 패키지
JP2016131246A (ja) * 2015-01-13 2016-07-21 デクセリアルズ株式会社 多層基板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0362411A (ja) * 1989-07-31 1991-03-18 Canon Inc 異方性導電フィルムの製造方法
US5965064A (en) * 1997-10-28 1999-10-12 Sony Chemicals Corporation Anisotropically electroconductive adhesive and adhesive film
JP2002110897A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体装置およびその製造方法
US20020076537A1 (en) * 2000-12-16 2002-06-20 Unipac Optoelectronics Corporation Laminated structure
JP2005277112A (ja) * 2004-03-25 2005-10-06 Sony Chem Corp 多層配線基板及びその製造方法
JP2006245311A (ja) * 2005-03-03 2006-09-14 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP2010232492A (ja) * 2009-03-27 2010-10-14 Dainippon Printing Co Ltd 多層プリント配線板組合せ体およびその製造方法

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