WO2016086841A1 - 二氧化硅基片的刻蚀方法和刻蚀设备 - Google Patents
二氧化硅基片的刻蚀方法和刻蚀设备 Download PDFInfo
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- WO2016086841A1 WO2016086841A1 PCT/CN2015/096128 CN2015096128W WO2016086841A1 WO 2016086841 A1 WO2016086841 A1 WO 2016086841A1 CN 2015096128 W CN2015096128 W CN 2015096128W WO 2016086841 A1 WO2016086841 A1 WO 2016086841A1
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- etching
- silicon dioxide
- gas
- dioxide substrate
- trench
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 181
- 238000005530 etching Methods 0.000 title claims abstract description 120
- 239000000758 substrate Substances 0.000 title claims abstract description 99
- 238000000034 method Methods 0.000 title claims abstract description 93
- 239000000377 silicon dioxide Substances 0.000 title claims abstract description 85
- 235000012239 silicon dioxide Nutrition 0.000 title claims abstract description 66
- 238000002161 passivation Methods 0.000 claims abstract description 35
- 238000005137 deposition process Methods 0.000 claims abstract description 26
- 238000001816 cooling Methods 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 106
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 24
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 6
- 229920002313 fluoropolymer Polymers 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 238000010792 warming Methods 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 238000006116 polymerization reaction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000003776 cleavage reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005289 physical deposition Methods 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Definitions
- the present invention relates to the field of semiconductor processing, and in particular to an etching method of a silicon dioxide substrate and an etching apparatus for performing the etching method.
- TSV Through Silicon Via
- the integrated circuit packaging technology based on TSV technology is the mainstream packaging technology.
- the integrated circuit packaged by TSV technology has small size, light weight, can effectively reduce parasitic effects, and improve the chip. Speed, power consumption and other characteristics.
- TGV Through Glass Via
- TGV Glass Via
- the low cost makes the advantages of TGV technology more prominent, and is known as the most promising three-dimensional packaging technology after TSV.
- the key point is that a via structure having a high aspect ratio and a small size needs to be etched on a silica glass substrate (hereinafter referred to as "silica substrate").
- the aspect ratio refers to the ratio of the depth of the through hole to the diameter of the through hole.
- a method of etching a silicon dioxide substrate is disclosed in Chinese Patent Application Publication No. WO 103700621, entitled “A Method of Etching a High Aspect Ratio Vertical Glass Through Hole", the method comprising the steps of:
- step S6 step S6 and step S5 are repeated until a trench having a predetermined aspect ratio is formed on the silicon dioxide substrate.
- step S4 is chemical vapor deposition
- step S5 is plasma etching. Therefore, the process chamber needs to have both a chemical vapor deposition function and a plasma etching function, which leads to the overall structural design of the etching device. Complex, costly, and increasing the complexity of the etching process.
- An object of the present invention is to provide a method for etching a silicon dioxide substrate and an etching device for performing the etching method.
- the etching device has a simple structure and a low cost, and the etching method is highly efficient.
- the present invention provides a method for etching a silicon dioxide substrate, wherein the etching method comprises:
- Step S2 and step S3 are repeatedly performed until a position corresponding to the first groove on the silica substrate forms a second groove having a predetermined aspect ratio.
- the temperature at which the silica substrate is cooled is set between -20 and 0 °C.
- the temperature at which the silica substrate is heated is set between 40 and 70 °C.
- the deposition process gas comprises a gaseous fluorocarbon
- the passivation layer is a fluorocarbon polymer layer.
- the main etching gas includes the same gaseous fluorocarbon as the step S2.
- the gaseous fluorocarbon comprises a CxFy compound and/or a CHxFy compound.
- the gaseous fluorocarbon comprises any one of CF 4 , C 4 F 8 , C 5 F 8 , CHF 3 , CH 2 F 2 or a combination of any of several.
- the power of the lower electrode is 0 to 10 W; and in the step S3, the power of the lower electrode is 200 to 1000 W.
- the main etching gas further includes an F-based gas other than the gaseous fluorocarbon, and the F-based gas includes SF 6 .
- an auxiliary etching gas is further introduced, and the auxiliary etching gas includes any one of argon gas, helium gas and nitrogen gas or a mixture of any one of them.
- an etching apparatus for etching a silicon dioxide substrate, wherein the etching apparatus includes a control module, a temperature adjustment module, a gas selection module, a deposition process gas source, and an engraving Etched gas source,
- control module controls the temperature adjustment module to cool the silicon dioxide substrate and control the gas
- the bulk selection module opens the deposition process gas source to pass a deposition process gas into the process chamber to form a passivation layer on the sidewalls and the bottom of the first trench;
- the control module controls the temperature adjustment module to heat the silicon dioxide substrate, and controls the gas selection module to open the etching gas source to pass an etching gas into the process chamber to Etching the bottom of the first trench;
- the control module controls the temperature adjustment module to alternately heat and cool the silicon dioxide substrate until a position on the silicon dioxide substrate corresponding to the first trench forms a predetermined aspect ratio Two slots up.
- step S2 since in step S2, only the silicon dioxide substrate is cooled and the deposition process gas is introduced into the process chamber in which the etching method is performed.
- the sidewalls and the bottom of one trench form a passivation layer, and the passivation layer is not required to be formed by chemical vapor deposition. Therefore, in the etching method of the silicon dioxide substrate of the present invention, the method of temperature control of the deposition process gas is performed. It is much simpler and easier than chemical vapor deposition, and the etching method is more efficient.
- the etching apparatus of the present invention since the step of forming a passivation layer on the sidewalls and the bottom of the first trench, it is only necessary to cool the silicon dioxide substrate and pass the deposition into the process chamber in which the etching method is performed.
- the process gas can form a passivation layer on the sidewalls and the bottom of the first trench, and does not need to form a passivation layer by chemical vapor deposition. Therefore, the process chamber does not need to have a chemical vapor deposition function, and the existing etching device is utilized.
- the step of forming a passivation layer on the sidewalls and the bottom of the first trench and the step of etching the bottom of the first trench may be performed without performing the step of forming a passivation layer on the sidewalls and the bottom of the first trench
- the process chamber performs other additional structural improvements. It can be seen that the etching apparatus provided by the invention has a simple structure and low cost.
- Figure 2a is a schematic view of the substrate after the first step S2;
- Figure 2b is a schematic view of the substrate after the first step S3;
- Figure 2c is a schematic view of the substrate after step S2 is performed again;
- Fig. 2d is a schematic view of the silica substrate after the step S3 is performed again.
- 100 a silicon dioxide substrate; 200, a mask pattern; 200a, a first trench; 300, a passivation layer; 100a, a trench having a certain depth.
- the present invention provides a method for etching a silicon dioxide substrate, wherein the etching method comprises:
- Step S2 and step S3 are repeatedly performed until a position corresponding to the first groove on the silicon oxide substrate forms a second groove having a predetermined aspect ratio. Wherein, step S2 and step S3 are alternately performed.
- the purpose of cooling the silica substrate is to deposit a deposition process gas on the sidewalls and bottom of the first trench to form a passivation layer.
- the deposition process gas is a gas that can be deposited to form a solid layer under low temperature conditions.
- step S2 since in step S2, only the silicon dioxide substrate is cooled and the deposition process gas is introduced into the process chamber in which the etching method is performed.
- the sidewalls and the bottom of one trench form a passivation layer, and the passivation layer is not required to be formed by chemical vapor deposition. Therefore, in the etching method of the silicon dioxide substrate of the present invention, the method of temperature control of the deposition process gas is performed. It is much simpler and easier than chemical vapor deposition, and the etching method is more efficient.
- the passivation layer 300 covers the upper surface of the mask pattern 200, the sidewalls of the first trench 200a, and the bottom of the first trench 200a.
- the first trench 200a is a through hole penetrating through the mask pattern 200. Therefore, the bottom of the first trench 200a is the portion of the silicon oxide substrate 100 that the first trench 200a can expose.
- step S3 when the step S3 is performed, the passivation layer on the bottom of the first trench 200a and the upper surface of the mask pattern 200 is etched due to the anisotropic etching ability during the etching method. Completely, the passivation layer on the sidewall of the first trench 200a is still retained. After a predetermined etching time, the portion of the silicon substrate 100 exposed by the first trench 200a is partially etched away to form A groove 100a having a certain depth. In order to ensure the normal progress of step S3, preferably, in step S3, the silica substrate is heated to set the temperature of the cooler of the process chamber between 40 and 70 °C.
- step S3 The reason why the temperature of the silica substrate is preferably increased in step S3 is that the etching of the silicon dioxide is an endothermic reaction, the higher the temperature, the faster the etching rate, and the high temperature is favorable to maintain the anisotropy of the etching.
- step S3 is too long, it is easy to etch the sidewall of the formed groove 100a having a certain depth, which is disadvantageous for forming a groove having a predetermined aspect ratio, so, as shown in FIG. 2c,
- step S2 is continued to form a capping layer 300 covering the mask pattern 200 and covering the bottom and sidewalls of the trench 100a having a certain depth formed on the silicon oxide substrate 100.
- step S3 is continued to further deepen the groove 100a having a certain depth formed on the silica substrate 100.
- Step S2 and step S3 are repeatedly performed until a second groove having a predetermined aspect ratio is formed on the silicon oxide substrate 100.
- step S1 may include:
- the specific composition of the passivation layer 300 is a deposition process gas which can form the passivation layer 300 by plasma physical deposition at a low temperature.
- the deposition process gas can be deposited to form the passivation layer 300, preferably, in step S2, the silicon dioxide substrate is cooled, and the temperature of the cooler of the process chamber is set between -20 and 0 °C. .
- step S2 a gaseous fluorocarbon is introduced into a process chamber in which an etching process is performed, so that a gaseous fluorocarbon is deposited to form a fluorocarbon polymer layer, and the fluorocarbon polymerization is performed.
- the layer of matter is the passivation layer 300.
- step S2 The composition of the deposition process gas that can be physically deposited according to the plasma in step S2
- the duration of step S2 is determined, and likewise, the duration of step S3 can be determined based on the composition of the etching gas in step S3.
- the specific component of the gaseous fluorocarbon is also not particularly limited.
- the gaseous fluorocarbon includes a CxFy compound and/or a CHxFy compound.
- the gaseous fluorocarbon may include CF 4 , C 4 . Any one of F 8 , C 5 F 8 , CHF 3 , CH 2 F 2 or a combination of any of several.
- the higher the carbon content in the gas the easier it is to form a fluorocarbon polymer.
- step S2 the flow rate of the gaseous fluorocarbon is 20 to 200 sccm. In this case, preferably, step S2 lasts for 100 to 200 s.
- the power of the lower electrode is not excessively high, thereby facilitating the deposition of a gaseous fluorocarbon.
- the power of the lower electrode is 0 to 10 W.
- the composition of the main etching gas is not specifically limited.
- the main etching gas is a fluorine-containing gas.
- the main etching gas may include The same gaseous fluorocarbon as step S2.
- the main etching gas of the step S3 includes the same gaseous fluorocarbon as the step S2, it is more convenient to control the passage of the process gas (including the deposition process gas and the main etching gas), further reducing the etching method. cost.
- the main etching gas may further include an F-based gas other than a gaseous fluorocarbon, and for example, the F-based gas may include SF 6 .
- the main etching gas may also be a mixed gas of SF 6 and a gaseous fluorocarbon for forming the passivation layer 300.
- the direction of motion usually during the etching process, maintains a lower air pressure in the process chamber.
- the pressure in the process chamber is 2.5 to 15 mT. Further preferably, in step S3, the pressure in the process chamber is 2.5 to 7 mT.
- the flow rate of the main etching gas may be 20-200 sccm.
- step S3 lasts for 200 s to 400 s.
- step S3 it is preferred to use a higher lower electrode power to ensure the direction and energy of the plasma bombardment to obtain a higher longitudinal etch rate.
- the lower electrode power is 200 to 1000 W.
- the lower electrode power is 400 to 850 W.
- an auxiliary etching gas is also used, and the auxiliary etching gas is a gas which does not react with the silica substrate 100 after being plasma-etched. .
- the impact of the auxiliary etching gas on the silica substrate 100 can promote the cleavage of the silicon-oxygen bonds in the silicon oxide substrate 100, thereby accelerating the etching rate.
- the auxiliary etching gas includes any one of argon gas, helium gas, and nitrogen gas, or a mixture of any of several. Since the molecular weight of argon gas is large, the impact force after plasma ionization is also large. Therefore, it is further preferred that the auxiliary etching gas may be argon gas.
- step S2 the pressure in the process chamber is 20 mT, the power of the upper electrode is 2500 W, the power of the lower electrode is 0 W, and the process gas for plasma physical deposition is gaseous C. 4 F 8 , C 4 F 8 flow rate is 100 sccm, cooler temperature is 0 ° C, and the duration of each step S2 is 120 s.
- step S3 the pressure in the process chamber is 5 mT, the power of the upper electrode is 2500 W, the power of the lower electrode is 500 W, the main etching gas is C 4 F 8 , the flow rate of C 4 F 8 is 100 sccm, and the auxiliary etching gas is argon gas.
- the flow rate of the argon gas was 100 sccm, the temperature of the cooler was 40 ° C, and the duration of each step S3 was 300 s.
- a second trench having an aspect ratio greater than 3:1 can be obtained on the silica substrate 100 using the preferred embodiment described above.
- an etching apparatus for performing the above etching method, the etching apparatus for etching a silicon oxide substrate 100, wherein the etching apparatus includes a control module, and a temperature An adjustment module, a gas selection module, a deposition process gas source, and an etch gas source.
- the control module controls the temperature adjustment module to cool the silicon dioxide substrate 100, and controls the gas selection module to open the deposition process gas source to the process.
- a deposition process gas is introduced into the cavity to form a passivation layer 300 at the sidewalls and bottom of the first trench 200a.
- the control module controls the temperature adjustment module to heat the silicon dioxide substrate 100, and controls the gas selection module to open the etching gas source to pass an etching gas into the process chamber to etch the bottom of the first trench 200a.
- the control module controls the temperature adjustment module to alternately heat and cool the silicon dioxide substrate 100 until a position corresponding to the first trench 200a on the silicon oxide substrate 100 forms a second trench having a predetermined aspect ratio.
- the temperature adjustment module can be connected to the cooler in the process chamber.
- step S2 the temperature adjustment module adjusts the temperature of the cooler to -20 to 0 ° C according to the signal sent by the control module; when performing step S3, the temperature The regulating module adjusts the temperature of the cooler to between 40 and 70 ° C according to the signal from the control module.
- the deposition process gas source and the etching gas source may be mutually independent gas sources providing two different gases; or may be the same gas source capable of providing gaseous fluorocarbons.
- the etch gas source may include an auxiliary etch gas source that provides an auxiliary etch gas and a main etch gas source that supplies the main etch gas.
- the process chamber of the etching apparatus in the process chamber of the etching apparatus provided by the present invention, only the silicon dioxide substrate needs to be cooled and proceeded when performing the foregoing step S2.
- the deposition process gas is introduced into the process chamber of the etching method.
- the sidewalls and the bottom of one trench form a passivation layer, and the passivation layer is not required to be formed by chemical vapor deposition. Therefore, the process chamber does not need to have a structure for chemical vapor deposition, and the foregoing etching apparatus can be used to perform the foregoing.
- step S2 and step S3 there is no need to perform other additional structural improvements to the process chamber for performing step S2. Therefore, the etching apparatus provided by the invention has a simple structure and a low cost.
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Abstract
Description
Claims (11)
- 一种二氧化硅基片的刻蚀方法,其特征在于,该刻蚀方法包括:S1、在所述二氧化硅基片表面形成掩膜图形,所述掩膜图形包括第一槽;S2、对所述二氧化硅基片进行降温,并向工艺腔内通入沉积工艺气体,以在所述第一槽的侧壁和底部形成钝化层;S3、对所述二氧化硅基片进行升温,并向所述工艺腔内通入主刻蚀气体,以对所述第一槽的底部进行刻蚀;重复执行步骤S2和步骤S3,,直至所述二氧化硅基片上对应于所述第一槽的位置形成具有预定深宽比的第二槽为止。
- 根据权利要求1所述的二氧化硅基片的刻蚀方法,其特征在于,在所述步骤S2中,对所述二氧化硅基片进行降温的温度设置在-20~0℃之间。
- 根据权利要求1所述的二氧化硅基片的刻蚀方法,其特征在于,在所述步骤S3中,对所述二氧化硅基片进行升温的温度设置在40~70℃之间。
- 根据权利要求1所述的二氧化硅基片的刻蚀方法,其特征在于,在所述步骤S2中,所述沉积工艺气体包括气态的碳氟化合物,所述钝化层为碳氟聚合物层。
- 根据权利要求4所述的二氧化硅基片的刻蚀方法,其特征在于,在所述步骤S3中,所述主刻蚀气体包括与所述步骤S2相同的所述气态的碳氟化合物。
- 根据权利要求4或5所述的二氧化硅基片的刻蚀方法,其特征在于,所述气态的碳氟化合物包括CxFy化合物和/或CHxFy化合物。
- 根据权利要求6所述的二氧化硅基片的刻蚀方法,其特征在于,所述气态的碳氟化合物包括CF4、C4F8、C5F8、CHF3、CH2F2中的任意一种或任意几种的组合。
- 根据权利要求5所述的二氧化硅基片的刻蚀方法,其特征在于,所述步骤S2中,下电极功率为0~10W;所述步骤S3中,下电极功率为200~1000W。
- 根据权利要求5所述的二氧化硅基片的刻蚀方法,其特征在于,在所述步骤S3中,所述主刻蚀气体还包括除所述气态的碳氟化合物之外的F基气体,所述F基气体包括SF6。
- 根据权利要求5所述的二氧化硅基片的刻蚀方法,其特征在于,在所述步骤S3中,还通入辅助刻蚀气体,所述辅助刻蚀气体包括氩气、氦气和氮气中的任意一种或者任意几种的混合。
- 一种刻蚀设备,用于刻蚀二氧化硅基片,其特征在于,所述刻蚀设备包括控制模块、温度调节模块、气体选择模块、沉积工艺气体源和刻蚀气体源,当所述二氧化硅基片上形成包括第一槽的掩膜图形后,所述控制模块控制所述温度调节模块对所述二氧化硅基片进行降温,并控制所述气体选择模块打开所述沉积工艺气体源以向工艺腔内通入沉积工艺气体,以在所述第一槽的侧壁和底部形成钝化层;所述控制模块控制所述温度调节模块对所述二氧化硅基片进行升温,并控制所述气体选择模块打开所述刻蚀气体源以向工艺腔内通入刻蚀气体,以对所述第一槽的底部进行刻蚀;所述控制模块控制所述温度调节模块交替地对所述二氧化硅基片进行升温、降温,直至所述二氧化硅基片上对应于所述第一槽的位置形成具有预定深宽比的第二槽为止。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019102483A (ja) * | 2017-11-28 | 2019-06-24 | 東京エレクトロン株式会社 | エッチング方法およびエッチング装置 |
CN114664649A (zh) * | 2022-05-19 | 2022-06-24 | 浙江大学杭州国际科创中心 | 碳化硅高深宽比槽刻蚀工艺优化方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11171011B2 (en) | 2018-08-21 | 2021-11-09 | Lam Research Corporation | Method for etching an etch layer |
TW202117847A (zh) * | 2019-07-17 | 2021-05-01 | 美商得昇科技股份有限公司 | 使用沉積製程和蝕刻製程的工件處理 |
JP7382578B2 (ja) * | 2019-12-27 | 2023-11-17 | パナソニックIpマネジメント株式会社 | プラズマ処理方法および素子チップの製造方法 |
CN111952169A (zh) * | 2020-08-21 | 2020-11-17 | 北京北方华创微电子装备有限公司 | 聚酰亚胺刻蚀方法 |
CN113451126B (zh) * | 2021-07-07 | 2024-02-27 | 北京北方华创微电子装备有限公司 | 晶圆刻蚀方法 |
CN114685057A (zh) * | 2022-03-30 | 2022-07-01 | 广东佛智芯微电子技术研究有限公司 | 一种玻璃基板的纳米金属诱导蚀刻方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5501893A (en) * | 1992-12-05 | 1996-03-26 | Robert Bosch Gmbh | Method of anisotropically etching silicon |
CN101379600A (zh) * | 2006-02-01 | 2009-03-04 | 阿尔卡特朗讯公司 | 各向异性刻蚀方法 |
CN103700621A (zh) * | 2013-12-27 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | 一种高深宽比垂直玻璃通孔的刻蚀方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0612767B2 (ja) * | 1984-01-25 | 1994-02-16 | 株式会社日立製作所 | 溝およびそのエッチング方法 |
JP3208596B2 (ja) * | 1992-04-01 | 2001-09-17 | ソニー株式会社 | ドライエッチング方法 |
JPH09232281A (ja) * | 1996-02-26 | 1997-09-05 | Sony Corp | ドライエッチング処理方法 |
JP4153606B2 (ja) * | 1998-10-22 | 2008-09-24 | 東京エレクトロン株式会社 | プラズマエッチング方法およびプラズマエッチング装置 |
JP2000156367A (ja) * | 1998-11-19 | 2000-06-06 | Sony Corp | ドライエッチング方法 |
JP2000164571A (ja) * | 1998-11-27 | 2000-06-16 | Sony Corp | コンタクトホール形成方法およびプラズマエッチング方法 |
JP4221859B2 (ja) * | 1999-02-12 | 2009-02-12 | 株式会社デンソー | 半導体装置の製造方法 |
KR100327346B1 (ko) * | 1999-07-20 | 2002-03-06 | 윤종용 | 선택적 폴리머 증착을 이용한 플라즈마 식각방법 및 이를이용한 콘택홀 형성방법 |
JP2002110647A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP3773785B2 (ja) * | 2000-11-24 | 2006-05-10 | 株式会社東芝 | 半導体装置の製造方法 |
US7169695B2 (en) * | 2002-10-11 | 2007-01-30 | Lam Research Corporation | Method for forming a dual damascene structure |
GB0401622D0 (en) * | 2004-01-26 | 2004-02-25 | Oxford Instr Plasma Technology | Plasma etching process |
US7273815B2 (en) * | 2005-08-18 | 2007-09-25 | Lam Research Corporation | Etch features with reduced line edge roughness |
EP1804281B1 (en) * | 2005-12-28 | 2011-12-14 | STMicroelectronics Srl | Process for digging a deep trench in a semiconductor body and semiconductor body so obtained |
JP2008244224A (ja) * | 2007-03-28 | 2008-10-09 | Sumitomo Precision Prod Co Ltd | プラズマ処理装置 |
WO2008153674A1 (en) * | 2007-06-09 | 2008-12-18 | Boris Kobrin | Method and apparatus for anisotropic etching |
CN101800175B (zh) * | 2010-02-11 | 2011-07-20 | 中微半导体设备(上海)有限公司 | 一种含硅绝缘层的等离子刻蚀方法 |
JP5981106B2 (ja) * | 2011-07-12 | 2016-08-31 | 東京エレクトロン株式会社 | プラズマエッチング方法 |
GB201611652D0 (en) * | 2016-07-04 | 2016-08-17 | Spts Technologies Ltd | Method of detecting a condition |
-
2014
- 2014-12-04 CN CN201410742698.4A patent/CN105719965A/zh active Pending
-
2015
- 2015-12-01 WO PCT/CN2015/096128 patent/WO2016086841A1/zh active Application Filing
- 2015-12-01 KR KR1020177018336A patent/KR102082803B1/ko active IP Right Grant
- 2015-12-01 JP JP2017528933A patent/JP6423534B2/ja active Active
- 2015-12-01 SG SG11201704068YA patent/SG11201704068YA/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5501893A (en) * | 1992-12-05 | 1996-03-26 | Robert Bosch Gmbh | Method of anisotropically etching silicon |
CN101379600A (zh) * | 2006-02-01 | 2009-03-04 | 阿尔卡特朗讯公司 | 各向异性刻蚀方法 |
CN103700621A (zh) * | 2013-12-27 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | 一种高深宽比垂直玻璃通孔的刻蚀方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019102483A (ja) * | 2017-11-28 | 2019-06-24 | 東京エレクトロン株式会社 | エッチング方法およびエッチング装置 |
CN114664649A (zh) * | 2022-05-19 | 2022-06-24 | 浙江大学杭州国际科创中心 | 碳化硅高深宽比槽刻蚀工艺优化方法 |
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