WO2016029616A1 - 基于五项最简混沌系统的无平衡点四维超混沌系统及模拟电路 - Google Patents

基于五项最简混沌系统的无平衡点四维超混沌系统及模拟电路 Download PDF

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WO2016029616A1
WO2016029616A1 PCT/CN2015/000260 CN2015000260W WO2016029616A1 WO 2016029616 A1 WO2016029616 A1 WO 2016029616A1 CN 2015000260 W CN2015000260 W CN 2015000260W WO 2016029616 A1 WO2016029616 A1 WO 2016029616A1
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pin
resistor
operational amplifier
multiplier
pins
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王忠林
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王忠林
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

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  • the invention relates to a chaotic system and an analog circuit, in particular to an unbalanced point four-dimensional hyperchaotic system and an analog circuit based on a five-term minimal chaotic system.
  • the existing hyperchaotic system is generally based on a three-dimensional chaotic system with three equilibrium points, adding one dimension to form a four-dimensional hyperchaotic system with at least one equilibrium point, and a four-dimensional hyperchaotic system without balance points.
  • the present invention proposes a four-dimensional hyperchaotic system with no balance point based on the five simplest three-dimensional chaotic systems, and implements it with analog circuits, which provides a chaotic system for communication and other engineering fields. New methods and ideas.
  • the technical problem to be solved by the present invention is to provide a non-equilibrium hyperchaotic system and an analog circuit based on a five-term minimal chaotic system, and the present invention adopts the following technical means to achieve the object of the invention:
  • a four-dimensional hyperchaotic system based on a five-minimum system without balance point characterized in that it comprises the following steps:
  • the analog circuit system is constructed, and the multiplier U3 and U4 are used to realize the multiplication operation by using the operational amplifier U1, the operational amplifier U2, and the resistor and the capacitor to form an inverting adder and an inverting integrator.
  • the operational amplifier U1 is connected to an operational amplifier U2, which is connected to a multiplier U4, a DC power supply, and an operational amplifier U1.
  • the multiplier U3 is connected to an operational amplifier U1, and the multiplier U4 is connected to an operational amplifier U2.
  • the 8V DC power supply is connected to the operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the second pin through the resistor R7, and is connected to the sixth pin through the resistor R9, and the third, fifth, ten, and 12th pins are grounded, and the fourth pin is connected to the VCC.
  • the eleventh pin is connected to VEE
  • the sixth pin is connected to the seventh pin through the capacitor C2
  • the seventh pin is connected to the output y
  • the third pin is connected through the resistor R1
  • the first sum of the multiplier U4 is connected.
  • the third pin, the eighth pin outputs x is connected to the ninth pin through the capacitor C1, is connected to the ninth pin through the resistor R4, and is connected to the sixth pin of the U2 through the resistor R14, and is connected to the multiplier
  • the first pin of U3, the 13th pin is connected to the 14th pin through the resistor R2, and the 14th pin is connected to the 9th pin through the resistor R5;
  • the first and second pins of the operational amplifier U2 are left floating, the third, fifth, tenth, and 12th pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin is connected to the capacitor C4 and the seventh.
  • the pin is connected, the 7th pin outputs w, the second pin of U1 is connected through the resistor R6, the 13th pin of U1 is connected through the resistor R3, the output pin z is connected to the 8th pin, and the multiplier U3 is connected.
  • the third pin, the ninth pin is connected to the eighth pin through the capacitor C3, and is grounded after the 8V DC power supply is connected through the resistor R12.
  • the 13th pin is connected to the 14th pin through the resistor R11, the 14th pin. Connected to the 9th pin through the resistor R13;
  • the first pin of the multiplier U3 is connected to the eighth pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh reference The pin is connected to the sixth pin of U1 through the resistor R8, and the eighth pin is connected to VCC;
  • the first and third pins of the multiplier U4 are connected to the seventh pin of U1, the second, fourth, and sixth pins are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to U2 through the resistor R10. Pin, the 8th pin is connected to VCC.
  • An analog circuit based on a five-minimum system of a balanced-free four-dimensional hyperchaotic system characterized in that it consists of an operational amplifier U1, an operational amplifier U2, a multiplier U3, a multiplier U4, and an 8V DC power supply.
  • the amplifier U1 is connected to an operational amplifier U2, which is connected to a multiplier U4, a DC power supply, and an operational amplifier U1.
  • the multiplier U3 is connected to an operational amplifier U1, and the multiplier U4 is connected to an operational amplifier U2.
  • the 8V DC power supply is connected to the operational amplifier U2, the operational amplifier U1 and the operational amplifier U2 are LF347N, and the multipliers U3 and U4 are AD633JN;
  • the first pin of the operational amplifier U1 is connected to the second pin through the resistor R7, and is connected to the sixth pin through the resistor R9, and the third, fifth, ten, and 12th pins are grounded, and the fourth pin is connected to the VCC.
  • the eleventh pin is connected to VEE
  • the sixth pin is connected to the seventh pin through the capacitor C2
  • the seventh pin is connected to the output y
  • the third pin is connected through the resistor R1
  • the first sum of the multiplier U4 is connected.
  • the third pin, the eighth pin outputs x is connected to the ninth pin through the capacitor C1, is connected to the ninth pin through the resistor R4, and is connected to the sixth pin of the U2 through the resistor R14, and is connected to the multiplier
  • the first pin of U3, the 13th pin is connected to the 14th pin through the resistor R2, and the 14th pin is connected to the 9th pin through the resistor R5;
  • the first and second pins of the operational amplifier U2 are left floating, the third, fifth, tenth, and 12th pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin is connected to the capacitor C4 and the seventh.
  • the pins are connected, the 7th pin outputs w, and the resistor is passed through R6 is connected to the second pin of U1, connected to the 13th pin of U1 through the resistor R3, the output pin z is connected to the 8th pin, and the 3rd pin of the multiplier U3 is connected, and the 9th pin passes through the capacitor C3 and
  • the 8th pin is connected, grounded through the resistor R12 and connected to the 8V DC power supply, the 13th pin is connected to the 14th pin through the resistor R11, and the 14th pin is connected to the 9th pin through the resistor R13;
  • the first pin of the multiplier U3 is connected to the eighth pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh reference The pin is connected to the sixth pin of U1 through the resistor R8, and the eighth pin is connected to VCC;
  • the first and third pins of the multiplier U4 are connected to the seventh pin of U1, the second, fourth, and sixth pins are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to U2 through the resistor R10. Pin, the 8th pin is connected to VCC.
  • the beneficial result of the invention is that on the basis of the five simplest three-dimensional chaotic systems, a four-dimensional hyperchaotic system without balance points is proposed and implemented by analog circuits, which provides a chaotic system for engineering fields such as communication. New methods and ideas.
  • FIG. 1 is a schematic diagram of a circuit connection structure according to a preferred embodiment of the present invention.
  • a four-dimensional hyperchaotic system based on a five-minimum system without balance point characterized in that it comprises the following steps:
  • the analog circuit system is constructed, and the multiplier U3 and U4 are used to realize the multiplication operation by using the operational amplifier U1, the operational amplifier U2, and the resistor and the capacitor to form an inverting adder and an inverting integrator.
  • the 8V DC power supply implements a constant input, and the operational amplifier U1 and the operational amplifier U2 adopt LF347N, and the multiplier U3 And U4 adopts AD633JN;
  • the operational amplifier U1 is connected to an operational amplifier U2, which is connected to a multiplier U4, a DC power supply, and an operational amplifier U1.
  • the multiplier U3 is connected to an operational amplifier U1, and the multiplier U4 is connected to an operational amplifier U2.
  • the 8V DC power supply is connected to the operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the second pin through the resistor R7, and is connected to the sixth pin through the resistor R9, and the third, fifth, ten, and 12th pins are grounded, and the fourth pin is connected to the VCC.
  • the eleventh pin is connected to VEE
  • the sixth pin is connected to the seventh pin through the capacitor C2
  • the seventh pin is connected to the output y
  • the third pin is connected through the resistor R1
  • the first sum of the multiplier U4 is connected.
  • the third pin, the eighth pin outputs x is connected to the ninth pin through the capacitor C1, is connected to the ninth pin through the resistor R4, and is connected to the sixth pin of the U2 through the resistor R14, and is connected to the multiplier
  • the first pin of U3, the 13th pin is connected to the 14th pin through the resistor R2, and the 14th pin is connected to the 9th pin through the resistor R5;
  • the first and second pins of the operational amplifier U2 are left floating, the third, fifth, tenth, and 12th pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin is connected to the capacitor C4 and the seventh.
  • the pin is connected, the 7th pin outputs w, the second pin of U1 is connected through the resistor R6, the 13th pin of U1 is connected through the resistor R3, the output pin z is connected to the 8th pin, and the multiplier U3 is connected.
  • the third pin, the ninth pin is connected to the eighth pin through the capacitor C3, and is grounded after the 8V DC power supply is connected through the resistor R12.
  • the 13th pin is connected to the 14th pin through the resistor R11, the 14th pin. Connected to the 9th pin through the resistor R13;
  • the first pin of the multiplier U3 is connected to the eighth pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh reference The pin is connected to the sixth pin of U1 through the resistor R8, and the eighth pin is connected to VCC;
  • the first and third pins of the multiplier U4 are connected to the seventh pin of U1, the second, fourth, and sixth pins are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to U2 through the resistor R10. Pin, the 8th pin is connected to VCC.
  • An analog circuit based on a five-minimum system of a balanced-free four-dimensional hyperchaotic system characterized in that it consists of an operational amplifier U1, an operational amplifier U2, a multiplier U3, a multiplier U4, and an 8V DC power supply.
  • the amplifier U1 is connected to an operational amplifier U2, which is connected to a multiplier U4, a DC power supply, and an operational amplifier U1.
  • the multiplier U3 is connected to an operational amplifier U1, and the multiplier U4 is connected to an operational amplifier U2.
  • the 8V DC power supply is connected to the operational amplifier U2, the operational amplifier U1 and the operational amplifier U2 are LF347N, and the multipliers U3 and U4 are AD633JN;
  • the first pin of the operational amplifier U1 is connected to the second pin through the resistor R7, and is connected to the sixth pin through the resistor R9, and the third, fifth, ten, and 12th pins are grounded, and the fourth pin is connected to the VCC.
  • the eleventh pin is connected to VEE
  • the sixth pin is connected to the seventh pin through the capacitor C2
  • the seventh pin is connected to the output y
  • the third pin is connected through the resistor R1
  • the third pin, the eighth pin outputs x is connected to the ninth pin through the capacitor C1, and is connected to the ninth pin through the resistor R4.
  • the first and second pins of the operational amplifier U2 are left floating, the third, fifth, tenth, and 12th pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin is connected to the capacitor C4 and the seventh.
  • the pin is connected, the 7th pin outputs w, the second pin of U1 is connected through the resistor R6, the 13th pin of U1 is connected through the resistor R3, the output pin z is connected to the 8th pin, and the multiplier U3 is connected.
  • the third pin, the ninth pin is connected to the eighth pin through the capacitor C3, and is grounded after the 8V DC power supply is connected through the resistor R12.
  • the 13th pin is connected to the 14th pin through the resistor R11, the 14th pin. Connected to the 9th pin through the resistor R13;
  • the first pin of the multiplier U3 is connected to the eighth pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh reference The pin is connected to the sixth pin of U1 through the resistor R8, and the eighth pin is connected to VCC;
  • the first and third pins of the multiplier U4 are connected to the seventh pin of U1, the second, fourth, and sixth pins are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to U2 through the resistor R10. Pin, the 8th pin is connected to VCC.

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Abstract

提供一种基于五项最简三维混沌系统的无平衡点四维超混沌系统及模拟电路，利用运算放大器(U1)、运算放大器(U2)及电阻和电容构成反相加法器和反相积分器，利用乘法器(U3)和(U4)实现乘法运算，利用8V直流电源实现常数输入，所述运算放大器(U1)和运算放大器(U2)采用LF347N，所述乘法器(U3)和(U4)采用AD633JN，所述运算放大器(U1)连接运算放大器(U2)、乘法器(U3)，所述运算放大器(U2)连接乘法器(U4)、直流电源和运算放大器(U1)，所述乘法器(U3)连接运算放大器(U1)，所述乘法器(U4)连接运算放大器(U2)，所述8V直流电源连接运算放大器(U2)，在五项最简三维混沌系统的基础上，提出了一个无平衡点的四维超混沌系统，并用模拟电路进行了实现，为混沌系统应用于通信等工程领域提供了一种新的方法和思路。

Description

基于五项最简混沌系统的无平衡点四维超混沌系统及模拟电路 技术领域
本发明涉及一个混沌系统及模拟电路，特别涉及一个基于五项最简混沌系统的无平衡点四维超混沌系统及模拟电路。
背景技术
目前，已有的超混沌系统一般是在具有三个平衡点的三维混沌系统的基础上，增加一维，形成具有至少有一个平衡点的四维超混沌系统，无平衡点的四维超混沌系统还没有被提出，本发明在五项最简三维混沌系统的基础上，提出了一个无平衡点的四维超混沌系统，并用模拟电路进行了实现，为混沌系统应用于通信等工程领域提供了一种新的方法和思路。
发明内容
本发明要解决的技术问题是提供一种基于五项最简混沌系统的无平衡点超混沌系统及模拟电路，本发明采用如下技术手段实现发明目的：
1、基于五项最简系统的无平衡点四维超混沌系统，其特征是在于，包括以下步骤：
(1)五项最简三维混沌混沌系统i为：
Figure PCTCN2015000260-appb-000001
(2)在三维混沌系统i的基础上，增加一个微分方程dw/dt＝-kx，并把w反馈到系统i的第一和第二个方程上，获得混沌系统ii
Figure PCTCN2015000260-appb-000002
(3)根据无平衡点超混沌系统ii构造模拟电路系统，利用运算放大器U1、运算放大器U2及电阻和电容构成反相加法器和反相积分器，利用乘法器U3和U4实现乘法运算，利用8V直流电源实现常数输入，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3和U4采用AD633JN；
所述运算放大器U1连接运算放大器U2、乘法器U3，所述运算放大器U2连接乘法器U4、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2，所述8V直流电源连接运算放大器U2；
所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R9与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R1与第13引脚相接，接乘法器U4的第1和第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，通过电阻R4与第9引脚相接，通过电阻R14与U2的第6引脚相接，接乘法器U3的第1引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R5与第9引脚相接；
所述运算放大器U2的第1、2引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R6与U1的第2引脚相接，通过电阻R3与U1的第13引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接8V直流电源后接地，第13引脚通过电阻R11与第14引脚相接，第14引脚通过电阻R13与第9引脚相接；
所述乘法器U3的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R8接U1第6引脚，第8引脚接VCC；
所述乘法器U4的第1、3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接U2第13引脚，第8引脚接VCC。
2、基于五项最简系统的无平衡点四维超混沌系统的模拟电路，其特征是在于，由运算放大器U1、运算放大器U2和乘法器U3、乘法器U4及8V直流电源组成，所述运算放大器U1连接运算放大器U2、乘法器U3，所述运算放大器U2连接乘法器U4、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2，所述8V直流电源连接运算放大器U2，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3和U4采用AD633JN；
所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R9与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R1与第13引脚相接，接乘法器U4的第1和第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，通过电阻R4与第9引脚相接，通过电阻R14与U2的第6引脚相接，接乘法器U3的第1引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R5与第9引脚相接；
所述运算放大器U2的第1、2引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻 R6与U1的第2引脚相接，通过电阻R3与U1的第13引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接8V直流电源后接地，第13引脚通过电阻R11与第14引脚相接，第14引脚通过电阻R13与第9引脚相接；
所述乘法器U3的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R8接U1第6引脚，第8引脚接VCC；
所述乘法器U4的第1、3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接U2第13引脚，第8引脚接VCC。
有益效果
本发明的有益果是：在五项最简三维混沌系统的基础上，提出了一个无平衡点的四维超混沌系统，并用模拟电路进行了实现，为混沌系统应用于通信等工程领域提供了一种新的方法和思路。
附图说明
图1为本发明优选实施例的电路连接结构示意图。
图2和图3为本发明的电路实际连接图。
具体实施方式
下面结合附图和优选实施例对本发明作更进一步的详细描述，参见图1-图3。
1、基于五项最简系统的无平衡点四维超混沌系统，其特征是在于，包括以下步骤：
(1)五项最简三维混沌混沌系统i为：
Figure PCTCN2015000260-appb-000003
(2)在三维混沌系统i的基础上，增加一个微分方程dw/dt＝-kx，并把w反馈到系统i的第一和第二个方程上，获得混沌系统ii
Figure PCTCN2015000260-appb-000004
(3)根据无平衡点超混沌系统ii构造模拟电路系统，利用运算放大器U1、运算放大器U2及电阻和电容构成反相加法器和反相积分器，利用乘法器U3和U4实现乘法运算，利用8V直流电源实现常数输入，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3 和U4采用AD633JN；
所述运算放大器U1连接运算放大器U2、乘法器U3，所述运算放大器U2连接乘法器U4、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2，所述8V直流电源连接运算放大器U2；
所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R9与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R1与第13引脚相接，接乘法器U4的第1和第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，通过电阻R4与第9引脚相接，通过电阻R14与U2的第6引脚相接，接乘法器U3的第1引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R5与第9引脚相接；
所述运算放大器U2的第1、2引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R6与U1的第2引脚相接，通过电阻R3与U1的第13引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接8V直流电源后接地，第13引脚通过电阻R11与第14引脚相接，第14引脚通过电阻R13与第9引脚相接；
所述乘法器U3的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R8接U1第6引脚，第8引脚接VCC；
所述乘法器U4的第1、3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接U2第13引脚，第8引脚接VCC。
2、基于五项最简系统的无平衡点四维超混沌系统的模拟电路，其特征是在于，由运算放大器U1、运算放大器U2和乘法器U3、乘法器U4及8V直流电源组成，所述运算放大器U1连接运算放大器U2、乘法器U3，所述运算放大器U2连接乘法器U4、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2，所述8V直流电源连接运算放大器U2，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3和U4采用AD633JN；
所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R9与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R1与第13引脚相接，接乘法器U4的第1和第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，通过电阻R4与第9引脚相 接，通过电阻R14与U2的第6引脚相接，接乘法器U3的第1引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R5与第9引脚相接；
所述运算放大器U2的第1、2引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R6与U1的第2引脚相接，通过电阻R3与U1的第13引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接8V直流电源后接地，第13引脚通过电阻R11与第14引脚相接，第14引脚通过电阻R13与第9引脚相接；
所述乘法器U3的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R8接U1第6引脚，第8引脚接VCC；
所述乘法器U4的第1、3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接U2第13引脚，第8引脚接VCC。
电路中电阻R2＝R5＝R7＝R9＝R11＝R13＝10kΩ，R3＝R6＝R12＝100kΩ，R1＝R4＝4.54kΩ，R8＝R10＝1kΩ，R14＝28.5kΩ，C1＝C2＝C3＝C4＝10nF。
当然，上述说明并非对本发明的限制，本发明也不仅限于上述举例，本技术领域的普通技术人员在本发明的实质范围内所做出的变化、改型、添加或替换，也属于本发明的保护范围。

Claims (2)

  1. 基于五项最简系统的无平衡点四维超混沌系统，其特征是在于，包括以下步骤：
    (1)五项最简三维混沌混沌系统i为：
    Figure PCTCN2015000260-appb-100001
       a＝5，b＝90
    (2)在三维混沌系统i的基础上，增加一个微分方程dw/dt＝-kx，并把w反馈到系统i的第一和第二个方程上，获得混沌系统ii
    Figure PCTCN2015000260-appb-100002
       a＝22，b＝80，k＝3.5
    (3)根据无平衡点超混沌系统ii构造模拟电路系统，利用运算放大器U1、运算放大器U2及电阻和电容构成反相加法器和反相积分器，利用乘法器U3和U4实现乘法运算，利用8V直流电源实现常数输入，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3和U4采用AD633JN；
    所述运算放大器U1连接运算放大器U2、乘法器U3，所述运算放大器U2连接乘法器U4、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2，所述8V直流电源连接运算放大器U2；
    所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R9与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R1与第13引脚相接，接乘法器U4的第1和第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，通过电阻R4与第9引脚相接，通过电阻R14与U2的第6引脚相接，接乘法器U3的第1引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R5与第9引脚相接；
    所述运算放大器U2的第1、2引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R6与U1的第2引脚相接，通过电阻R3与U1的第13引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接8V直流电源后接地，第13引脚通过电阻R11与第14引脚相接，第14引脚通过电阻R13与第9引脚相接；
    所述乘法器U3的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R8接U1第6引脚，第8引脚接VCC；
    所述乘法器U4的第1、3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接U2第13引脚，第8引脚接VCC。
  2. 基于五项最简系统的无平衡点四维超混沌系统的模拟电路，其特征是在于，由运算放大器U1、运算放大器U2和乘法器U3、乘法器U4及8V直流电源组成，所述运算放大器U1连接运算放大器U2、乘法器U3，所述运算放大器U2连接乘法器U4、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2，所述8V直流电源连接运算放大器U2，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3和U4采用AD633JN；
    所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R9与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R1与第13引脚相接，接乘法器U4的第1和第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，通过电阻R4与第9引脚相接，通过电阻R14与U2的第6引脚相接，接乘法器U3的第1引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R5与第9引脚相接；
    所述运算放大器U2的第1、2引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R6与U1的第2引脚相接，通过电阻R3与U1的第13引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接8V直流电源后接地，第13引脚通过电阻R11与第14引脚相接，第14引脚通过电阻R13与第9引脚相接；
    所述乘法器U3的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R8接U1第6引脚，第8引脚接VCC；
    所述乘法器U4的第1、3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接U2第13引脚，第8引脚接VCC。
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109543313A (zh) * 2018-11-27 2019-03-29 杭州电子科技大学 基于忆阻器反馈的超混沌系统的电路模型
CN109684747A (zh) * 2018-12-27 2019-04-26 杭州电子科技大学 一种对数型荷控忆容器等效电路模型
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CN110611560A (zh) * 2019-09-18 2019-12-24 湘潭大学 一种三维非自治混沌模型及电路
CN110896347A (zh) * 2019-12-13 2020-03-20 哈尔滨工程大学 一种具有离散分岔图的多稳定性混沌系统
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CN112152983A (zh) * 2019-06-28 2020-12-29 天津科技大学 一种具有六簇混沌流的非哈密顿系统及其电路实现
CN112152773A (zh) * 2019-06-28 2020-12-29 天津科技大学 一种三维改进型的Sprott-A混沌系统及其电路实现
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CN113505559A (zh) * 2021-08-05 2021-10-15 合肥工业大学智能制造技术研究院 一种三值理想通用压控忆阻器电路模型
CN113872749A (zh) * 2021-09-29 2021-12-31 南开大学 一种具有4簇保守混沌流的系统及电路
CN114726501A (zh) * 2022-04-25 2022-07-08 兰州大学 一种基于四维保守混沌系统的模拟电路

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104202140A (zh) * 2014-08-31 2014-12-10 王春梅 基于五项最简混沌系统的无平衡点四维超混沌系统及模拟电路
CN105119709A (zh) * 2015-09-09 2015-12-02 高建红 基于五项最简混沌系统的无平衡点四维超混沌系统自适应同步方法及电路
CN105262579A (zh) * 2015-09-09 2016-01-20 王晓红 基于Rikitake系统的无平衡点四维超混沌系统自适应同步方法及电路
CN107453860B (zh) * 2016-05-22 2020-06-05 台州市牛诺电子商务有限公司 线性化Sprott B混沌系统为二次和二次项的电路
CN113162551A (zh) * 2021-05-06 2021-07-23 湘潭大学 一种能产生新型复杂簇发现象的多频慢激励Lorenz衍生系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103684747A (zh) * 2014-01-07 2014-03-26 滨州学院 一个双层蝶形吸引子混沌发生器及电路
CN103684746A (zh) * 2014-01-03 2014-03-26 滨州学院 一个无平衡点的四维超混沌系统及模拟电路实现
CN103731256A (zh) * 2014-01-03 2014-04-16 滨州学院 一个三维无平衡点的混沌系统及模拟电路实现
CN104202140A (zh) * 2014-08-31 2014-12-10 王春梅 基于五项最简混沌系统的无平衡点四维超混沌系统及模拟电路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201726386U (zh) * 2010-07-21 2011-01-26 滨州学院 超混沌/混沌系统通用模拟电路
CN102946309B (zh) * 2012-11-19 2015-04-15 合肥工业大学 一种超混沌电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103684746A (zh) * 2014-01-03 2014-03-26 滨州学院 一个无平衡点的四维超混沌系统及模拟电路实现
CN103731256A (zh) * 2014-01-03 2014-04-16 滨州学院 一个三维无平衡点的混沌系统及模拟电路实现
CN103684747A (zh) * 2014-01-07 2014-03-26 滨州学院 一个双层蝶形吸引子混沌发生器及电路
CN104202140A (zh) * 2014-08-31 2014-12-10 王春梅 基于五项最简混沌系统的无平衡点四维超混沌系统及模拟电路

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