WO2016029619A1 - 基于Rikitake系统的无平衡点四维超混沌系统及模拟电路 - Google Patents

基于Rikitake系统的无平衡点四维超混沌系统及模拟电路 Download PDF

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WO2016029619A1
WO2016029619A1 PCT/CN2015/000264 CN2015000264W WO2016029619A1 WO 2016029619 A1 WO2016029619 A1 WO 2016029619A1 CN 2015000264 W CN2015000264 W CN 2015000264W WO 2016029619 A1 WO2016029619 A1 WO 2016029619A1
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pin
multiplier
operational amplifier
resistor
grounded
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PCT/CN2015/000264
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李敏
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李敏
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals

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  • the invention relates to a chaotic system and an analog circuit, in particular to a four-dimensional hyperchaotic system and an analog circuit based on a three-dimensional Rikitake chaotic system.
  • the existing hyperchaotic system is generally based on a three-dimensional chaotic system with three equilibrium points, adding one dimension to form a four-dimensional hyperchaotic system with at least one equilibrium point, and a four-dimensional hyperchaotic system without balance points.
  • the present invention proposes a four-dimensional hyperchaotic system without balance point based on the three-dimensional Rikitake chaotic system, and implements it with analog circuits, which provides a new method for the application of chaotic systems in communication and other engineering fields. And ideas.
  • the technical problem to be solved by the present invention is to provide a non-equilibrium hyperchaotic system and an analog circuit based on a three-dimensional Rikitake chaotic system, and the present invention adopts the following technical means to achieve the object of the invention:
  • a balanced-free four-dimensional hyperchaotic system based on the Rikitake system characterized in that it comprises the following steps:
  • the analog circuit system is constructed, and the operational amplifiers U1, U2 and the resistors and capacitors are used to form the inverting adder and the inverting integrator, and the multipliers U3, U4 and U5 are used to realize the multiplication operation.
  • 1V DC power supply to achieve constant input the operational amplifier U1 and operational amplifier U2 using LF347N, the multiplier U3, U4 and U5 using AD633JN;
  • the operational amplifier U1 is connected to an operational amplifier U2, which is connected to a multiplier U5, a 1V DC power supply and an operational amplifier U1.
  • the multiplier U3 is connected to an operational amplifier U1, and the multiplier U4 is connected.
  • An operational amplifier U1, the multiplier U5 is connected to an operational amplifier U2, and the 1V DC power supply is connected to an operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the second pin through the resistor R7, and is connected to the sixth pin of U1 through the resistor R8, and the third, fifth, ten, and 12th pins are grounded, and the fourth pin is connected.
  • the 11th pin is connected to VEE
  • the 6th pin is connected to the 7th pin of U1 through the capacitor C2
  • the 7th pin is connected to the output y
  • the 6th pin is connected through the resistor R10
  • the resistor R13 is used.
  • the 6th pin of U2 is connected, connected to the 1st pin of multiplier U3, connected to the 3rd pin of multiplier U5, the 8th pin outputs x, is connected to the 9th pin through capacitor C1, and is connected to the multiplier
  • the first pin of U4 is connected to the first pin of multiplier U5, connected to the sixth pin of U1 through resistor R9, connected to the ninth pin of U1 through resistor R4, and the third pin is passed through resistor R2.
  • the 14th pin is connected to the 9th pin through the resistor R3;
  • the first, second, thirteen, and fourteen pins of the operational amplifier U2 are left floating, the third, fifth, tenth, and twelfth pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin is passed through the capacitor.
  • C4 is connected to the 7th pin, the 7th pin outputs w, the second pin of U1 is connected through the resistor R5, the output pin is connected to the 8th pin, and the 3rd pin of the multiplier U3 is connected to the multiplier.
  • the third pin of U4, the ninth pin is connected to the eighth pin of U2 through the capacitor C3, and is grounded after being connected to the 1V power supply through the resistor R12;
  • the first pin of the multiplier U3 is connected to the seventh pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh lead The pin is connected to the 13th pin of U1 through the resistor R1, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the eighth pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh reference The pin is connected to the second pin of U1 through resistor R6, and the eighth pin is connected to VCC.
  • the first pin of the multiplier U5 is connected to the eighth pin of U1
  • the third pin is connected to the seventh pin of U1
  • the second, fourth, and sixth pins are grounded
  • the fifth pin is connected to VEE
  • the seventh lead The pin is connected to the 9th pin of U2 through the resistor R11, and the 8th pin is connected to VCC.
  • An analog circuit of a four-dimensional hyperchaotic system without a balance point based on a three-dimensional chaotic system characterized in that it is composed of operational amplifiers U1, U2 and multipliers U3, U4, U5 and 1V DC power supply;
  • the operational amplifier U1 is connected to an operational amplifier U2, which is connected to a multiplier U5, a DC power supply, and an operational amplifier U1.
  • the multiplier U3 is connected to an operational amplifier U1, and the multiplier U4 is connected to the operational amplifier U2.
  • the amplifier U1 is connected to the operational amplifier U2, the 1V DC power supply is connected to the operational amplifier U2, the operational amplifier U1 and the operational amplifier U2 are LF347D, and the multipliers U3, U4 and U5 are AD633JN;
  • the first pin of the operational amplifier U1 is connected to the second pin through the resistor R7, and is connected to the sixth pin through the resistor R8, and the third, fifth, ten, and 12th pins are grounded, and the fourth pin is connected to the VCC.
  • the 11th pin is connected to VEE
  • the 6th pin is connected to the 7th pin through the capacitor C2
  • the 7th pin is connected to the output y
  • the 6th pin is connected through the resistor R10, and the 6th through the resistor R13 and U2
  • the pin is connected, and the first pin of the multiplier U3 is connected to the third pin of the multiplier U5, and the eighth pin outputs x.
  • the over-capacitor C1 is connected to the ninth pin, and is connected to the first pin of the multiplier U4, connected to the first pin of the multiplier U5, connected to the sixth pin through the resistor R9, and passed through the resistor R4 and the ninth pin.
  • the 13th pin is connected to the 14th pin through the resistor R2
  • the 14th pin is connected to the 9th pin through the resistor R3;
  • the first, second, thirteen, and fourteen pins of the operational amplifier U2 are left floating, the third, fifth, tenth, and twelfth pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin is passed through the capacitor.
  • C4 is connected to the 7th pin, the 7th pin outputs w, the second pin of U1 is connected through the resistor R5, the output pin is connected to the 8th pin, and the 3rd pin of the multiplier U3 is connected to the multiplier.
  • the third pin of U4, the ninth pin is connected to the eighth pin through the capacitor C3, and is grounded after being connected to the 1V power supply through the resistor R12;
  • the first pin of the multiplier U3 is connected to the seventh pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh lead The pin is connected to the 13th pin of U1 through the resistor R1, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the eighth pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh reference The pin is connected to the second pin of U1 through the resistor R6, and the eighth pin is connected to VCC;
  • the first pin of the multiplier U5 is connected to the eighth pin of U1, the third pin is connected to the seventh pin of U1, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh lead The pin is connected to the 9th pin of U2 through the resistor R11, and the 8th pin is connected to VCC;
  • the beneficial result of the invention is that a four-dimensional hyperchaotic system without balance point is proposed based on the three-dimensional Rikitake chaotic system, and is realized by analog circuit, which provides a new kind of chaotic system for communication and other engineering fields. Methods and ideas.
  • FIG. 1 is a schematic diagram of a circuit connection structure according to a preferred embodiment of the present invention.
  • a balanced-free four-dimensional hyperchaotic system based on the Rikitake system characterized in that it comprises the following steps:
  • the analog circuit system is constructed, and the operational amplifiers U1, U2 and the resistors and capacitors are used to form the inverting adder and the inverting integrator, and the multipliers U3, U4 and U5 are used to realize the multiplication operation.
  • 1V DC power supply to achieve constant input the operational amplifier U1 and operational amplifier U2 using LF347N, the multiplier U3, U4 and U5 using AD633JN;
  • the operational amplifier U1 is connected to an operational amplifier U2, which is connected to a multiplier U5, a 1V DC power supply and an operational amplifier U1.
  • the multiplier U3 is connected to an operational amplifier U1, and the multiplier U4 is connected.
  • An operational amplifier U1, the multiplier U5 is connected to the operational amplifier U2, the 1V DC power supply is connected to the operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the second pin through the resistor R7, and is connected to the sixth pin of U1 through the resistor R8, and the third, fifth, ten, and 12th pins are grounded, and the fourth pin is connected.
  • the 11th pin is connected to VEE
  • the 6th pin is connected to the 7th pin of U1 through the capacitor C2
  • the 7th pin is connected to the output y
  • the 6th pin is connected through the resistor R10
  • the resistor R13 is used.
  • the 6th pin of U2 is connected, connected to the 1st pin of multiplier U3, connected to the 3rd pin of multiplier U5, the 8th pin outputs x, is connected to the 9th pin through capacitor C1, and is connected to the multiplier
  • the first pin of U4 is connected to the first pin of multiplier U5, connected to the sixth pin of U1 through resistor R9, connected to the ninth pin of U1 through resistor R4, and the third pin is passed through resistor R2.
  • the 14th pin is connected to the 9th pin through the resistor R3;
  • the first, second, thirteen, and fourteen pins of the operational amplifier U2 are left floating, the third, fifth, tenth, and twelfth pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin is passed through the capacitor.
  • C4 is connected to the 7th pin, the 7th pin outputs w, the second pin of U1 is connected through the resistor R5, the output pin is connected to the 8th pin, and the 3rd pin of the multiplier U3 is connected to the multiplier.
  • the third pin of U4, the ninth pin is connected to the eighth pin of U2 through the capacitor C3, and is grounded after being connected to the 1V power supply through the resistor R12;
  • the first pin of the multiplier U3 is connected to the seventh pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh lead The pin is connected to the 13th pin of U1 through the resistor R1, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the eighth pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh reference The pin is connected to the second pin of U1 through the resistor R6, and the eighth pin is connected to VCC;
  • the first pin of the multiplier U5 is connected to the eighth pin of U1
  • the third pin is connected to the seventh pin of U1
  • the second, fourth, and sixth pins are grounded
  • the fifth pin is connected to VEE
  • the seventh lead The pin is connected to the 9th pin of U2 through the resistor R11, and the 8th pin is connected to VCC.
  • the operational amplifier U1 is connected to an operational amplifier U2, which is connected to a multiplier U5, a DC power supply, and an operational amplifier U1.
  • the multiplier U3 is connected to an operational amplifier U1, and the multiplier U4 is connected to the operational amplifier U2.
  • the amplifier U1 is connected to the operational amplifier U2, the 1V DC power supply is connected to the operational amplifier U2, the operational amplifier U1 and the operational amplifier U2 are LF347D, and the multipliers U3, U4 and U5 are AD633JN;
  • the first pin of the operational amplifier U1 is connected to the second pin through the resistor R7, and is connected to the sixth pin through the resistor R8, and the third, fifth, ten, and 12th pins are grounded, and the fourth pin is connected to the VCC.
  • the 11th pin is connected to VEE
  • the 6th pin is connected to the 7th pin through the capacitor C2
  • the 7th pin is connected to the output y
  • the 6th pin is connected through the resistor R10, and the 6th through the resistor R13 and U2
  • the pin is connected to the first pin of the multiplier U3, the third pin of the multiplier U5, the output pin of the eighth pin is x
  • the capacitor is connected to the ninth pin through the capacitor C1, and the first of the multiplier U4 is connected.
  • the pin is connected to the first pin of the multiplier U5, connected to the sixth pin through the resistor R9, connected to the ninth pin through the resistor R4, and the 13th pin is connected to the 14th pin through the resistor R2.
  • the 14th pin is connected to the 9th pin through the resistor R3;
  • the first, second, thirteen, and fourteen pins of the operational amplifier U2 are left floating, the third, fifth, tenth, and twelfth pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin is passed through the capacitor.
  • C4 is connected to the 7th pin, the 7th pin outputs w, the second pin of U1 is connected through the resistor R5, the output pin is connected to the 8th pin, and the 3rd pin of the multiplier U3 is connected to the multiplier.
  • the third pin of U4, the ninth pin is connected to the eighth pin through the capacitor C3, and is grounded after being connected to the 1V power supply through the resistor R12;
  • the first pin of the multiplier U3 is connected to the seventh pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh lead The pin is connected to the 13th pin of U1 through the resistor R1, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the eighth pin of U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE, the seventh reference The pin is connected to the second pin of U1 through the resistor R6, and the eighth pin is connected to VCC;
  • the first pin of the multiplier U5 is connected to the eighth pin of U1
  • the third pin is connected to the seventh pin of U1
  • the second, fourth, and sixth pins are grounded
  • the fifth pin is connected to VEE
  • the seventh lead The pin is connected to the 9th pin of U2 through the resistor R11, and the 8th pin is connected to VCC.

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Abstract

一种基于三维Rikitake混沌系统的无平衡点四维超混沌系统及模拟电路，利用运算放大器U1、运算放大器U2及电阻和电容构成反相加法器和反相积分器，利用乘法器U3、U4和U5实现乘法运算，利用1V直流电源实现常数输入，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3、U4和U5采用AD633JN，所述运算放大器U1连接运算放大器U2、乘法器U3和乘法器U4，所述运算放大器U2连接乘法器U5、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U1，所述乘法器U5连接运算放大器U2，所述1V直流电源连接运算放大器U2，在三维Rikitake混沌系统的基础上，提出了一个无平衡点的四维超混沌系统，并用模拟电路进行了实现，为混沌系统应用于通信等工程领域提供了一种新的方法和思路。

Description

基于Rikitake系统的无平衡点四维超混沌系统及模拟电路 技术领域
本发明涉及一个混沌系统及模拟电路，特别涉及一个基于三维Rikitake混沌系统的无平衡点四维超混沌系统及模拟电路。
背景技术
目前，已有的超混沌系统一般是在具有三个平衡点的三维混沌系统的基础上，增加一维，形成具有至少有一个平衡点的四维超混沌系统，无平衡点的四维超混沌系统还没有被提出，本发明在三维Rikitake混沌系统的基础上，提出了一个无平衡点的四维超混沌系统，并用模拟电路进行了实现，为混沌系统应用于通信等工程领域提供了一种新的方法和思路。
发明内容
本发明要解决的技术问题是提供一种基于三维Rikitake混沌系统的无平衡点超混沌系统及模拟电路，本发明采用如下技术手段实现发明目的：
1、基于Rikitake系统的无平衡点四维超混沌系统，其特征是在于，包括以下步骤：
(1)Rikitake三维混沌系统i为：
Figure PCTCN2015000264-appb-000001
(2)在三维混沌系统i的基础上，增加一个微分方程dw/dt＝-ky，并把w反馈到系统i的第二个方程上，获得混沌系统ii
Figure PCTCN2015000264-appb-000002
(3)根据无平衡点超混沌系统ii构造模拟电路系统，利用运算放大器U1、U2及电阻和电容构成反相加法器和反相积分器，利用乘法器U3、U4和U5实现乘法运算，利用1V直流电源实现常数输入，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3、U4和U5采用AD633JN；
所述运算放大器U1连接运算放大器U2、乘法器U3和U4，所述运算放大器U2连接乘法器U5、1V直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U1，所述乘法器U5连接运算放大器U2，所述1V直流电源连接运算放大器 U2；
所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R8与U1的第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与U1的第7引脚相接，第7引脚接输出y，通过电阻R10与第6引脚相接，通过电阻R13与U2的第6引脚相接，接乘法器U3的第1引脚，接乘法器U5的第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，接乘法器U4的第1引脚，接乘法器U5的第1引脚，通过电阻R9与U1的第6引脚相接，通过电阻R4与U1的第9引脚相接，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
所述运算放大器U2的第1、2、13、14引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R5与U1的第2引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，接乘法器U4的第3引脚，第9引脚通过电容C3与U2的第8引脚相接，通过电阻R12接1V电源后接地；
所述乘法器U3的第1引脚接U1的第7脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R1接U1第13引脚，第8引脚接VCC；
所述乘法器U4的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R6接U1第2引脚，第8引脚接VCC。
所述乘法器U5的第1引脚接U1的第8脚，第3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R11接U2第9引脚，第8引脚接VCC。
2、基于三维混沌系统的无平衡点四维超混沌系统的模拟电路，其特征是在于，由运算放大器U1、U2和乘法器U3、U4、U5及1V直流电源组成；
所述运算放大器U1连接运算放大器U2、乘法器U3和U4，所述运算放大器U2连接乘法器U5、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U1，所述乘法器U5连接运算放大器U2，所述1V直流电源连接运算放大器U2，所述运算放大器U1和运算放大器U2采用LF347D，所述乘法器U3、U4和U5采用AD633JN；
所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R8与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R10与第6引脚相接，通过电阻R13与U2的第6引脚相接，接乘法器U3的第1引脚，接乘法器U5的第3引脚，第8引脚输出x，通 过电容C1与第9引脚相接，接乘法器U4的第1引脚，接乘法器U5的第1引脚，通过电阻R9与第6引脚相接，通过电阻R4与第9引脚相接，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
所述运算放大器U2的第1、2、13、14引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R5与U1的第2引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，接乘法器U4的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接1V电源后接地；
所述乘法器U3的第1引脚接U1的第7脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R1接U1第13引脚，第8引脚接VCC；
所述乘法器U4的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R6接U1第2引脚，第8引脚接VCC；
所述乘法器U5的第1引脚接U1的第8脚，第3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R11接U2第9引脚，第8引脚接VCC；
本发明的有益果是：在三维Rikitake混沌系统的基础上，提出了一个无平衡点的四维超混沌系统，并用模拟电路进行了实现，为混沌系统应用于通信等工程领域提供了一种新的方法和思路。
附图说明
图1为本发明优选实施例的电路连接结构示意图。
图2和图3为本发明的电路实际连接图。
具体实施方式
下面结合附图和优选实施例对本发明作更进一步的详细描述，参见图1-图3。
1、基于Rikitake系统的无平衡点四维超混沌系统，其特征是在于，包括以下步骤：
(1)Rikitake三维混沌混沌系统i为：
Figure PCTCN2015000264-appb-000003
(2)在三维混沌系统i的基础上，增加一个微分方程dw/dt＝-ky，并把w反馈到系统i的第二个方程上，获得混沌系统ii
Figure PCTCN2015000264-appb-000004
(3)根据无平衡点超混沌系统ii构造模拟电路系统，利用运算放大器U1、U2及电阻和电容构成反相加法器和反相积分器，利用乘法器U3、U4和U5实现乘法运算，利用1V直流电源实现常数输入，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3、U4和U5采用AD633JN；
所述运算放大器U1连接运算放大器U2、乘法器U3和U4，所述运算放大器U2连接乘法器U5、1V直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U1，所述乘法器U5连接运算放大器U2，所述1V直流电源连接运算放大器U2；
所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R8与U1的第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与U1的第7引脚相接，第7引脚接输出y，通过电阻R10与第6引脚相接，通过电阻R13与U2的第6引脚相接，接乘法器U3的第1引脚，接乘法器U5的第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，接乘法器U4的第1引脚，接乘法器U5的第1引脚，通过电阻R9与U1的第6引脚相接，通过电阻R4与U1的第9引脚相接，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
所述运算放大器U2的第1、2、13、14引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R5与U1的第2引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，接乘法器U4的第3引脚，第9引脚通过电容C3与U2的第8引脚相接，通过电阻R12接1V电源后接地；
所述乘法器U3的第1引脚接U1的第7脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R1接U1第13引脚，第8引脚接VCC；
所述乘法器U4的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R6接U1第2引脚，第8引脚接VCC；
所述乘法器U5的第1引脚接U1的第8脚，第3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R11接U2第9引脚，第8引脚接VCC。
2、基于Rikitake系统的无平衡点四维超混沌系统的模拟电路，其特征是在于，由运 算放大器U1、U2和乘法器U3、U4、U5及1V直流电源组成；
所述运算放大器U1连接运算放大器U2、乘法器U3和U4，所述运算放大器U2连接乘法器U5、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U1，所述乘法器U5连接运算放大器U2，所述1V直流电源连接运算放大器U2，所述运算放大器U1和运算放大器U2采用LF347D，所述乘法器U3、U4和U5采用AD633JN；
所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R8与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R10与第6引脚相接，通过电阻R13与U2的第6引脚相接，接乘法器U3的第1引脚，接乘法器U5的第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，接乘法器U4的第1引脚，接乘法器U5的第1引脚，通过电阻R9与第6引脚相接，通过电阻R4与第9引脚相接，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
所述运算放大器U2的第1、2、13、14引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R5与U1的第2引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，接乘法器U4的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接1V电源后接地；
所述乘法器U3的第1引脚接U1的第7脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R1接U1第13引脚，第8引脚接VCC；
所述乘法器U4的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R6接U1第2引脚，第8引脚接VCC；
所述乘法器U5的第1引脚接U1的第8脚，第3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R11接U2第9引脚，第8引脚接VCC。
电路中电阻R1＝R2＝R3＝R6＝R7＝R8＝R9＝R11＝10kΩ，R4＝R10＝50kΩ，R5＝R12＝100kΩ，R13＝33.33kΩ，C1＝C2＝C3＝C4＝10nF。
当然，上述说明并非对本发明的限制，本发明也不仅限于上述举例，本技术领域的普通技术人员在本发明的实质范围内所做出的变化、改型、添加或替换，也属于本发明的保护范围。

Claims (2)

  1. 基于Rikitake系统的无平衡点四维超混沌系统，其特征是在于，包括以下步骤：
    (1)Rikitake三维混沌混沌系统i为：
    Figure PCTCN2015000264-appb-100001
       μ＝2，a＝5
    (2)在三维混沌系统i的基础上，增加一个微分方程dw/dt＝-ky，并把w反馈到系统i的第二个方程上，获得混沌系统ii
    Figure PCTCN2015000264-appb-100002
        μ＝2，a＝40，k＝3
    (3)根据无平衡点超混沌系统ii构造模拟电路系统，利用运算放大器U1、U2及电阻和电容构成反相加法器和反相积分器，利用乘法器U3、U4和U5实现乘法运算，利用1V直流电源实现常数输入，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3、U4和U5采用AD633JN；
    所述运算放大器U1连接运算放大器U2、乘法器U3和U4，所述运算放大器U2连接乘法器U5、1V直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U1，所述乘法器U5连接运算放大器U2，所述1V直流电源连接运算放大器U2；
    所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R8与U1的第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与U1的第7引脚相接，第7引脚接输出y，通过电阻R10与第6引脚相接，通过电阻R13与U2的第6引脚相接，接乘法器U3的第1引脚，接乘法器U5的第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，接乘法器U4的第1引脚，接乘法器U5的第1引脚，通过电阻R9与U1的第6引脚相接，通过电阻R4与U1的第9引脚相接，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
    所述运算放大器U2的第1、2、13、14引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R5与U1的第2引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，接乘法器U4的第3引脚，第9引脚通过电容C3与U2的第8引脚相接，通过电阻R12接1V电源后接地；
    所述乘法器U3的第1引脚接U1的第7脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R1接U1第13引脚，第8引脚接VCC；
    所述乘法器U4的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R6接U1第2引脚，第8引脚接VCC；
    所述乘法器U5的第1引脚接U1的第8脚，第3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R11接U2第9引脚，第8引脚接VCC。
  2. 基于Rikitake系统的无平衡点四维超混沌系统的模拟电路，其特征是在于，由运算放大器U1、U2和乘法器U3、U4、U5及1V直流电源组成；
    所述运算放大器U1连接运算放大器U2、乘法器U3和U4，所述运算放大器U2连接乘法器U5、直流电源和运算放大器U1，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U1，所述乘法器U5连接运算放大器U2，所述1V直流电源连接运算放大器U2，所述运算放大器U1和运算放大器U2采用LF347D，所述乘法器U3、U4和U5采用AD633JN；
    所述运算放大器U1的第1引脚通过电阻R7与第2引脚相接，通过电阻R8与第6引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C2与第7引脚相接，第7引脚接输出y，通过电阻R10与第6引脚相接，通过电阻R13与U2的第6引脚相接，接乘法器U3的第1引脚，接乘法器U5的第3引脚，第8引脚输出x，通过电容C1与第9引脚相接，接乘法器U4的第1引脚，接乘法器U5的第1引脚，通过电阻R9与第6引脚相接，通过电阻R4与第9引脚相接，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
    所述运算放大器U2的第1、2、13、14引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚通过电容C4与第7引脚相接，第7引脚输出w，通过电阻R5与U1的第2引脚相接，第8引脚接输出z，接乘法器U3的第3引脚，接乘法器U4的第3引脚，第9引脚通过电容C3与第8引脚相接，通过电阻R12接1V电源后接地；
    所述乘法器U3的第1引脚接U1的第7脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R1接U1第13引脚，第8引脚接VCC；
    所述乘法器U4的第1引脚接U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R6接U1第2引脚，第8引脚接VCC；
    所述乘法器U5的第1引脚接U1的第8脚，第3引脚接U1的第7引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R11接U2第9引脚，第8引脚接VCC。
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