WO2016187740A1 - 一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法及电路 - Google Patents

一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法及电路 Download PDF

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WO2016187740A1
WO2016187740A1 PCT/CN2015/000573 CN2015000573W WO2016187740A1 WO 2016187740 A1 WO2016187740 A1 WO 2016187740A1 CN 2015000573 W CN2015000573 W CN 2015000573W WO 2016187740 A1 WO2016187740 A1 WO 2016187740A1
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pin
operational amplifier
resistor
selector
multiplier
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PCT/CN2015/000573
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English (en)
French (fr)
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王忠林
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王忠林
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

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  • the invention relates to a chaotic system and a circuit, in particular to a method and a circuit for constructing a Lorenz type four-system switching hyperchaotic system for facilitating ultimate boundary estimation.
  • the boundary estimation of hyperchaotic systems is of great significance in the application of chaos control and synchronization.
  • the method of constructing four-dimensional hyperchaos is based on the three-dimensional chaotic system, adding one-dimensional four-dimensional hyperchaotic systems.
  • the hyperchaotic system is not easy to perform ultimate boundary estimation.
  • the hyperchaotic system that can perform ultimate boundary estimation has the characteristic that the characteristic elements of the main diagonal of the Jacobian matrix are all negative, and the hyperchaotic system constructed by the present invention has ya The characteristic elements of the main diagonal of the comparable matrix are all negative, and the ultimate boundary estimation can be performed. This has important application prospects for the control and synchronization of hyperchaos.
  • a method for constructing a Lorenz type four-system switching hyperchaotic system for facilitating ultimate boundary estimation comprising the steps of:
  • x, y, and z are state variables, and a, b, c, and d are system parameters;
  • w 1 is a state variable and k, r are system parameters
  • variable w 1 is used as a one-dimensional system variable and added to the first equation of the Lorenz-type chaotic system i.
  • a Lorenz-type hyperchaotic system iii is obtained to facilitate the ultimate boundary estimation.
  • variable w 1 is used as a one-dimensional system variable and added to the second equation of the Lorenz type chaotic system i.
  • a Lorenz hyperchaotic system iv is obtained to facilitate the ultimate boundary estimation.
  • variable w 2 is used as a one-dimensional system variable and added to the first equation of the Lorenz-type chaotic system i.
  • a Lorenz-type hyperchaotic system vi is obtained for the ultimate boundary estimation.
  • variable w 2 is used as a one-dimensional system variable and added to the second equation of the Lorenz type chaotic system i.
  • a Lorenz hyperchaotic system vii is obtained for the ultimate boundary estimation.
  • x, y, z, w are state variables
  • f(x) is a switching function
  • the addition and integration operations are realized by the operational amplifier U1, the operational amplifier U2, the resistors and the capacitors, the inversion operation is realized by the operational amplifier U3 and the resistor, and the multiplier U4 and the multiplier U5 are implemented in the system.
  • the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6, and a multiplier U5.
  • the operational amplifier U2 is connected to a multiplier U4 and an operational amplifier U3.
  • the operational amplifier U3 is connected to the operational amplifier U1 and the operational amplifier U2.
  • An amplifier U6 and a multiplier U4 is connected to an operational amplifier U1, the multiplier U5 is connected to an operational amplifier U2; the operational amplifier U6 is connected to a selector U7, and the selector U7 is connected to an operational amplifier U1, the operation
  • the amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selectors U7 and U8 adopt ADG409;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy.
  • the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected.
  • the first pin of the multiplier U5 is connected, the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 through the resistor R7, and the seventh pin of the operational amplifier U1 is connected to the output y, and the operational amplifier U1 is The 8th pin is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx.
  • the 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry1, and the 8th pin of the operational amplifier U1.
  • the eighth pin of operational amplifier U1 Connected to the second pin of operational amplifier U3 through resistor R5, the eighth pin of operational amplifier U1 and The third pin of the U5 is connected, the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U6, and the eighth pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U6.
  • the 8th pin of the operational amplifier U1 is connected to the output x.
  • the 13th pin of the U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx, and the 14th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R1;
  • the first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw.
  • the 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw.
  • the 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11.
  • the 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2
  • the pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier
  • the 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed.
  • the resistor R3 is connected to the ninth pin of the operational amplifier U2;
  • the first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first of the operational amplifiers
  • the pin is connected to the fourth pin of the selector U8; the first pin of the operational amplifier U3 outputs -x, and the second pin of the operational amplifier U3 is connected to the first pin of the operational amplifier U3 via the resistor R6, and the operation is performed.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of the amplifier U3 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin of the operational amplifier U3 is connected through the resistor R8.
  • the seventh pin of the operational amplifier U3 is connected, the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2, and the seventh pin of the operational amplifier U3 is connected to the operational amplifier U2 through the resistor Rw1 and the operational amplifier U2.
  • the second pin is connected, the seventh pin of the operational amplifier U3 is connected to the fifth pin of the selector U8, the seventh pin of the operational amplifier U3 is connected to the output -y; the eighth pin of the operational amplifier U3 is connected to the resistor R10 is connected to the 9th pin of the operational amplifier U3, and the 8th pin of the operational amplifier U3 passes through the resistor Rz2 and the 13th of the operational amplifier U2.
  • the pin is connected, the 8th pin of the operational amplifier U3 is connected to the output -z, the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 through the resistor R12, and the 14th pin of the operational amplifier U3 is passed.
  • the resistor Rw2 is connected to the second pin of the operational amplifier U2, and the 14th pin of the operational amplifier U3 is connected to the output -w;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;
  • the first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6.
  • Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 7th pin of the operational amplifier U6 is connected to the U15 of the resistor U15.
  • the 1 pin is connected; the 7th pin of the operational amplifier U6 is connected to the ground through the resistor R15 and the resistor R16, and the 8th, 9th, 12th, and 13th pins of the operational amplifier U6 are 14-pin floating;
  • the second pin of the selector U7 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifth pin, the thirteenth pin, the fifteenth pin and the sixteenth of the selector U7 The pin is grounded.
  • the 8th pin of the selector U7 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx3, and the 9th pin of the selector U7 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry4.
  • the sixth pin, the seventh pin, the ninth pin, the tenth pin, the eleventh pin, and the twelfth pin of the selector U7 are suspended;
  • the second pin of the selector U8 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifth pin, the thirteenth pin, the fifteenth pin and the sixteenth of the selector U7 The pin is grounded.
  • the 8th pin of the selector U8 is connected to the 2nd pin of the operational amplifier U2 through the resistor Rw1.
  • the 11th pin is left floating.
  • a Lorenz type four-system switching hyperchaotic system circuit for the ultimate boundary estimation which is characterized in that an operational amplifier U1, an operational amplifier U2, a resistor and a capacitor are used for addition and integration operations, and an operational amplifier U3 and a resistor are used for inversion.
  • Operation, multiplier U4 and multiplier U5 implement multiplication in the system, the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6 and a multiplier U5, which is connected to a multiplier U4 and an operational amplifier U3,
  • the operational amplifier U3 is connected to the operational amplifier U1, the operational amplifier U2, the operational amplifier U6, and the multiplier U4.
  • the multiplier U4 is connected to the operational amplifier U1, and the multiplier U5 is connected to the operational amplifier U2.
  • the operational amplifier U6 is connected to the selector U7.
  • the selector U7 is connected to the operational amplifier U1, the operational amplifiers U1, U2, U3 and U6 are LF347BN, the multipliers U4 and U5 are AD633JN, and the selectors U7 and U8 are ADG409;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy.
  • the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected.
  • the first pin of the multiplier U5 is connected, and the seventh pin of the operational amplifier U1 Connected to the sixth pin of the operational amplifier U3 via the resistor R7, the seventh pin of the operational amplifier U1 is connected to the output y, and the eighth pin of the operational amplifier U1 is connected to the ninth pin of the operational amplifier U1 through the capacitor Cx.
  • the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor Ry1, and the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 via the resistor R5, and the operational amplifier U1 is connected.
  • the 8th pin is connected to the 3rd pin of the multiplier U5, the 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U6, and the 8th pin of the operational amplifier U1 and the operational amplifier U6 are connected.
  • the 6-pin is connected, the 8th pin of the operational amplifier U1 is connected to the output x, the 13th pin of the operational amplifier U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx, and the 14th pin of the operational amplifier U1 is passed.
  • the resistor R1 is connected to the ninth pin of the operational amplifier U1;
  • the first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw.
  • the 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw.
  • the 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11.
  • the 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2
  • the pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier
  • the 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed.
  • the resistor R3 is connected to the ninth pin of the operational amplifier U2;
  • the first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first of the operational amplifiers
  • the pin is connected to the fourth pin of the selector U8; the first pin of the operational amplifier U3 outputs -x, and the second pin of the operational amplifier U3 is connected to the first pin of the operational amplifier U3 via the resistor R6, and the operation is performed.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of the amplifier U3 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin of the operational amplifier U3 is connected through the resistor R8.
  • the seventh pin of the operational amplifier U3 is connected, the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2, and the seventh pin of the operational amplifier U3 is connected to the operational amplifier U2 through the resistor Rw1 and the operational amplifier U2.
  • the second pin is connected, the seventh pin of the operational amplifier U3 is connected to the fifth pin of the selector U8, the seventh pin of the operational amplifier U3 is connected to the output -y; the eighth pin of the operational amplifier U3 is connected to the resistor R10 is connected to the 9th pin of the operational amplifier U3, and the 8th pin of the operational amplifier U3 passes through the resistor Rz2 and the 13th of the operational amplifier U2.
  • the pin is connected, the 8th pin of the operational amplifier U3 is connected to the output -z, and the 13th pin of the operational amplifier U3 is connected to the operational amplifier by the resistor R12.
  • the 14th pin of U3 is connected, the 14th pin of the operational amplifier U3 is connected to the 2nd pin of the operational amplifier U2 through the resistor Rw2, and the 14th pin of the operational amplifier U3 is connected to the output -w;
  • the multiplier U4 The second pin, the fourth pin, and the sixth pin are all grounded, the fifth pin is connected to VEE, the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin is connected to VCC;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;
  • the first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6.
  • Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 7th pin of the operational amplifier U6 is connected to the U15 of the resistor U15.
  • the 1 pin is connected; the 7th pin of the operational amplifier U6 is connected to the ground through the resistor R15 and the resistor R16, and the 8th, 9th, 12th, and 13th pins of the operational amplifier U6 are 14-pin floating;
  • the second pin of the selector U7 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifth pin, the thirteenth pin, the fifteenth pin and the sixteenth of the selector U7 The pin is grounded.
  • the 8th pin of the selector U7 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx3, and the 9th pin of the selector U7 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry4.
  • the sixth pin, the seventh pin, the ninth pin, the tenth pin, the eleventh pin, and the twelfth pin of the selector U7 are suspended;
  • the second pin of the selector U8 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifth pin, the thirteenth pin, the fifteenth pin and the sixteenth of the selector U7 The pin is grounded.
  • the 8th pin of the selector U8 is connected to the 2nd pin of the operational amplifier U2 through the resistor Rw1.
  • the 11th pin is left floating.
  • the Lorenz-type four-system switched hyperchaotic system construction method for the ultimate boundary estimation is designed and an analog circuit is designed to realize the chaotic system, which is the synchronization and control of chaos.
  • a new hyperchaotic system signal source is provided.
  • FIG. 1 is a schematic diagram of a circuit connection structure according to a preferred embodiment of the present invention.
  • FIG. 3 is a diagram showing the actual connection of the circuit of the operational amplifier U3.
  • Figure 5 is a diagram showing the actual connection of the circuits of the selectors U7 and U8 and the operational amplifier U6.
  • a Lorenz type four-system switching hyperchaotic system construction method for facilitating ultimate boundary estimation comprising the following steps:
  • x, y, and z are state variables, and a, b, c, and d are system parameters;
  • w 1 is a state variable and k, r are system parameters
  • variable w 1 is used as a one-dimensional system variable and added to the first equation of the Lorenz-type chaotic system i.
  • a Lorenz-type hyperchaotic system iii is obtained to facilitate the ultimate boundary estimation.
  • variable w 1 is used as a one-dimensional system variable and added to the second equation of the Lorenz type chaotic system i.
  • a Lorenz hyperchaotic system iv is obtained to facilitate the ultimate boundary estimation.
  • variable w 2 is used as a one-dimensional system variable and added to the first equation of the Lorenz-type chaotic system i.
  • a Lorenz-type hyperchaotic system vi is obtained for the ultimate boundary estimation.
  • variable w 2 is used as a one-dimensional system variable and added to the second equation of the Lorenz type chaotic system i.
  • a Lorenz hyperchaotic system vii is obtained for the ultimate boundary estimation.
  • x, y, z, w are state variables
  • f(x) is a switching function
  • the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6, and a multiplier U5, which is connected to a multiplier U4 and an operational amplifier U3, which is connected to an operational amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, the multiplier U4 is connected to an operational amplifier U1, the multiplier U5 is connected to an operational amplifier U2; the operational amplifier U6 is connected to a selector U7, and the selector U7 is connected Operation amplifier U1, said operational amplifiers U1, U2, U3 and U6 adopt LF347BN, said multipliers U4 and U5 adopt AD633JN, said selectors U7 and U8 adopt ADG409;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy.
  • the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected.
  • the first pin of the multiplier U5 is connected, the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 through the resistor R7, and the seventh pin of the operational amplifier U1 is connected to the output y, and the operational amplifier U1 is The 8th pin is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx.
  • the 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry1, and the 8th pin of the operational amplifier U1.
  • the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 through resistor R5, the eighth pin of operational amplifier U1 and The third pin of the U5 is connected, the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U6, and the eighth pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U6.
  • the 8th pin of the operational amplifier U1 is connected to the output x.
  • the 13th pin of the operational amplifier U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx, and the 14th pin of the operational amplifier U1 is connected to the operational amplifier by the resistor R1.
  • the 9th pin of U1 is connected;
  • the first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw.
  • the 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw.
  • the 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11.
  • the 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2
  • the pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier
  • the 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed.
  • the resistor R3 is connected to the ninth pin of the operational amplifier U2;
  • the first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx1, and the operation is performed.
  • the first pin of the amplifier U3 is connected to the first pin of the multiplier U4, the first pin of the operational amplifier is connected to the fourth pin of the selector U8, and the first pin of the operational amplifier U3 is outputting -x,
  • the second pin of the operational amplifier U3 is connected to the first pin of the operational amplifier U3 via the resistor R6, and the third pin, the fifth pin, the tenth pin, and the twelfth pin of the operational amplifier U3 are grounded, and the fourth pin is connected.
  • the pin is connected to VCC, the eleventh pin is connected to VEE, the sixth pin of the operational amplifier U3 is connected to the seventh pin of the operational amplifier U3 through the resistor R8, and the seventh pin of the operational amplifier U3 is connected to the operational amplifier U1 through the resistor Ry2.
  • the second pin is connected, the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the seventh pin of the operational amplifier U3 is connected to the fifth pin of the selector U8.
  • the seventh pin of the operational amplifier U3 is connected to the output -y; the eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 through the resistor R10, and the eighth pin of the operational amplifier U3 is connected to the resistor Rz2.
  • the 13th pin of the amplifier U2 is connected, the 8th pin of the operational amplifier U3 is connected to the output -z, and the 13th pin of the operational amplifier U3 is powered.
  • R12 and operational amplifier U3 contact pin 14, the operational amplifier 14, the second pin contact pin through a resistor Rw2 of the operational amplifier U3, U2, operational amplifier 14 connected to the output pin of the U3 -w;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;
  • the first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6.
  • Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 7th pin of the operational amplifier U6 is connected to the U15 of the resistor U15.
  • the 1 pin is connected; the 7th pin of the operational amplifier U6 is connected to the ground through the resistor R15 and the resistor R16, and the 8th, 9th, 12th, and 13th pins of the operational amplifier U6 are 14-pin floating;
  • the second pin of the selector U7 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifth pin, the thirteenth pin, the fifteenth pin and the sixteenth of the selector U7 The pin is grounded.
  • the 8th pin of the selector U7 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx3, and the 9th pin of the selector U7 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry4.
  • the sixth pin, the seventh pin, the ninth pin, the tenth pin, the eleventh pin, and the twelfth pin of the selector U7 are suspended;
  • a Lorenz type four-system switching hyperchaotic system circuit for the ultimate boundary estimation which is characterized in that an operational amplifier U1, an operational amplifier U2, a resistor and a capacitor are used for addition and integration operations, and an operational amplifier U3 and a resistor are used for inversion.
  • Operation, multiplier U4 and multiplier U5 implement multiplication in the system, the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6 and a multiplier U5, which is connected to a multiplier U4 and an operational amplifier U3,
  • the operational amplifier U3 is connected to the operational amplifier U1, the operational amplifier U2, the operational amplifier U6, and the multiplier U4.
  • the multiplier U4 is connected to the operational amplifier U1, and the multiplier U5 is connected to the operational amplifier U2.
  • the operational amplifier U6 is connected to the selector U7.
  • the selector U7 is connected to the operational amplifier U1, the operational amplifiers U1, U2, U3 and U6 are LF347BN, the multipliers U4 and U5 are AD633JN, and the selectors U7 and U8 are ADG409;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy.
  • the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected.
  • the first pin of the multiplier U5 is connected, the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 through the resistor R7, and the seventh pin of the operational amplifier U1 is connected to the output y, and the operational amplifier U1 is The 8th pin is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx.
  • the 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry1, and the 8th pin of the operational amplifier U1.
  • the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 through resistor R5, the eighth pin of operational amplifier U1 and The third pin of the U5 is connected, the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U6, and the eighth pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U6.
  • the 8th pin of the operational amplifier U1 is connected to the output x.
  • the 13th pin of the operational amplifier U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx, and the 14th pin of the operational amplifier U1 is connected to the operational amplifier by the resistor R1.
  • the 9th pin of U1 is connected;
  • the first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw.
  • the 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw.
  • the 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11.
  • the 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the operational amplifier
  • the 8th pin of U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, the 8th pin of the operational amplifier U2 is connected to the 3rd pin of the multiplier U4, and the 8th pin of the operational amplifier U2 is passed.
  • the resistor R9 is connected to the ninth pin of the operational amplifier U3, the eighth pin of the operational amplifier U2 is connected to the output z, and the thirteenth pin of the operational amplifier U2 is connected to the 14th pin of the operational amplifier U2 via the resistor Rz.
  • the 14th pin of the amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the resistor R3;
  • the first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first of the operational amplifiers
  • the pin is connected to the fourth pin of the selector U8; the first pin of the operational amplifier U3 outputs -x, and the second pin of the operational amplifier U3 is connected to the first pin of the operational amplifier U3 via the resistor R6, and the operation is performed.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of the amplifier U3 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the sixth pin of the operational amplifier U3 is connected through the resistor R8.
  • the seventh pin of the operational amplifier U3 is connected, the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2, and the seventh pin of the operational amplifier U3 is connected to the operational amplifier U2 through the resistor Rw1 and the operational amplifier U2.
  • the second pin is connected, the seventh pin of the operational amplifier U3 is connected to the fifth pin of the selector U8, the seventh pin of the operational amplifier U3 is connected to the output -y; the eighth pin of the operational amplifier U3 is connected to the resistor R10 is connected to the 9th pin of the operational amplifier U3, and the 8th pin of the operational amplifier U3 passes through the resistor Rz2 and the 13th of the operational amplifier U2.
  • the pin is connected, the 8th pin of the operational amplifier U3 is connected to the output -z, the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 through the resistor R12, and the 14th pin of the operational amplifier U3 is passed.
  • the resistor Rw2 is connected to the second pin of the operational amplifier U2, and the 14th pin of the operational amplifier U3 is connected to the output -w;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;
  • the first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6.
  • Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 7th pin of the operational amplifier U6 is connected to the U15 of the resistor U15.
  • the 1 pin is connected; the 7th pin of the operational amplifier U6 is connected to the ground through the resistor R15 and the resistor R16, and the 8th, 9th, 12th, and 13th pins of the operational amplifier U6 are 14-pin floating;
  • the second pin of the selector U7 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifth pin, the thirteenth pin, the fifteenth pin and the sixteenth of the selector U7
  • the pin is grounded, and the 8th pin of the selector U7 is powered.
  • the resistor Rx3 is connected to the 13th pin of the operational amplifier U1
  • the 9th pin of the selector U7 is connected to the second pin of the operational amplifier U1 through the resistor Ry4, and the 6th and 7th pins of the selector U7 are connected. , the 9th pin, the 10th pin, the 11th pin, and the 12th pin are suspended;
  • the second pin of the selector U8 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifth pin, the thirteenth pin, the fifteenth pin and the sixteenth of the selector U7 The pin is grounded.
  • the 8th pin of the selector U8 is connected to the 2nd pin of the operational amplifier U2 through the resistor Rw1.
  • the 11th pin is left floating.

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Abstract

提供一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法及电路,利用运算放大器U1、运算放大器U2和电阻、电容实现加法和积分运算,利用运算放大器U3和电阻实现反相运算,乘法器U4和乘法器U5实现系统中的乘法运算,所述运算放大器U1连接运算放大器U2、运算放大器U3和乘法器U5,所述运算放大器U2连接运算放大器U3和乘法器U4,所述运算放大器U1、U2和U3采用LF347BN,所述乘法器U4和U5采用AD633JN。在Lorenz型混沌系统的基础上,设计一种便于终极边界估计的Lorenz型四系统切换超混沌统构建方法并设计一个模拟电路进行实现这个混沌系统,为混沌的同步及控制提供了新的超混沌系统信号源。

Description

一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法及电路 技术领域
本发明涉及一种混沌系统及电路,特别涉及一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法及电路。
背景技术
超混沌系统的边界估计在混沌的控制、同步等工程应用方面具有重要的意义,当前,构造四维超混沌的方法主要是在三维混沌系统的基础上,增加一维构成四维超混沌系统,但所构成的超混沌系统不易于进行终极边界估计,可以进行终极边界估计的超混沌系统具有的特征是:雅可比矩阵主对角线的特征元素全部为负值,本发明构造的超混沌系统具有雅可比矩阵主对角线的特征元素全部为负值的特点,可以进行终极边界估计,这对于超混沌的控制、同步等具有重要的工作应用前景。
发明内容
本发明要解决的技术问题是提供一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法及电路:
1.一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法,其特征在于,包括以下步骤:
(1)Lorenz型混沌系统i为:
Figure PCTCN2015000573-appb-000001
式中x,y,z为状态变量,a,b,c,d为系统参数;
(2)在混沌系统i上增加一维变量w1
dw1/dt=-kx-rw1   k=5,r=0.1               ii
式中w1为状态变量,k,r为系统参数;
(3)把变量w1作为一维系统变量,加在Lorenz型混沌系统i的第一方程上,获得一种便于终极边界估计的Lorenz型超混沌系统iii为
Figure PCTCN2015000573-appb-000002
式中x,y,z,w1为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(4)把变量w1作为一维系统变量,加在Lorenz型混沌系统i的第二方程上,获得一种便于终极边界估计的Lorenz型超混沌系统iv为
Figure PCTCN2015000573-appb-000003
式中x,y,z,w1为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(5)在混沌系统i上增加一维变量w2
dw2/dt=-ky-rw2    k=5,r=0.1              v
式中w2为状态变量,k,r为系统参数;
(6)把变量w2作为一维系统变量,加在Lorenz型混沌系统i的第一方程上,获得一种便于终极边界估计的Lorenz型超混沌系统vi为
Figure PCTCN2015000573-appb-000004
式中x,y,z,w2为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(7)把变量w2作为一维系统变量,加在Lorenz型混沌系统i的第二方程上,获得一种便于终极边界估计的Lorenz型超混沌系统vii为
Figure PCTCN2015000573-appb-000005
式中x,y,z,w2为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(8)构造一个选择函数viii将w1和w2组成一维切换变量w,构造一个切换函数ix和x为:
Figure PCTCN2015000573-appb-000006
dw/dt=kf(x)-rw             k=5,r=0.1
式中w为状态变量,k,r为系统参数;
Figure PCTCN2015000573-appb-000007
Figure PCTCN2015000573-appb-000008
(9)把切换函数ix和x分别加在Lorenz型混沌系统i的第一、二方程上,获得一种便于终极边界估计的Lorenz型四系统切换超混沌系统xi
Figure PCTCN2015000573-appb-000009
式中x,y,z,w为状态变量,f(x)是切换函数,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(10)基于系统xi构造的电路,利用运算放大器U1、运算放大器U2和电阻、电容实现加法和积分运算,利用运算放大器U3和电阻实现反相运算,乘法器U4和乘法器U5实现系统中的乘法运算,所述运算放大器U1连接运算放大器U3、运算放大器U6和乘法器U5,所述运算放大器U2连接乘法器U4和运算放大器U3,所述运算放大器U3连接运算放大器U1、运算放大器U2、运算放大器U6和乘法器U4,所述乘法器U4连接运算放大器U1,所述乘法器U5连接运算放大器U2;所述运算放大器U6连接选择器U7,所述选择器U7连接运算放大器U1,所述运算放大器U1、U2、U3和U6采用LF347BN,所述乘法器U4和U5采用AD633JN,所述选择器U7和U8采用ADG409;
所述运算放大器U1的第1引脚通过电阻R2与运算放大器U1的第6引脚相接,运算放大器U1的第2引脚通过电阻Ry与运算放大器U1的第1引脚相接,运算放大器U1的第3引脚、第5引脚、第10引脚、第12引脚接地,运算放大器U1的第4引脚接VCC,运算放大器U1的第11引脚接VEE,运算放大器U1的第6引脚通过电容Cy与运算放大器U1的第7引脚相接,运算放大器U1的第7引脚通过电阻Rx2与运算放大器U1的第13引脚相接,运算放大器U1的第7引脚与乘法器U5的第1引脚相接,运算放大器U1的第7引脚通过电阻R7与运算放大器U3的第6引脚相接,运算放大器U1的第7引脚接输出y,运算放大器U1的第8引脚通过电容Cx与运算放大器U1的第9引脚相接,运算放大器U1的第8引脚通过电阻Ry1与运算放大器U1的第2引脚相接,运算放大器U1的第8引脚通过电阻R5与运算放大器U3的第2引脚相接,运算放大器U1的第8引脚与乘法器U5的第3引脚相接,运算放大器U1的第8引脚与运算放大器U6的第2引脚相接,运算放大器U1的第8引脚与运算放大器U6的第6引脚相接,运算放大器U1的第8引脚接输出x,运算放 大器U1的第13引脚通过电阻Rx与运算放大器U1的第14引脚相接,运算放大器U1的第14引脚通过电阻R1与运算放大器U1的第9引脚相接;
所述运算放大器U2的第1引脚通过电阻R4与运算放大器U2的第6引脚相接,运算放大器U2的第2引脚通过电阻Rw与运算放大器U2的第1引脚相接,运算放大器U2的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U2的第6引脚通过电容Cw与运算放大器U2的第7引脚相接,运算放大器U2的第7引脚与选择器U7的第4引脚和第12引脚相接,运算放大器U2的第7引脚通过电阻R11与运算放大器U3的第13引脚相接,运算放大器U2的第7引脚接输出w,运算放大器U2的第8引脚通过电容Cz与运算放大器U2的第9引脚相接,运算放大器U2的第8引脚与乘法器U4的第3引脚相接,运算放大器U2的第8引脚通过电阻R9与运算放大器U3的第9引脚相接,运算放大器U2的第8引脚接输出z,运算放大器U2的第13引脚通过电阻Rz与运算放大器U2的第14引脚相接,运算放大器U2的第14引脚通过电阻R3与运算放大器U2的第9引脚相接;
所述运算放大器U3的第1引脚通过电阻Rx1与运算放大器U1的第13引脚相接,运算放大器U3的第1引脚与乘法器U4的第1引脚相接,运算放大器的第1引脚与选择器U8的第4引脚相接;运算放大器U3的第1引脚输出-x,运算放大器U3的第2引脚通过电阻R6与运算放大器U3的第1引脚相接,运算放大器U3的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U3的第6引脚通过电阻R8与运算放大器U3的第7引脚相接,运算放大器U3的第7引脚通过电阻Ry2与运算放大器U1的第2引脚相接,运算放大器U3的第7引脚通过电阻Rw1与运算放大器U2的第2引脚相接,运算放大器U3的第7引脚与选择器U8的第5引脚相接,运算放大器U3的第7引脚接输出-y;运算放大器U3的第8引脚通过电阻R10与运算放大器U3的第9引脚相接,运算放大器U3的第8引脚通过电阻Rz2与运算放大器U2的第13引脚相接,运算放大器U3的第8引脚接输出-z,运算放大器U3的第13引脚通过电阻R12与运算放大器U3的第14引脚相接,运算放大器U3的第14引脚通过电阻Rw2与运算放大器U2的第2引脚相接,运算放大器U3的第14引脚接输出-w;
所述乘法器U4的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Ry3接运算放大器U1的第2引脚,第8引脚接VCC;
所述乘法器U5的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Rz1接运算放大器U2第13引脚,第8引脚接VCC;
所述运算放大器U6的第1引脚通过电阻R13与选择器U7的第1引脚相接,运算放大器U6的第1引脚通过电阻R13和电阻R14与地相接,运算放大器U6的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U6的第7引脚通过电阻R15与选择器U8的第1引脚相接;运算放大器U6的第7引脚通过电阻R15和电阻R16与地相接,运算放大器U6的第8引脚、第9引脚、第12引脚、第13引脚、第14引脚悬空;
所述选择器U7的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U7的第8引脚通过电阻Rx3与运算放大器U1的第13引脚相接,选择器U7的第9引脚通过电阻Ry4与运算放大器U1的第2引脚相接,选择器U7的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚、第12引脚悬空;
所述选择器U8的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U8的第8引脚通过电阻Rw1与运算放大器U2的第2引脚相接,选择器U8的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚悬空。
2.一种便于终极边界估计的Lorenz型四系统切换超混沌系统电路,其特征在于,利用运算放大器U1、运算放大器U2和电阻、电容实现加法和积分运算,利用运算放大器U3和电阻实现反相运算,乘法器U4和乘法器U5实现系统中的乘法运算,所述运算放大器U1连接运算放大器U3、运算放大器U6和乘法器U5,所述运算放大器U2连接乘法器U4和运算放大器U3,所述运算放大器U3连接运算放大器U1、运算放大器U2、运算放大器U6和乘法器U4,所述乘法器U4连接运算放大器U1,所述乘法器U5连接运算放大器U2;所述运算放大器U6连接选择器U7,所述选择器U7连接运算放大器U1,所述运算放大器U1、U2、U3和U6采用LF347BN,所述乘法器U4和U5采用AD633JN,所述选择器U7和U8采用ADG409;
所述运算放大器U1的第1引脚通过电阻R2与运算放大器U1的第6引脚相接,运算放大器U1的第2引脚通过电阻Ry与运算放大器U1的第1引脚相接,运算放大器U1的第3引脚、第5引脚、第10引脚、第12引脚接地,运算放大器U1的第4引脚接VCC,运算放大器U1的第11引脚接VEE,运算放大器U1的第6引脚通过电容Cy与运算放大器U1的第7引脚相接,运算放大器U1的第7引脚通过电阻Rx2与运算放大器U1的第13引脚相接,运算放大器U1的第7引脚与乘法器U5的第1引脚相接,运算放大器U1的第7引脚 通过电阻R7与运算放大器U3的第6引脚相接,运算放大器U1的第7引脚接输出y,运算放大器U1的第8引脚通过电容Cx与运算放大器U1的第9引脚相接,运算放大器U1的第8引脚通过电阻Ry1与运算放大器U1的第2引脚相接,运算放大器U1的第8引脚通过电阻R5与运算放大器U3的第2引脚相接,运算放大器U1的第8引脚与乘法器U5的第3引脚相接,运算放大器U1的第8引脚与运算放大器U6的第2引脚相接,运算放大器U1的第8引脚与运算放大器U6的第6引脚相接,运算放大器U1的第8引脚接输出x,运算放大器U1的第13引脚通过电阻Rx与运算放大器U1的第14引脚相接,运算放大器U1的第14引脚通过电阻R1与运算放大器U1的第9引脚相接;
所述运算放大器U2的第1引脚通过电阻R4与运算放大器U2的第6引脚相接,运算放大器U2的第2引脚通过电阻Rw与运算放大器U2的第1引脚相接,运算放大器U2的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U2的第6引脚通过电容Cw与运算放大器U2的第7引脚相接,运算放大器U2的第7引脚与选择器U7的第4引脚和第12引脚相接,运算放大器U2的第7引脚通过电阻R11与运算放大器U3的第13引脚相接,运算放大器U2的第7引脚接输出w,运算放大器U2的第8引脚通过电容Cz与运算放大器U2的第9引脚相接,运算放大器U2的第8引脚与乘法器U4的第3引脚相接,运算放大器U2的第8引脚通过电阻R9与运算放大器U3的第9引脚相接,运算放大器U2的第8引脚接输出z,运算放大器U2的第13引脚通过电阻Rz与运算放大器U2的第14引脚相接,运算放大器U2的第14引脚通过电阻R3与运算放大器U2的第9引脚相接;
所述运算放大器U3的第1引脚通过电阻Rx1与运算放大器U1的第13引脚相接,运算放大器U3的第1引脚与乘法器U4的第1引脚相接,运算放大器的第1引脚与选择器U8的第4引脚相接;运算放大器U3的第1引脚输出-x,运算放大器U3的第2引脚通过电阻R6与运算放大器U3的第1引脚相接,运算放大器U3的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U3的第6引脚通过电阻R8与运算放大器U3的第7引脚相接,运算放大器U3的第7引脚通过电阻Ry2与运算放大器U1的第2引脚相接,运算放大器U3的第7引脚通过电阻Rw1与运算放大器U2的第2引脚相接,运算放大器U3的第7引脚与选择器U8的第5引脚相接,运算放大器U3的第7引脚接输出-y;运算放大器U3的第8引脚通过电阻R10与运算放大器U3的第9引脚相接,运算放大器U3的第8引脚通过电阻Rz2与运算放大器U2的第13引脚相接,运算放大器U3的第8引脚接输出-z,运算放大器U3的第13引脚通过电阻R12与运算放大器 U3的第14引脚相接,运算放大器U3的第14引脚通过电阻Rw2与运算放大器U2的第2引脚相接,运算放大器U3的第14引脚接输出-w;所述乘法器U4的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Ry3接运算放大器U1的第2引脚,第8引脚接VCC;
所述乘法器U5的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Rz1接运算放大器U2第13引脚,第8引脚接VCC;
所述运算放大器U6的第1引脚通过电阻R13与选择器U7的第1引脚相接,运算放大器U6的第1引脚通过电阻R13和电阻R14与地相接,运算放大器U6的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U6的第7引脚通过电阻R15与选择器U8的第1引脚相接;运算放大器U6的第7引脚通过电阻R15和电阻R16与地相接,运算放大器U6的第8引脚、第9引脚、第12引脚、第13引脚、第14引脚悬空;
所述选择器U7的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U7的第8引脚通过电阻Rx3与运算放大器U1的第13引脚相接,选择器U7的第9引脚通过电阻Ry4与运算放大器U1的第2引脚相接,选择器U7的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚、第12引脚悬空;
所述选择器U8的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U8的第8引脚通过电阻Rw1与运算放大器U2的第2引脚相接,选择器U8的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚悬空。
有益效果:本发明在Lorenz型混沌系统的基础上,设计了一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法并设计一个模拟电路进行实现这个混沌系统,为混沌的同步及控制提供了新的超混沌系统信号源。
附图说明
图1为本发明优选实施例的电路连接结构示意图。
图2为乘法器U4和运算放大器U1的电路实际连接图。
图3为运算放大器U3的电路实际连接图。
图4为乘法器U5和运算放大器U2的电路实际连接图。
图5为选择器U7与U8和运算放大器U6的电路实际连接图。
具体实施方式
下面结合附图和优选实施例对本发明作更进一步的详细描述,参见图1-图5。
1。一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法,其特征在于,包括以下步骤:
(1)Lorenz型混沌系统i为:
Figure PCTCN2015000573-appb-000010
式中x,y,z为状态变量,a,b,c,d为系统参数;
(2)在混沌系统i上增加一维变量w1
dw1/dt=-kx-rw1    k=5,r=0.1                       ii
式中w1为状态变量,k,r为系统参数;
(3)把变量w1作为一维系统变量,加在Lorenz型混沌系统i的第一方程上,获得一种便于终极边界估计的Lorenz型超混沌系统iii为
Figure PCTCN2015000573-appb-000011
式中x,y,z,w1为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(4)把变量w1作为一维系统变量,加在Lorenz型混沌系统i的第二方程上,获得一种便于终极边界估计的Lorenz型超混沌系统iv为
Figure PCTCN2015000573-appb-000012
式中x,y,z,w1为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(5)在混沌系统i上增加一维变量w2
dw2/dt=-ky-rw2   k=5,r=0.1                           v
式中w2为状态变量,k,r为系统参数;
(6)把变量w2作为一维系统变量,加在Lorenz型混沌系统i的第一方程上,获得一种便于终极边界估计的Lorenz型超混沌系统vi为
Figure PCTCN2015000573-appb-000013
式中x,y,z,w2为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(7)把变量w2作为一维系统变量,加在Lorenz型混沌系统i的第二方程上,获得一种便于终极边界估计的Lorenz型超混沌系统vii为
Figure PCTCN2015000573-appb-000014
式中x,y,z,w2为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(8)构造一个选择函数viii将w1和w2组成一维切换变量w,构造一个切换函数ix和x为:
Figure PCTCN2015000573-appb-000015
dw/dt=kf(x)-rw         k=5,r=0.1
式中w为状态变量,k,r为系统参数;
Figure PCTCN2015000573-appb-000016
Figure PCTCN2015000573-appb-000017
(9)把切换函数ix和x分别加在Lorenz型混沌系统i的第一、二方程上,获得一种便于终极边界估计的Lorenz型四系统切换超混沌系统xi
Figure PCTCN2015000573-appb-000018
式中x,y,z,w为状态变量,f(x)是切换函数,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
(10)基于系统xi构造的电路,利用运算放大器U1、运算放大器U2和电阻、电容实现加法和积分运算,利用运算放大器U3和电阻实现反相运算,乘法器U4和乘法器U5实现系统中的乘法运算,所述运算放大器U1连接运算放大器U3、运算放大器U6和乘法器U5,所述运算放大器U2连接乘法器U4和运算放大器U3,所述运算放大器U3连接运算放大器 U1、运算放大器U2、运算放大器U6和乘法器U4,所述乘法器U4连接运算放大器U1,所述乘法器U5连接运算放大器U2;所述运算放大器U6连接选择器U7,所述选择器U7连接运算放大器U1,所述运算放大器U1、U2、U3和U6采用LF347BN,所述乘法器U4和U5采用AD633JN,所述选择器U7和U8采用ADG409;
所述运算放大器U1的第1引脚通过电阻R2与运算放大器U1的第6引脚相接,运算放大器U1的第2引脚通过电阻Ry与运算放大器U1的第1引脚相接,运算放大器U1的第3引脚、第5引脚、第10引脚、第12引脚接地,运算放大器U1的第4引脚接VCC,运算放大器U1的第11引脚接VEE,运算放大器U1的第6引脚通过电容Cy与运算放大器U1的第7引脚相接,运算放大器U1的第7引脚通过电阻Rx2与运算放大器U1的第13引脚相接,运算放大器U1的第7引脚与乘法器U5的第1引脚相接,运算放大器U1的第7引脚通过电阻R7与运算放大器U3的第6引脚相接,运算放大器U1的第7引脚接输出y,运算放大器U1的第8引脚通过电容Cx与运算放大器U1的第9引脚相接,运算放大器U1的第8引脚通过电阻Ry1与运算放大器U1的第2引脚相接,运算放大器U1的第8引脚通过电阻R5与运算放大器U3的第2引脚相接,运算放大器U1的第8引脚与乘法器U5的第3引脚相接,运算放大器U1的第8引脚与运算放大器U6的第2引脚相接,运算放大器U1的第8引脚与运算放大器U6的第6引脚相接,运算放大器U1的第8引脚接输出x,运算放大器U1的第13引脚通过电阻Rx与运算放大器U1的第14引脚相接,运算放大器U1的第14引脚通过电阻R1与运算放大器U1的第9引脚相接;
所述运算放大器U2的第1引脚通过电阻R4与运算放大器U2的第6引脚相接,运算放大器U2的第2引脚通过电阻Rw与运算放大器U2的第1引脚相接,运算放大器U2的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U2的第6引脚通过电容Cw与运算放大器U2的第7引脚相接,运算放大器U2的第7引脚与选择器U7的第4引脚和第12引脚相接,运算放大器U2的第7引脚通过电阻R11与运算放大器U3的第13引脚相接,运算放大器U2的第7引脚接输出w,运算放大器U2的第8引脚通过电容Cz与运算放大器U2的第9引脚相接,运算放大器U2的第8引脚与乘法器U4的第3引脚相接,运算放大器U2的第8引脚通过电阻R9与运算放大器U3的第9引脚相接,运算放大器U2的第8引脚接输出z,运算放大器U2的第13引脚通过电阻Rz与运算放大器U2的第14引脚相接,运算放大器U2的第14引脚通过电阻R3与运算放大器U2的第9引脚相接;
所述运算放大器U3的第1引脚通过电阻Rx1与运算放大器U1的第13引脚相接,运算 放大器U3的第1引脚与乘法器U4的第1引脚相接,运算放大器的第1引脚与选择器U8的第4引脚相接;运算放大器U3的第1引脚输出-x,运算放大器U3的第2引脚通过电阻R6与运算放大器U3的第1引脚相接,运算放大器U3的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U3的第6引脚通过电阻R8与运算放大器U3的第7引脚相接,运算放大器U3的第7引脚通过电阻Ry2与运算放大器U1的第2引脚相接,运算放大器U3的第7引脚通过电阻Rw1与运算放大器U2的第2引脚相接,运算放大器U3的第7引脚与选择器U8的第5引脚相接,运算放大器U3的第7引脚接输出-y;运算放大器U3的第8引脚通过电阻R10与运算放大器U3的第9引脚相接,运算放大器U3的第8引脚通过电阻Rz2与运算放大器U2的第13引脚相接,运算放大器U3的第8引脚接输出-z,运算放大器U3的第13引脚通过电阻R12与运算放大器U3的第14引脚相接,运算放大器U3的第14引脚通过电阻Rw2与运算放大器U2的第2引脚相接,运算放大器U3的第14引脚接输出-w;
所述乘法器U4的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Ry3接运算放大器U1的第2引脚,第8引脚接VCC;
所述乘法器U5的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Rz1接运算放大器U2第13引脚,第8引脚接VCC;
所述运算放大器U6的第1引脚通过电阻R13与选择器U7的第1引脚相接,运算放大器U6的第1引脚通过电阻R13和电阻R14与地相接,运算放大器U6的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U6的第7引脚通过电阻R15与选择器U8的第1引脚相接;运算放大器U6的第7引脚通过电阻R15和电阻R16与地相接,运算放大器U6的第8引脚、第9引脚、第12引脚、第13引脚、第14引脚悬空;
所述选择器U7的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U7的第8引脚通过电阻Rx3与运算放大器U1的第13引脚相接,选择器U7的第9引脚通过电阻Ry4与运算放大器U1的第2引脚相接,选择器U7的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚、第12引脚悬空;
所述选择器U8的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U8的第8引脚通过电阻Rw1与运算放大器U2的第2引脚相接,选择器U8的第6引脚、第7引脚、第9引脚、 第10引脚、第11引脚悬空。
2.一种便于终极边界估计的Lorenz型四系统切换超混沌系统电路,其特征在于,利用运算放大器U1、运算放大器U2和电阻、电容实现加法和积分运算,利用运算放大器U3和电阻实现反相运算,乘法器U4和乘法器U5实现系统中的乘法运算,所述运算放大器U1连接运算放大器U3、运算放大器U6和乘法器U5,所述运算放大器U2连接乘法器U4和运算放大器U3,所述运算放大器U3连接运算放大器U1、运算放大器U2、运算放大器U6和乘法器U4,所述乘法器U4连接运算放大器U1,所述乘法器U5连接运算放大器U2;所述运算放大器U6连接选择器U7,所述选择器U7连接运算放大器U1,所述运算放大器U1、U2、U3和U6采用LF347BN,所述乘法器U4和U5采用AD633JN,所述选择器U7和U8采用ADG409;
所述运算放大器U1的第1引脚通过电阻R2与运算放大器U1的第6引脚相接,运算放大器U1的第2引脚通过电阻Ry与运算放大器U1的第1引脚相接,运算放大器U1的第3引脚、第5引脚、第10引脚、第12引脚接地,运算放大器U1的第4引脚接VCC,运算放大器U1的第11引脚接VEE,运算放大器U1的第6引脚通过电容Cy与运算放大器U1的第7引脚相接,运算放大器U1的第7引脚通过电阻Rx2与运算放大器U1的第13引脚相接,运算放大器U1的第7引脚与乘法器U5的第1引脚相接,运算放大器U1的第7引脚通过电阻R7与运算放大器U3的第6引脚相接,运算放大器U1的第7引脚接输出y,运算放大器U1的第8引脚通过电容Cx与运算放大器U1的第9引脚相接,运算放大器U1的第8引脚通过电阻Ry1与运算放大器U1的第2引脚相接,运算放大器U1的第8引脚通过电阻R5与运算放大器U3的第2引脚相接,运算放大器U1的第8引脚与乘法器U5的第3引脚相接,运算放大器U1的第8引脚与运算放大器U6的第2引脚相接,运算放大器U1的第8引脚与运算放大器U6的第6引脚相接,运算放大器U1的第8引脚接输出x,运算放大器U1的第13引脚通过电阻Rx与运算放大器U1的第14引脚相接,运算放大器U1的第14引脚通过电阻R1与运算放大器U1的第9引脚相接;
所述运算放大器U2的第1引脚通过电阻R4与运算放大器U2的第6引脚相接,运算放大器U2的第2引脚通过电阻Rw与运算放大器U2的第1引脚相接,运算放大器U2的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U2的第6引脚通过电容Cw与运算放大器U2的第7引脚相接,运算放大器U2的第7引脚与选择器U7的第4引脚和第12引脚相接,运算放大器U2的第7引脚通过电阻R11与运算放大器U3的第13引脚相接,运算放大器U2的第7引脚接输出w,运算放大器 U2的第8引脚通过电容Cz与运算放大器U2的第9引脚相接,运算放大器U2的第8引脚与乘法器U4的第3引脚相接,运算放大器U2的第8引脚通过电阻R9与运算放大器U3的第9引脚相接,运算放大器U2的第8引脚接输出z,运算放大器U2的第13引脚通过电阻Rz与运算放大器U2的第14引脚相接,运算放大器U2的第14引脚通过电阻R3与运算放大器U2的第9引脚相接;
所述运算放大器U3的第1引脚通过电阻Rx1与运算放大器U1的第13引脚相接,运算放大器U3的第1引脚与乘法器U4的第1引脚相接,运算放大器的第1引脚与选择器U8的第4引脚相接;运算放大器U3的第1引脚输出-x,运算放大器U3的第2引脚通过电阻R6与运算放大器U3的第1引脚相接,运算放大器U3的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U3的第6引脚通过电阻R8与运算放大器U3的第7引脚相接,运算放大器U3的第7引脚通过电阻Ry2与运算放大器U1的第2引脚相接,运算放大器U3的第7引脚通过电阻Rw1与运算放大器U2的第2引脚相接,运算放大器U3的第7引脚与选择器U8的第5引脚相接,运算放大器U3的第7引脚接输出-y;运算放大器U3的第8引脚通过电阻R10与运算放大器U3的第9引脚相接,运算放大器U3的第8引脚通过电阻Rz2与运算放大器U2的第13引脚相接,运算放大器U3的第8引脚接输出-z,运算放大器U3的第13引脚通过电阻R12与运算放大器U3的第14引脚相接,运算放大器U3的第14引脚通过电阻Rw2与运算放大器U2的第2引脚相接,运算放大器U3的第14引脚接输出-w;
所述乘法器U4的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Ry3接运算放大器U1的第2引脚,第8引脚接VCC;
所述乘法器U5的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Rz1接运算放大器U2第13引脚,第8引脚接VCC;
所述运算放大器U6的第1引脚通过电阻R13与选择器U7的第1引脚相接,运算放大器U6的第1引脚通过电阻R13和电阻R14与地相接,运算放大器U6的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U6的第7引脚通过电阻R15与选择器U8的第1引脚相接;运算放大器U6的第7引脚通过电阻R15和电阻R16与地相接,运算放大器U6的第8引脚、第9引脚、第12引脚、第13引脚、第14引脚悬空;
所述选择器U7的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U7的第8引脚通过电 阻Rx3与运算放大器U1的第13引脚相接,选择器U7的第9引脚通过电阻Ry4与运算放大器U1的第2引脚相接,选择器U7的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚、第12引脚悬空;
所述选择器U8的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U8的第8引脚通过电阻Rw1与运算放大器U2的第2引脚相接,选择器U8的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚悬空。
当然,上述说明并非对发明的限制,本发明也不仅限于上述举例,本技术领域的普通技术人员在本发明的实质范围内所做出的变化、改型、添加或替换,也属于本发明的保护范围。

Claims (2)

  1. 一种便于终极边界估计的Lorenz型四系统切换超混沌系统构建方法,其特征在于,包括以下步骤:
    (1)Lorenz型混沌系统i为:
    Figure PCTCN2015000573-appb-100001
    式中x,y,z为状态变量,a,b,c,d为系统参数;
    (2)在混沌系统i上增加一维变量w1
    dw1/dt=-kx-rw1   k=5,r=0.1                 ii
    式中w1为状态变量,k,r为系统参数;
    (3)把变量w1作为一维系统变量,加在Lorenz型混沌系统i的第一方程上,获得一种便于终极边界估计的Lorenz型超混沌系统iii为
    Figure PCTCN2015000573-appb-100002
    式中x,y,z,w1为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
    (4)把变量w1作为一维系统变量,加在Lorenz型混沌系统i的第二方程上,获得一种便于终极边界估计的Lorenz型超混沌系统iv为
    Figure PCTCN2015000573-appb-100003
    式中x,y,z,w1为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
    (5)在混沌系统i上增加一维变量w2
    dw2/dt=-ky-rw2   k=5,r=0.1                 v
    式中w2为状态变量,k,r为系统参数;
    (6)把变量w2作为一维系统变量,加在Lorenz型混沌系统i的第一方程上,获得一种便于终极边界估计的Lorenz型超混沌系统vi为
    Figure PCTCN2015000573-appb-100004
    式中x,y,z,w2为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
    (7)把变量w2作为一维系统变量,加在Lorenz型混沌系统i的第二方程上,获得一种便于终极边界估计的Lorenz型超混沌系统vii为
    Figure PCTCN2015000573-appb-100005
    式中x,y,z,w2为状态变量,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
    (8)构造一个选择函数viii将w1和w2组成一维切换变量w,构造一个切换函数ix和x为:
    Figure PCTCN2015000573-appb-100006
    dw/dt=kf(x)-rw   k=5,r=0.1
    式中w为状态变量,k,r为系统参数;
    Figure PCTCN2015000573-appb-100007
    Figure PCTCN2015000573-appb-100008
    (9)把切换函数ix和x分别加在Lorenz型混沌系统i的第一、二方程上,获得一种便于终极边界估计的Lorenz型四系统切换超混沌系统xi
    Figure PCTCN2015000573-appb-100009
    式中x,y,z,w为状态变量,f(x)是切换函数,参数值a=12,b=23,c=1,d=2.1,k=5,r=0.1;
    (10)基于系统xi构造的电路,利用运算放大器U1、运算放大器U2和电阻、电容实现加法和积分运算,利用运算放大器U3和电阻实现反相运算,乘法器U4和乘法器U5实现系统中的乘法运算,所述运算放大器U1连接运算放大器U3、运算放大器U6和乘法器U5,所述运算放大器U2连接乘法器U4和运算放大器U3,所述运算放大器U3连接运算放大器 U1、运算放大器U2、运算放大器U6和乘法器U4,所述乘法器U4连接运算放大器U1,所述乘法器U5连接运算放大器U2;所述运算放大器U6连接选择器U7,所述选择器U7连接运算放大器U1,所述运算放大器U1、U2、U3和U6采用LF347BN,所述乘法器U4和U5采用AD633JN,所述选择器U7和U8采用ADG409;
    所述运算放大器U1的第1引脚通过电阻R2与运算放大器U1的第6引脚相接,运算放大器U1的第2引脚通过电阻Ry与运算放大器U1的第1引脚相接,运算放大器U1的第3引脚、第5引脚、第10引脚、第12引脚接地,运算放大器U1的第4引脚接VCC,运算放大器U1的第11引脚接VEE,运算放大器U1的第6引脚通过电容Cy与运算放大器U1的第7引脚相接,运算放大器U1的第7引脚通过电阻Rx2与运算放大器U1的第13引脚相接,运算放大器U1的第7引脚与乘法器U5的第1引脚相接,运算放大器U1的第7引脚通过电阻R7与运算放大器U3的第6引脚相接,运算放大器U1的第7引脚接输出y,运算放大器U1的第8引脚通过电容Cx与运算放大器U1的第9引脚相接,运算放大器U1的第8引脚通过电阻Ry1与运算放大器U1的第2引脚相接,运算放大器U1的第8引脚通过电阻R5与运算放大器U3的第2引脚相接,运算放大器U1的第8引脚与乘法器U5的第3引脚相接,运算放大器U1的第8引脚与运算放大器U6的第2引脚相接,运算放大器U1的第8引脚与运算放大器U6的第6引脚相接,运算放大器U1的第8引脚接输出x,运算放大器U1的第13引脚通过电阻Rx与运算放大器U1的第14引脚相接,运算放大器U1的第14引脚通过电阻R1与运算放大器U1的第9引脚相接;
    所述运算放大器U2的第1引脚通过电阻R4与运算放大器U2的第6引脚相接,运算放大器U2的第2引脚通过电阻Rw与运算放大器U2的第1引脚相接,运算放大器U2的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U2的第6引脚通过电容Cw与运算放大器U2的第7引脚相接,运算放大器U2的第7引脚与选择器U7的第4引脚和第12引脚相接,运算放大器U2的第7引脚通过电阻R11与运算放大器U3的第13引脚相接,运算放大器U2的第7引脚接输出w,运算放大器U2的第8引脚通过电容Cz与运算放大器U2的第9引脚相接,运算放大器U2的第8引脚与乘法器U4的第3引脚相接,运算放大器U2的第8引脚通过电阻R9与运算放大器U3的第9引脚相接,运算放大器U2的第8引脚接输出z,运算放大器U2的第13引脚通过电阻Rz与运算放大器U2的第14引脚相接,运算放大器U2的第14引脚通过电阻R3与运算放大器U2的第9引脚相接;
    所述运算放大器U3的第1引脚通过电阻Rx1与运算放大器U1的第13引脚相接,运算放大器U3的第1引脚与乘法器U4的第1引脚相接,运算放大器的第1引脚与选择器U8 的第4引脚相接;运算放大器U3的第1引脚输出-x,运算放大器U3的第2引脚通过电阻R6与运算放大器U3的第1引脚相接,运算放大器U3的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U3的第6引脚通过电阻R8与运算放大器U3的第7引脚相接,运算放大器U3的第7引脚通过电阻Ry2与运算放大器U1的第2引脚相接,运算放大器U3的第7引脚通过电阻Rw1与运算放大器U2的第2引脚相接,运算放大器U3的第7引脚与选择器U8的第5引脚相接,运算放大器U3的第7引脚接输出-y;运算放大器U3的第8引脚通过电阻R10与运算放大器U3的第9引脚相接,运算放大器U3的第8引脚通过电阻Rz2与运算放大器U2的第13引脚相接,运算放大器U3的第8引脚接输出-z,运算放大器U3的第13引脚通过电阻R12与运算放大器U3的第14引脚相接,运算放大器U3的第14引脚通过电阻Rw2与运算放大器U2的第2引脚相接,运算放大器U3的第14引脚接输出-w;
    所述乘法器U4的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Ry3接运算放大器U1的第2引脚,第8引脚接VCC;
    所述乘法器U5的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Rz1接运算放大器U2第13引脚,第8引脚接VCC;
    所述运算放大器U6的第1引脚通过电阻R13与选择器U7的第1引脚相接,运算放大器U6的第1引脚通过电阻R13和电阻R14与地相接,运算放大器U6的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U6的第7引脚通过电阻R15与选择器U8的第1引脚相接;运算放大器U6的第7引脚通过电阻R15和电阻R16与地相接,运算放大器U6的第8引脚、第9引脚、第12引脚、第13引脚、第14引脚悬空;
    所述选择器U7的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U7的第8引脚通过电阻Rx3与运算放大器U1的第13引脚相接,选择器U7的第9引脚通过电阻Ry4与运算放大器U1的第2引脚相接,选择器U7的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚、第12引脚悬空;
    所述选择器U8的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U8的第8引脚通过电阻Rw1与运算放大器U2的第2引脚相接,选择器U8的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚悬空。
  2. 一种便于终极边界估计的Lorenz型四系统切换超混沌系统电路,其特征在于,利用运算 放大器U1、运算放大器U2和电阻、电容实现加法和积分运算,利用运算放大器U3和电阻实现反相运算,乘法器U4和乘法器U5实现系统中的乘法运算,所述运算放大器U1连接运算放大器U3、运算放大器U6和乘法器U5,所述运算放大器U2连接乘法器U4和运算放大器U3,所述运算放大器U3连接运算放大器U1、运算放大器U2、运算放大器U6和乘法器U4,所述乘法器U4连接运算放大器U1,所述乘法器U5连接运算放大器U2;所述运算放大器U6连接选择器U7,所述选择器U7连接运算放大器U1,所述运算放大器U1、U2、U3和U6采用LF347BN,所述乘法器U4和U5采用AD633JN,所述选择器U7和U8采用ADG409;
    所述运算放大器U1的第1引脚通过电阻R2与运算放大器U1的第6引脚相接,运算放大器U1的第2引脚通过电阻Ry与运算放大器U1的第1引脚相接,运算放大器U1的第3引脚、第5引脚、第10引脚、第12引脚接地,运算放大器U1的第4引脚接VCC,运算放大器U1的第11引脚接VEE,运算放大器U1的第6引脚通过电容Cy与运算放大器U1的第7引脚相接,运算放大器U1的第7引脚通过电阻Rx2与运算放大器U1的第13引脚相接,运算放大器U1的第7引脚与乘法器U5的第1引脚相接,运算放大器U1的第7引脚通过电阻R7与运算放大器U3的第6引脚相接,运算放大器U1的第7引脚接输出y,运算放大器U1的第8引脚通过电容Cx与运算放大器U1的第9引脚相接,运算放大器U1的第8引脚通过电阻Ry1与运算放大器U1的第2引脚相接,运算放大器U1的第8引脚通过电阻R5与运算放大器U3的第2引脚相接,运算放大器U1的第8引脚与乘法器U5的第3引脚相接,运算放大器U1的第8引脚与运算放大器U6的第2引脚相接,运算放大器U1的第8引脚与运算放大器U6的第6引脚相接,运算放大器U1的第8引脚接输出x,运算放大器U1的第13引脚通过电阻Rx与运算放大器U1的第14引脚相接,运算放大器U1的第14引脚通过电阻R1与运算放大器U1的第9引脚相接;
    所述运算放大器U2的第1引脚通过电阻R4与运算放大器U2的第6引脚相接,运算放大器U2的第2引脚通过电阻Rw与运算放大器U2的第1引脚相接,运算放大器U2的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U2的第6引脚通过电容Cw与运算放大器U2的第7引脚相接,运算放大器U2的第7引脚与选择器U7的第4引脚和第12引脚相接,运算放大器U2的第7引脚通过电阻R11与运算放大器U3的第13引脚相接,运算放大器U2的第7引脚接输出w,运算放大器U2的第8引脚通过电容Cz与运算放大器U2的第9引脚相接,运算放大器U2的第8引脚与乘法器U4的第3引脚相接,运算放大器U2的第8引脚通过电阻R9与运算放大器U3的第9引脚相接,运算放大器U2的第8引脚接输出z,运算放大器U2的第13引脚通过电阻 Rz与运算放大器U2的第14引脚相接,运算放大器U2的第14引脚通过电阻R3与运算放大器U2的第9引脚相接;
    所述运算放大器U3的第1引脚通过电阻Rx1与运算放大器U1的第13引脚相接,运算放大器U3的第1引脚与乘法器U4的第1引脚相接,运算放大器的第1引脚与选择器U8的第4引脚相接;运算放大器U3的第1引脚输出-x,运算放大器U3的第2引脚通过电阻R6与运算放大器U3的第1引脚相接,运算放大器U3的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U3的第6引脚通过电阻R8与运算放大器U3的第7引脚相接,运算放大器U3的第7引脚通过电阻Ry2与运算放大器U1的第2引脚相接,运算放大器U3的第7引脚通过电阻Rw1与运算放大器U2的第2引脚相接,运算放大器U3的第7引脚与选择器U8的第5引脚相接,运算放大器U3的第7引脚接输出-y;运算放大器U3的第8引脚通过电阻R10与运算放大器U3的第9引脚相接,运算放大器U3的第8引脚通过电阻Rz2与运算放大器U2的第13引脚相接,运算放大器U3的第8引脚接输出-z,运算放大器U3的第13引脚通过电阻R12与运算放大器U3的第14引脚相接,运算放大器U3的第14引脚通过电阻Rw2与运算放大器U2的第2引脚相接,运算放大器U3的第14引脚接输出-w;
    所述乘法器U4的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Ry3接运算放大器U1的第2引脚,第8引脚接VCC;
    所述乘法器U5的第2引脚、第4引脚、第6引脚均接地,第5引脚接VEE,第7引脚通过电阻Rz1接运算放大器U2第13引脚,第8引脚接VCC;
    所述运算放大器U6的第1引脚通过电阻R13与选择器U7的第1引脚相接,运算放大器U6的第1引脚通过电阻R13和电阻R14与地相接,运算放大器U6的第3引脚、第5引脚、第10引脚、第12引脚接地,第4引脚接VCC,第11引脚接VEE,运算放大器U6的第7引脚通过电阻R15与选择器U8的第1引脚相接;运算放大器U6的第7引脚通过电阻R15和电阻R16与地相接,运算放大器U6的第8引脚、第9引脚、第12引脚、第13引脚、第14引脚悬空;
    所述选择器U7的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U7的第8引脚通过电阻Rx3与运算放大器U1的第13引脚相接,选择器U7的第9引脚通过电阻Ry4与运算放大器U1的第2引脚相接,选择器U7的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚、第12引脚悬空;
    所述选择器U8的第2引脚和第14引脚阶VCC,选择器U7的第3引脚接VEE,选 择器U7的第5引脚、第13引脚、第15引脚和第16引脚接地,选择器U8的第8引脚通过电阻Rw1与运算放大器U2的第2引脚相接,选择器U8的第6引脚、第7引脚、第9引脚、第10引脚、第11引脚悬空。
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