WO2016033917A1 - 一种通用混沌系统的电路设计 - Google Patents

一种通用混沌系统的电路设计 Download PDF

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WO2016033917A1
WO2016033917A1 PCT/CN2015/000262 CN2015000262W WO2016033917A1 WO 2016033917 A1 WO2016033917 A1 WO 2016033917A1 CN 2015000262 W CN2015000262 W CN 2015000262W WO 2016033917 A1 WO2016033917 A1 WO 2016033917A1
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pin
potentiometer
power supply
operational amplifier
pins
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PCT/CN2015/000262
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French (fr)
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王忠林
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王忠林
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

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  • the invention relates to a circuit design, in particular to a circuit design of a universal chaotic system.
  • the current chaotic system circuit generally uses a breadboard for circuit design.
  • the circuit design with breadboard takes time and costs and the error rate is relatively high. The error is not easy to check.
  • the PCB printed circuit board is used for design, and each chaotic system should be performed once.
  • Design, low flexibility, long design cycle, the existing universal chaotic system circuit uses welding method, each circuit board can design a chaotic system circuit, but there are large plates, frequent replacement of components, easy to cause components damage.
  • the present invention proposes a circuit design of a universal chaotic system, in which the connection ends are welded with holes, and the connection lines can be inserted into the holes, and are repeatedly used, using an operational amplifier U1, an operational amplifier U2, and a resistor and a capacitor.
  • an operational amplifier U1 an operational amplifier U2
  • a resistor and a capacitor Four sets of inverting adders and four sets of inverting integrators, each set of inverting adders having four input terminals, each input terminal drawing four input signals, using operational amplifier U3 and resistors and capacitors to form four sets of inverters Multiplier U4, U5, U6, and U7 are used to implement multiplication, respectively.
  • Each group outputs two outputs of positive and negative signals, and each output signal leads to five output terminals.
  • the operational amplifier U1 and operational amplifier U2 The operational amplifier U3 uses LF347N, and the multipliers U4 and U5 use AD633JN.
  • the first pin of the operational amplifier U1 is connected to the second pin through the potentiometer U1_Y_F_R, the sixth pin is connected through the potentiometer U1_Y_C_R, and the second pin is connected to the four inputs Y_I_1R, Y_I_2R, Y_I_3R, Y_I_4R, 3, 5, 10, 12 pin grounding, the 4th pin is connected to the positive power supply VCC, the 11th pin is connected to the negative power VEE, the 6th pin is connected to the 7th pin through the capacitor Cy, the 7th pin is connected to +Y, and the Y is connected through the resistor Y_OUT_R The 8th pin is connected to +X, connected to X through the resistor X_OUT_R, connected to the 9th pin through the capacitor Cx, the 13th pin is connected to the four inputs X_I_1R, X_I_2R, X_I_3R, X_I_4R, and the 14th
  • the first pin of the operational amplifier U2 is connected to the second pin through the potentiometer U2_U_F_R
  • the sixth pin is connected through the potentiometer U2_U_C_R
  • the second pin is connected to the four inputs U_I_1R, U_I_2R, U_I_3R, U_I_4R, 3, 5, 10, 12 pin grounding
  • the 4th pin is connected to the positive power supply VCC
  • the 11th pin is connected to the negative power VEE
  • the 6th pin is connected to the 7th pin through the capacitor Cu
  • the 7th pin is connected to the +U
  • the U is connected through the resistor U_OUT_R
  • the 8th pin is connected to +Z, connected to Z through the resistor Z_OUT_R, connected to the 9th pin through the capacitor Cz
  • the 13th pin is connected to the four inputs Z_I_1R, Z_I_2R, Z_I_3R, Z_I_4R
  • the 14th pin is connected
  • the first pin of the operational amplifier U3 is connected to -X
  • the second pin is connected through the potentiometer U3_X_F_R
  • the second pin is connected to the +X through the potentiometer U3_X_IN_R
  • the third, fifth, ten, and 12 pins are grounded
  • the fourth lead The pin is connected to the positive power supply VCC
  • the 11th pin is connected to the negative power VEE
  • the 6th pin is connected to -Y through the potentiometer U3_Y_F_R
  • the 7th pin is connected to -Y
  • the 8th pin is connected to -Z
  • the 9th pin is connected to +Z through U3_Z_IN_R
  • the 13th pin is connected to the 14th pin through the potentiometer U3_U_F_R
  • the 14th pin is connected to +U through
  • the first pin of the multiplier U4 is connected to X_A, the second, fourth, and sixth pins are grounded, the third pin is connected to X_B, the fifth pin is connected to the negative power supply VEE, and the seventh pin is connected to the output X_AB, the eighth pin. Connect the positive power supply VCC.
  • the first pin of the multiplier U5 is connected to Y_A, the second, fourth, and sixth pins are grounded, the third pin is connected to Y_B, the fifth pin is connected to the negative power supply VEE, and the seventh pin is connected to the output Y_AB, the eighth pin. Connect the positive power supply VCC.
  • the first pin of the multiplier U6 is connected to Z_A, the second, fourth, and sixth pins are grounded, the third pin is connected to Z_B, the fifth pin is connected to the negative power supply VEE, and the seventh pin is connected to the output Z_AB, the eighth pin. Connect the positive power supply VCC.
  • the first pin of the multiplier U7 is connected to U_A, the second, fourth, and sixth pins are grounded, the third pin is connected to U_B, the fifth pin is connected to the negative power supply VEE, and the seventh pin is connected to the output U_AB, the eighth pin. Connect the positive power supply VCC.
  • the universal chaotic system circuit designed by the invention not only has the flexibility of the breadboard, but also has the reliability of printing the PCB circuit board, and overcomes the existing universal chaotic circuit, and the frequent replacement of components caused by one system corresponding to each system. Weakness, strong versatility and reliability.
  • Figure 1 is a schematic view of the structure of the present invention.
  • the first pin of the operational amplifier U1 is connected to the second pin through the potentiometer U1_Y_F_R, and the sixth pin is connected through the potentiometer U1_Y_C_R.
  • the second pin is connected to the seventh pin of U1 through the input Y_I_1R, and the input Y_I_2R Connect the first pin of U2, the 3rd, 5th, 10th, and 12th pins are grounded, the 4th pin is connected to the positive power supply VCC, the 11th pin is connected to the negative power VEE, and the 6th pin is connected to the 7th pin through the capacitor Cy.
  • the 7th pin is connected to +Y, the Y is connected to Y through the resistor Y_OUT_R, the 8th pin is connected to +X, the X is connected to X through the resistor X_OUT_R, the 9th pin is connected through the capacitor Cx, and the 13th pin is connected to the 8th pin of U1 through the input X_I_1R.
  • the pin is connected to the 7th pin of U4 through input X_I_2R, the 14th pin is connected to the 13th pin through the potentiometer U1_X_F_R, and the 9th pin is connected through the potentiometer U1_X_C_R, wherein the potentiometers Y_I_1R, Y_I_2R, X_I_1R are 2.85K ⁇ , Potentiometer X_I_2R is 1K ⁇ , potentiometers X_I_3R, X_I_4R, Y_I_3R, Y_I_4R are all left floating, potentiometers U1_X_F_R, U1_X_C_R, U1_Y_F_R, U1_Y_C_R are all 10K ⁇ , and capacitors Cx and Cy are 10nF.
  • the first pin of the operational amplifier U2 is connected to the second pin through the potentiometer U2_U_F_R, the sixth pin is connected through the potentiometer U2_U_C_R, and the second pin is connected to the four inputs U_I_1R, U_I_2R, U_I_3R, U_I_4R, 3, 5, 10, 12 pin grounding, the 4th pin is connected to the positive power supply VCC, the 11th pin is connected to the negative power VEE, the 6th pin is connected to the 7th pin through the capacitor Cu, the 7th pin is connected to the +U, and the U is connected through the resistor U_OUT_R The 8th pin is connected to +Z, connected to Z through the resistor Z_OUT_R, and connected to the 9th pin through the capacitor Cz.
  • the 13th pin is connected to the 8th pin of U2 through the input Z_I_1R, and the 7th pin of U5 is connected through the input Z_I_2R.
  • the 14th pin is connected to the 13th pin through the potentiometer U2_Z_F_R, and the 9th pin is connected through the potentiometer U2_Z_C_R, wherein the potentiometer Z_I_1R is 33.4K ⁇ , the potentiometer Z_I_2R is 1K ⁇ , the potentiometer Z_I_3R, Z_I_4R, U_I_1R, U_I_2R, U_I_3R U_I_4R is suspended, potentiometer U2_Z_F_R, U2_Z_C_R are 10K ⁇ , potentiometer U2_U_F_R, U2_U_C_R are all suspended, capacitor Cz is 10nF, capacitor Cu is suspended.
  • the first pin of the operational amplifier U3 is connected to -X
  • the second pin is connected through the potentiometer U3_X_F_R
  • the second pin is connected to the +X through the potentiometer U3_X_IN_R
  • the third, fifth, ten, and 12 pins are grounded
  • the fourth lead The pin is connected to the positive power supply VCC
  • the 11th pin is connected to the negative VEE
  • the 6th pin is connected to the -Y through the potentiometer U3_Y_F_R
  • the Y3 is connected to the pot by the potentiometer U3_YINR
  • the 7th pin is connected to the -Y
  • the 8th pin is connected to the -Z.
  • the first pin of the multiplier U4 is connected to the eighth pin of U1, the second, fourth, and sixth pins are grounded, the third pin is connected to the eighth pin of U3, and the fifth pin is connected to the negative power supply VEE, the seventh pin.
  • the pin is connected to the 13th pin of U1 through the potentiometer X_I_2R, and the 8th pin is connected to the positive power supply VCC.
  • the first pin of the multiplier U5 is connected to the eighth pin of U1, the second, fourth, and sixth pins are grounded, the third pin is connected to the seventh pin of U1, and the fifth pin is connected to the negative power supply VEE, the seventh pin.
  • the pin is connected to the 13th pin of U2 through the potentiometer Z_I_2R, the 8th The pin is connected to the positive power supply VCC.
  • the first pin of the multiplier U6 is left floating, the second, fourth, and sixth pins are grounded, the third pin is left floating, the fifth pin is connected to the negative power supply VEE, the seventh pin is left floating, and the eighth pin is connected to the positive power supply VCC. .
  • the first pin of the multiplier U7 is left floating, the second, fourth, and sixth pins are grounded, the third pin is left floating, the fifth pin is connected to the negative power supply VEE, the seventh pin is left floating, and the eighth pin is connected to the positive power supply VCC. .
  • the first pin of the operational amplifier U1 is connected to the second pin through the potentiometer U1_Y_F_R, and the sixth pin is connected through the potentiometer U1_Y_C_R.
  • the second pin is connected to the seventh pin of U1 through the input Y_I_1R, and is connected to the U2 through the input Y_I_2R.
  • the first pin, the 3rd, 5th, 10th, and 12th pins are grounded, the 4th pin is connected to the positive power supply VCC, the 11th pin is connected to the negative power VEE, and the 6th pin is connected to the 7th pin through the capacitor Cy, the 7th lead Connect the pin to +Y, connect Y through the resistor Y_OUT_R, connect +X to the 8th pin, connect X through the resistor X_OUT_R, connect the 9th pin through the capacitor Cx, and connect the 13th pin to the 8th pin of U1 through the input X_I_1R.
  • the first pin of the operational amplifier U2 is connected to the second pin through the potentiometer U2_U_F_R, the sixth pin is connected through the potentiometer U2_U_C_R, and the second pin is connected to the first pin of U3 through the input U_I_1R, the third, fifth, and tenth. 12 pin grounding, the 4th pin is connected to the positive power supply VCC, the 11th pin is connected to the negative power VEE, the 6th pin is connected to the 7th pin through the capacitor Cu, the 7th pin is connected to the +U, and the U is connected to the U through the resistor U_OUT_R.
  • the 8th pin is connected to +Z, connected to Z through the resistor Z_OUT_R, and connected to the 9th pin through the capacitor Cz.
  • the 13th pin is connected to the 8th pin of U2 through the input Z_I_1R, and the 7th pin of U5 is connected through the input Z_I_2R.
  • the 14 pin is connected to the 13th pin through the potentiometer U2_Z_F_R, and the 9th pin is connected through the potentiometer U2_Z_C_R, wherein the potentiometer Z_I_1R is 33.4K ⁇ , the potentiometer Z_I_2R is 1K ⁇ , the potentiometer U_I_1R is 12.5K ⁇ , the potentiometer Z_I_3R, Z_I_4R U_I_2R, U_I_3R, and U_I_4R are all left floating. Potentiometers U2_Z_F_R, U2_Z_C_R, U2_U_F_R, and U2_U_C_R are all 10K ⁇ , and capacitors Cz and Cu are 10nF.
  • the first pin of the operational amplifier U3 is connected to -X, and the second pin and the second pin are connected through the potentiometer U3_X_F_R.
  • the potentiometer U3_Y_IN_R is connected to +Y, the 7th pin is connected to -Y, the 8th pin is connected to -Z, the 9th pin is connected through the potentiometer U3_Z_F_R, the 9th pin is connected to +Z through U3_Z_IN_R, and the 13th pin is passed through the potentiometer U3_U_F_R is connected to the 14th pin, and the 14th pin is connected to +U through the potentiometer U3_U_IN_R.
  • the potentiometers U3_X_F_R, U3_X_IN_R, U3_Y_F_R, U3_Y_IN_R, U3_Z_IN_R, U3_Z_F_R are all 10K ⁇ , U3_U_F_R, U3_U_IN_R are left floating.
  • the first pin of the multiplier U4 is connected to the eighth pin of U1, the second, fourth, and sixth pins are grounded, the third pin is connected to the eighth pin of U3, and the fifth pin is connected to the negative power supply VEE, the seventh pin.
  • the pin is connected to the 13th pin of U1 through the potentiometer X_I_2R, and the 8th pin is connected to the positive power supply VCC.
  • the first pin of the multiplier U5 is connected to the eighth pin of U1, the second, fourth, and sixth pins are grounded, the third pin is connected to the seventh pin of U1, and the fifth pin is connected to the negative power supply VEE, the seventh pin.
  • the pin is connected to the 13th pin of U2 through the potentiometer Z_I_2R, and the 8th pin is connected to the positive power supply VCC.
  • the first pin of the multiplier U6 is left floating, the second, fourth, and sixth pins are grounded, the third pin is left floating, the fifth pin is connected to the negative power supply VEE, the seventh pin is left floating, and the eighth pin is connected to the positive power supply VCC. .
  • the first pin of the multiplier U7 is left floating, the second, fourth, and sixth pins are grounded, the third pin is left floating, the fifth pin is connected to the negative power supply VEE, the seventh pin is left floating, and the eighth pin is connected to the positive power supply VCC. .

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Abstract

一种通用混沌系统的电路设计，各连接端焊接排孔，连接线可以插入排孔，反复使用，利用运算放大器U1、运算放大器U2及电阻和电容构成四组反相加法器和四组反相积分器，每组反相加法器有四路输入端，每路输入端引出四个输入信号，利用运算放大器U3及电阻和电容构成四组反相器，利用乘法器U4、U5、U6和U7分别实现乘法运算，每组输出各引出正信号和负信号2路输出，每路输出信号各引出5个输出端，所述运算放大器U1、运算放大器U2和运算放大器U3采用LF347N，所述乘法器U4和U5采用AD633JN。该通用混沌系统电路，既有面包板的灵活性，又具有印制PCB电路板的可靠性，同时克服了己有通用混沌电路，每一系统对应一块电路而引起的频繁更换元件的弱点，具有较强的通用性和可靠性。

Description

一种通用混沌系统的电路设计 技术领域
本发明涉及一种电路设计，特别涉及一种通用混沌系统的电路设计。
背景技术
当前的混沌系统电路一般采用面包板进行电路设计，用面包板进行电路设计费时费用且出错率比较高，出错不容易检查，如采用PCB印制电路板进行设计，对应每一个混沌系统要进行一次设计，灵活度比较低，设计周期比较长，已有的通用混沌系统电路采用焊接方式，每块电路板可以设计一个混沌系统电路，但存在用板量比较大，频繁更换元件，容易引起元件的损坏。
发明内容
针对现有技术的不足，本发明提出了一种通用混沌系统的电路设计，各连接端焊接排孔，连接线可以插入排孔，反复使用，利用运算放大器U1、运算放大器U2及电阻和电容构成四组反相加法器和四组反相积分器，每组反相加法器有四路输入端，每路输入端引出四个输入信号，利用运算放大器U3及电阻和电容构成四组反相器，利用乘法器U4、U5、U6和U7分别实现乘法运算，每组输出各引出正信号和负信号2路输出，每路输出信号各引出5个输出端，所述运算放大器U1、运算放大器U2和运算放大器U3采用LF347N，所述乘法器U4和U5采用AD633JN。
所述运算放大器U1第1引脚通过电位器U1_Y_F_R接第2引脚，通过电位器U1_Y_C_R接第6引脚，第2引脚接四路输入Y_I_1R、Y_I_2R、Y_I_3R、Y_I_4R，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电容Cy接第7引脚，第7引脚接+Y，通过电阻Y_OUT_R接Y，第8引脚接+X，通过电阻X_OUT_R接X，通过电容Cx接第9引脚，第13引脚接四路输入X_I_1R、X_I_2R、X_I_3R、X_I_4R，第14引脚通过电位器U1_X_F_R接第13引脚，通过电位器U1_X_C_R接第9引脚。
所述运算放大器U2第1引脚通过电位器U2_U_F_R接第2引脚，通过电位器U2_U_C_R接第6引脚，第2引脚接四路输入U_I_1R、U_I_2R、U_I_3R、U_I_4R，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电容Cu接第7引脚，第7引脚接+U，通过电阻U_OUT_R接U，第8引脚接+Z，通过电阻Z_OUT_R接Z，通过电容Cz接第9引脚，第13引脚接四路输入Z_I_1R、Z_I_2R、 Z_I_3R、Z_I_4R，第14引脚通过电位器U2_Z_F_R接第13引脚，通过电位器U2_Z_C_R接第9引脚。
所述运算放大器U3第1引脚连接-X，通过电位器U3_X_F_R连接第2引脚，第2引脚通过电位器U3_X_IN_R连接+X，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电位器U3_Y_F_R接-Y，通过电位器U3_Y_IN_R接+Y，第7引脚接-Y，第8引脚接-Z，通过电位器U3_Z_F_R接第9引脚，第9引脚通过U3_Z_IN_R接+Z，第13引脚通过电位器U3_U_F_R接第14引脚，第14引脚通过电位器U3_U_IN_R接+U。
所述乘法器U4第1引脚接X_A，第2、4、6引脚接地，第3引脚接X_B，第5引脚连接负电源VEE，第7引脚接输出X_AB，第8引脚连接正电源VCC。
所述乘法器U5第1引脚接Y_A，第2、4、6引脚接地，第3引脚接Y_B，第5引脚连接负电源VEE，第7引脚接输出Y_AB，第8引脚连接正电源VCC。
所述乘法器U6第1引脚接Z_A，第2、4、6引脚接地，第3引脚接Z_B，第5引脚连接负电源VEE，第7引脚接输出Z_AB，第8引脚连接正电源VCC。
所述乘法器U7第1引脚接U_A，第2、4、6引脚接地，第3引脚接U_B，第5引脚连接负电源VEE，第7引脚接输出U_AB，第8引脚连接正电源VCC。
有益效果
本发明设计的通用混沌系统电路，既有面包板的灵活性，又具有印制PCB电路板的可靠性，同时克服了已有通用混沌电路，每一系统对应一块电路而引起的频繁更换元件的弱点，具有较强的通用性和可靠性。
附图说明
图1是本实用新型的结构示意图。
具体实施方式
下面结合附图对本发明作更进一步的详细描述。
(1)以Yang-Chen系统为例说明本发明在三维混沌系统中的使用方法，参见图1-图8，Yang-Chen系统的数学模型为：
Figure PCTCN2015000262-appb-000001
所述运算放大器U1第1引脚通过电位器U1_Y_F_R接第2引脚，通过电位器U1_Y_C_R接第6引脚，第2引脚通过输入Y_I_1R接U1的第7引脚，通过输入Y_I_2R 接U2的第1引脚，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电容Cy接第7引脚，第7引脚接+Y，通过电阻Y_OUT_R接Y，第8引脚接+X，通过电阻X_OUT_R接X，通过电容Cx接第9引脚，第13引脚通过输入X_I_1R接U1的第8引脚，通过输入X_I_2R接U4的第7引脚，第14引脚通过电位器U1_X_F_R接第13引脚，通过电位器U1_X_C_R接第9引脚，其中电位器Y_I_1R、Y_I_2R、X_I_1R均为2.85KΩ，电位器X_I_2R为1KΩ，电位器X_I_3R、X_I_4R、Y_I_3R、Y_I_4R均悬空，电位器U1_X_F_R、U1_X_C_R、U1_Y_F_R、U1_Y_C_R均为10KΩ，电容Cx、Cy均为10nF，。
所述运算放大器U2第1引脚通过电位器U2_U_F_R接第2引脚，通过电位器U2_U_C_R接第6引脚，第2引脚接四路输入U_I_1R、U_I_2R、U_I_3R、U_I_4R，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电容Cu接第7引脚，第7引脚接+U，通过电阻U_OUT_R接U，第8引脚接+Z，通过电阻Z_OUT_R接Z，通过电容Cz接第9引脚，第13引脚通过输入Z_I_1R接U2的第8引脚，通过输入Z_I_2R接U5的第7引脚，第14引脚通过电位器U2_Z_F_R接第13引脚，通过电位器U2_Z_C_R接第9引脚，其中电位器Z_I_1R均为33.4KΩ，电位器Z_I_2R为1KΩ，电位器Z_I_3R、Z_I_4R、U_I_1R、U_I_2R、U_I_3R、U_I_4R均悬空，电位器U2_Z_F_R、U2_Z_C_R均为10KΩ，电位器U2_U_F_R、U2_U_C_R均悬空，电容Cz为10nF，电容Cu悬空。
所述运算放大器U3第1引脚连接-X，通过电位器U3_X_F_R连接第2引脚，第2引脚通过电位器U3_X_IN_R连接+X，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电位器U3_Y_F_R接-Y，通过电位器U3_YINR接+Y，第7引脚接-Y，第8引脚接-Z，通过电位器U3_Z_F_R接第9引脚，第9引脚通过U3_Z_IN_R接+Z，第13引脚通过电位器U3_U_F_R接第14引脚，第14引脚通过电位器U3_U_IN_R接+U，其中电位器U3_X_F_R、U3_X_IN_R、U3_Y_F_R、U3_Y_IN_R、U3_Z_IN_R、U3_Z_F_R均为10KΩ，U3_U_F_R、U3_U_IN_R悬空。
所述乘法器U4第1引脚接U1的第8引脚，第2、4、6引脚接地，第3引脚接U3的第8引脚，第5引脚连接负电源VEE，第7引脚通过电位器X_I_2R接U1的第13引脚，第8引脚连接正电源VCC。
所述乘法器U5第1引脚接U1的第8引脚，第2、4、6引脚接地，第3引脚接U1的第7引脚，第5引脚连接负电源VEE，第7引脚通过电位器Z_I_2R接U2的第13引脚，第8 引脚连接正电源VCC。
所述乘法器U6第1引脚悬空，第2、4、6引脚接地，第3引脚悬空，第5引脚连接负电源VEE，第7引脚悬空，第8引脚连接正电源VCC。
所述乘法器U7第1引脚悬空，第2、4、6引脚接地，第3引脚悬空，第5引脚连接负电源VEE，第7引脚悬空，第8引脚连接正电源VCC。
(2)以Yang-Chen超系统为例说明本发明在四维超混沌系统中的使用方法，参见图1-图8，Yang-Chen超混沌系统的数学模型为：
Figure PCTCN2015000262-appb-000002
所述运算放大器U1第1引脚通过电位器U1_Y_F_R接第2引脚，通过电位器U1_Y_C_R接第6引脚，第2引脚通过输入Y_I_1R接U1的第7引脚，通过输入Y_I_2R接U2的第1引脚，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电容Cy接第7引脚，第7引脚接+Y，通过电阻Y_OUT_R接Y，第8引脚接+X，通过电阻X_OUT_R接X，通过电容Cx接第9引脚，第13引脚通过输入X_I_1R接U1的第8引脚，通过输入X_I_2R接U4的第7引脚，通过输入X_I_3R接U2的第7引脚，第14引脚通过电位器U1_X_F_R接第13引脚，通过电位器U1_X_C_R接第9引脚，其中电位器Y_I_1R、Y_I_2R、X_I_1R均为2.85KΩ，电位器X_I_2R为1KΩ，电位器X_I_3R为100KΩ，电位器X_I_4R、Y_I_3R、Y_I_4R均悬空，电位器U1_X_F_R、U1_X_C_R、U1_Y_F_R、U1_Y_C_R均为10KΩ，电容Cx、Cy均为10nF，。
所述运算放大器U2第1引脚通过电位器U2_U_F_R接第2引脚，通过电位器U2_U_C_R接第6引脚，第2引脚通过输入U_I_1R接U3的第1引脚，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电容Cu接第7引脚，第7引脚接+U，通过电阻U_OUT_R接U，第8引脚接+Z，通过电阻Z_OUT_R接Z，通过电容Cz接第9引脚，第13引脚通过输入Z_I_1R接U2的第8引脚，通过输入Z_I_2R接U5的第7引脚，第14引脚通过电位器U2_Z_F_R接第13引脚，通过电位器U2_Z_C_R接第9引脚，其中电位器Z_I_1R均为33.4KΩ，电位器Z_I_2R为1KΩ，电位器U_I_1R为12.5KΩ，电位器Z_I_3R、Z_I_4R、U_I_2R、U_I_3R、U_I_4R均悬空，电位器U2_Z_F_R、U2_Z_C_R、U2_U_F_R、U2_U_C_R均为10KΩ，电容Cz、Cu均为10nF。
所述运算放大器U3第1引脚连接-X，通过电位器U3_X_F_R连接第2引脚，第2引脚 通过电位器U3_X_IN_R连接+X，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电位器U3_Y_F_R接-Y，通过电位器U3_Y_IN_R接+Y，第7引脚接-Y，第8引脚接-Z，通过电位器U3_Z_F_R接第9引脚，第9引脚通过U3_Z_IN_R接+Z，第13引脚通过电位器U3_U_F_R接第14引脚，第14引脚通过电位器U3_U_IN_R接+U，其中电位器U3_X_F_R、U3_X_IN_R、U3_Y_F_R、U3_Y_IN_R、U3_Z_IN_R、U3_Z_F_R均为10KΩ，U3_U_F_R、U3_U_IN_R悬空。
所述乘法器U4第1引脚接U1的第8引脚，第2、4、6引脚接地，第3引脚接U3的第8引脚，第5引脚连接负电源VEE，第7引脚通过电位器X_I_2R接U1的第13引脚，第8引脚连接正电源VCC。
所述乘法器U5第1引脚接U1的第8引脚，第2、4、6引脚接地，第3引脚接U1的第7引脚，第5引脚连接负电源VEE，第7引脚通过电位器Z_I_2R接U2的第13引脚，第8引脚连接正电源VCC。
所述乘法器U6第1引脚悬空，第2、4、6引脚接地，第3引脚悬空，第5引脚连接负电源VEE，第7引脚悬空，第8引脚连接正电源VCC。
所述乘法器U7第1引脚悬空，第2、4、6引脚接地，第3引脚悬空，第5引脚连接负电源VEE，第7引脚悬空，第8引脚连接正电源VCC。
当然，上述说明并非对本发明的限制，本发明也不仅限于上述举例，本技术领域的普通技术人员在本发明的实质范围内所做出的变化、改型、添加或替换，也属于本发明的保护范围。

Claims (8)

  1. 一种通用混沌系统的电路设计，其特征是在于，利用运算放大器U1、运算放大器U2及电阻和电容构成四组反相加法器和四组反相积分器，每组反相加法器有四路输入端，每路输入端引出四个输入信号，利用运算放大器U3及电阻和电容构成四组反相器，利用乘法器U4、U5、U6和U7分别实现乘法运算，每组输出各引出正信号和负信号2路输出，每路输出信号各引出5个输出端，所述运算放大器U1、运算放大器U2和运算放大器U3采用LF347N，所述乘法器U4和U5采用AD633JN；
  2. 根据权利要求1所述一种通用混沌系统的电路设计，所述运算放大器U1第1引脚通过电位器U1_Y_F_R接第2引脚，通过电位器U1_Y_C_R接第6引脚，第2引脚接四路输入Y_I_1R、Y_I_2R、Y_I_3R、Y_I_4R，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电容Cy接第7引脚，第7引脚接+Y，通过电阻Y_OUT_R接Y，第8引脚接+X，通过电阻X_OUT_R接X，通过电容Cx接第9引脚，第13引脚接四路输入X_I_1R、X_I_2R、X_I_3R、X_I_4R，第14引脚通过电位器U1_X_F_R接第13引脚，通过电位器U1_X_C_R接第9引脚；
  3. 根据权利要求1所述一种通用混沌系统的电路设计，所述运算放大器U2第1引脚通过电位器U2_U_F_R接第2引脚，通过电位器U2_U_C_R接第6引脚，第2引脚接四路输入U_I_1R、U_I_2R、U_I_3R、U_I_4R，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电容Cu接第7引脚，第7引脚接+U，通过电阻U_OUT_R接U，第8引脚接+Z，通过电阻Z_OUT_R接Z，通过电容Cz接第9引脚，第13引脚接四路输入Z_I_1R、Z_I_2R、Z_I_3R、Z_I_4R，第14引脚通过电位器U2_Z_F_R接第13引脚，通过电位器U2_Z_C_R接第9引脚；
  4. 根据权利要求1所述一种通用混沌系统的电路设计，所述运算放大器U3第1引脚连接-X，通过电位器U3_X_F_R连接第2引脚，第2引脚通过电位器U3_X_IN_R连接+X，第3、5、10、12引脚接地，第4引脚接正电源VCC，第11引脚接负电VEE，第6引脚通过电位器U3_Y_F_R接-Y，通过电位器U3_Y_IN_R接+Y，第7引脚接-Y，第8引脚接-Z，通过电位器U3_Z_F_R接第9引脚，第9引脚通过U3_Z_IN_R接+Z，第13引脚通过电位器U3_U_F_R接第14引脚，第14引脚通过电位器U3_U_IN_R接+U；
  5. 根据权利要求1所述一种通用混沌系统的电路设计，所述乘法器U4第1引脚接X_A，第2、4、6引脚接地，第3引脚接X_B，第5引脚连接负电源VEE，第7引脚接输出X_AB，第8引脚连接正电源VCC；
  6. 根据权利要求1所述一种通用混沌系统的电路设计，所述乘法器U5第1引脚接Y_A，第2、4、6引脚接地，第3引脚接Y_B，第5引脚连接负电源VEE，第7引脚接输出Y_AB， 第8引脚连接正电源VCC；
  7. 根据权利要求1所述一种通用混沌系统的电路设计，所述乘法器U6第1引脚接Z_A，第2、4、6引脚接地，第3引脚接Z_B，第5引脚连接负电源VEE，第7引脚接输出Z_AB，第8引脚连接正电源VCC；
  8. 根据权利要求1所述一种通用混沌系统的电路设计，所述乘法器U7第1引脚接U_A，第2、4、6引脚接地，第3引脚接U_B，第5引脚连接负电源VEE，第7引脚接输出U_AB，第8引脚连接正电源VCC。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112422262A (zh) * 2019-08-23 2021-02-26 天津科技大学 一种具有双簇保守混沌流的广义Sprott-A系统及其电路实现

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104184576A (zh) * 2014-09-02 2014-12-03 王忠林 一种通用混沌系统的电路设计
CN105790733A (zh) * 2016-04-06 2016-07-20 张晓丹 一种具有类心音波形信号的系统及电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201336097Y (zh) * 2008-12-31 2009-10-28 张新国 一种混沌电路实验装置
CN102739392A (zh) * 2012-06-29 2012-10-17 东北大学 一种Chen混沌信号发生器
CN102752099A (zh) * 2012-06-29 2012-10-24 东北大学 一种Lorenz混沌信号发生器
CN102752100A (zh) * 2012-06-29 2012-10-24 东北大学 一种Lü混沌信号发生器
CN104184576A (zh) * 2014-09-02 2014-12-03 王忠林 一种通用混沌系统的电路设计

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202334551U (zh) * 2011-12-13 2012-07-11 滨州学院 实现分数阶三个系统自动切换混沌系统的电路
CN202503530U (zh) * 2012-04-06 2012-10-24 滨州学院 三维混沌系统
CN102903282B (zh) * 2012-10-26 2014-08-27 玉林师范学院 整数阶分数阶多功能混沌实验仪

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201336097Y (zh) * 2008-12-31 2009-10-28 张新国 一种混沌电路实验装置
CN102739392A (zh) * 2012-06-29 2012-10-17 东北大学 一种Chen混沌信号发生器
CN102752099A (zh) * 2012-06-29 2012-10-24 东北大学 一种Lorenz混沌信号发生器
CN102752100A (zh) * 2012-06-29 2012-10-24 东北大学 一种Lü混沌信号发生器
CN104184576A (zh) * 2014-09-02 2014-12-03 王忠林 一种通用混沌系统的电路设计

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112422262A (zh) * 2019-08-23 2021-02-26 天津科技大学 一种具有双簇保守混沌流的广义Sprott-A系统及其电路实现
CN112422262B (zh) * 2019-08-23 2022-05-20 天津科技大学 一种具有双簇保守混沌流的广义Sprott-A系统及其构建方法

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