WO2016041105A1 - 基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路 - Google Patents

基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路 Download PDF

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WO2016041105A1
WO2016041105A1 PCT/CN2014/001021 CN2014001021W WO2016041105A1 WO 2016041105 A1 WO2016041105 A1 WO 2016041105A1 CN 2014001021 W CN2014001021 W CN 2014001021W WO 2016041105 A1 WO2016041105 A1 WO 2016041105A1
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pin
resistor
operational amplifier
circuit module
order
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PCT/CN2014/001021
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李建庆
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李建庆
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

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  • the invention relates to a universal fractional-order integration circuit module and a 0.2-order chaotic system circuit implementation thereof, in particular to a 0.2-order Chen chaotic system circuit based on a chain-type fractional-order integration circuit module.
  • the resistance and capacitance of the circuit implementing the fractional-order chaotic system are both unconventional resistors and capacitors, it is generally implemented by a series connection of resistors and capacitors.
  • the main method of implementation is to combine the existing resistors and capacitors on the breadboard.
  • the method has low reliability and stability, and is easy to make mistakes, and is difficult to find after an error.
  • the present invention overcomes this problem and adopts a chain structure to design and manufacture a PCB circuit.
  • the circuit is composed of four parts. Part of the general fractional-order integral module circuit consisting of four resistors in parallel with a potentiometer and four capacitors in parallel.
  • the 0.2-order fractional-order integration circuit consists of four parts. This method is used to achieve 0.2-order fractional order chaos. System circuit, high reliability, not easy to make mistakes.
  • the technical problem to be solved by the present invention is to provide a 0.2-order Chen chaotic system circuit based on a chain-type fractional-order integration circuit module, and the present invention adopts the following technical means to achieve the object of the invention:
  • a chain fractional integration circuit module characterized in that a resistor Rx is connected in parallel with a capacitor Cx to form a first portion, a resistor Ry is connected in parallel with a capacitor Cy to form a second portion, and a resistor Rz is connected in parallel with the capacitor Cz to form a third portion.
  • the resistor Rw is connected in parallel with the capacitor Cw to form a fourth portion.
  • the cascade input pins PI1, PI2 and the output pin P are connected to the first portion, the first portion is connected to the output pin P1 and the second portion, and the second portion is connected to the output pin.
  • P2 and the third part the third part is connected to the output pin P3 and the fourth part, and the fourth part is connected to the output pin P4 and the cascade output pins PO1, PO2.
  • a chain type fractional integration circuit module wherein said resistor Rx is composed of a potentiometer Rx1 and resistors Rx2, Rx3, Rx4, Rx5 connected in series, said capacitor Cx being capacitor Cx1.
  • Cx2, Cx3, and Cx4 are formed in parallel
  • the resistor Ry is composed of a potentiometer Ry1 and resistors Ry2, Ry3, Ry4, and Ry5 connected in series, and the capacitor Cy is composed of capacitors Cy1, Cy2, Cy3, Cy4, in parallel
  • the resistor Rz is composed of The potentiometer Rz1 and the resistors Rz2, Rz3, Rz4, and Rz5 are formed in series, and the capacitor Cz is composed of capacitors Cz1, Cz2, Cz3, and Cz4 in parallel
  • the resistor Rw is composed of a potentiometer Rw1 and resistors Rw2, Rw3, Rw4, and Rw5 in series.
  • the capacitor Cw is composed of capacitors Cw1, Cw2, Cw3, and Cw4
  • a 0.2-order Chen chaotic system circuit based on a chain fractional integration circuit module characterized in that:
  • the analog circuit is constructed by using the operational amplifier U1, the operational amplifier U2, the resistor and the 0.2-order integral circuit module U5, the 0.2-order integral circuit module U6, and the 0.2-order integral circuit module U7 to form an inverting adder.
  • the inverse 0.2-order integrator, multiply operation is performed by the multiplier U3 and the multiplier U4, the operational amplifier U1 and the operational amplifier U2 adopt LF347N, and the multiplier U3 and the multiplier U4 adopt AD633JN;
  • the operational amplifier U1 is connected to an operational amplifier U2, a multiplier U3, a multiplier U4 and a 0.2-order integrating circuit module U5, and a 0.2-order integrating circuit module U6.
  • the operational amplifier U2 is connected to a multiplier U3, a multiplier U4, and a 0.2-order integrating circuit.
  • Module U7, the multiplier U3 is connected to the operational amplifier U1, the multiplier U4 is connected to the operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of U1 through the resistor R9, and the second pin is connected to the first pin of U1 through the resistor R6, and the third, fifth, ten, and twelve pins are connected.
  • Grounding the fourth pin is connected to VCC
  • the eleventh pin is connected to VEE
  • the sixth pin is connected to the P pin of the 0.2-order integrating circuit module U6,
  • the seventh pin is connected to the output y
  • the second-order integrating circuit is connected.
  • the P3 pin of the module U6 is connected to the first pin of the multiplier U4, connected to the second pin through the resistor R5, connected to the 13th pin through the resistor R1, and the output pin x is connected to the 8th pin through the resistor R8.
  • the first, second, sixth, and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and 12th pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the eighth pin is outputted by z.
  • Connect the P3 pin of the 0.2-step integration circuit module U7 connect the third pin of the multiplier U3, connect the 9th pin through the resistor R12, and connect the 9th pin to the P pin of the 0.2-order integration circuit module U7.
  • the 13th pin is connected to the 14th pin through the resistor R11, and the 14th pin is connected to the 9th pin through the resistor R13;
  • the first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE.
  • the 7 pin is connected to the 6th pin of U1 through the resistor R7, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the seventh pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U1.
  • the second, fourth, and sixth pins are grounded, and the fifth pin is connected to the VEE.
  • the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and the 8th pin is connected to VCC;
  • the PI1, PI2, PO1, PO2, P1, P2, and P3 pins of the 0.2-order integrating circuit module U5 are left floating, the P pin is connected to the 9th pin of the operational amplifier U1, and the P4 pin is connected to the 8th of the operational amplifier U1. Pin
  • the P11, PI2, PO1, PO2, P1, P2, and P3 pins of the 0.2-order integrating circuit module U6 are suspended, the P pin is connected to the sixth pin of the operational amplifier U1, and the P4 pin is connected to the seventh of the operational amplifier U1. Pin
  • the PI1, PI2, PO1, PO2, P1, P2, and P3 pins of the 0.2-order integrating circuit module U7 are suspended, the P pin is connected to the 9th pin of the operational amplifier U2, and the P4 pin is connected to the 8th of the operational amplifier U2. Pin.
  • the beneficial effects of the invention are: using a chain structure, designing and manufacturing a PCB circuit, the circuit is composed of four parts, each part is composed of four resistors and one potentiometer in series, and a universal fractional integration module composed of four capacitors in parallel
  • the circuit, the 0.2-order fractional-order integration circuit is composed of four parts.
  • the 0.2-order fractional-order chaotic system circuit is realized by this method, which has high reliability and is not easy to be mistaken.
  • FIG. 1 is a schematic diagram showing the internal structure of a chain type fractional integration circuit module of the present invention (a), an internal actual connection diagram (b), and an actual connection diagram (c) of a 0.2-order integration circuit.
  • FIG. 2 is a schematic diagram of a circuit connection structure of a preferred embodiment of the present invention.
  • 3 and 4 are actual connection diagrams of the circuit of the present invention.
  • a chain fractional integration circuit module characterized in that a resistor Rx is connected in parallel with a capacitor Cx to form a first portion, a resistor Ry is connected in parallel with a capacitor Cy to form a second portion, and a resistor Rz is connected in parallel with the capacitor Cz to form a third portion.
  • the resistor Rw is connected in parallel with the capacitor Cw to form a fourth portion.
  • the cascade input pins PI1, PI2 and the output pin P are connected to the first portion, the first portion is connected to the output pin P1 and the second portion, and the second portion is connected to the output pin.
  • P2 and the third part the third part is connected to the output pin P3 and the fourth part, and the fourth part is connected to the output pin P4 and the cascade output pins PO1, PO2.
  • a chain type fractional integration circuit module wherein said resistor Rx is composed of a potentiometer Rx1 and resistors Rx2, Rx3, Rx4, Rx5 connected in series, said capacitor Cx being capacitor Cx1.
  • Cx2, Cx3, and Cx4 are formed in parallel
  • the resistor Ry is composed of a potentiometer Ry1 and resistors Ry2, Ry3, Ry4, and Ry5 connected in series, and the capacitor Cy is composed of capacitors Cy1, Cy2, Cy3, Cy4, in parallel
  • the resistor Rz is composed of The potentiometer Rz1 and the resistors Rz2, Rz3, Rz4, and Rz5 are formed in series, and the capacitor Cz is composed of capacitors Cz1, Cz2, Cz3, and Cz4 in parallel
  • the resistor Rw is composed of a potentiometer Rw1 and resistors Rw2, Rw3, Rw4, and Rw5 in series.
  • the capacitor Cw is composed of capacitors Cw1, Cw2, Cw3, and Cw4
  • the resistance Ry 0.607M
  • the potentiometer Ry1 5.1K
  • the capacitance Cy 2.93uF
  • the capacitance Cy1 2.2uF
  • Cy2 220nF
  • Cy3 470nF
  • Cy4 47nF
  • the resistance Rz
  • a 0.2-order Chen chaotic system circuit based on a chain fractional integration circuit module characterized in that:
  • the analog circuit is constructed by using the operational amplifier U1, the operational amplifier U2, the resistor and the 0.2-order integral circuit module U5, the 0.2-order integral circuit module U6, and the 0.2-order integral circuit module U7 to form an inverting adder.
  • the inverse 0.2-order integrator, multiply operation is performed by the multiplier U3 and the multiplier U4, the operational amplifier U1 and the operational amplifier U2 adopt LF347N, and the multiplier U3 and the multiplier U4 adopt AD633JN;
  • the operational amplifier U1 is connected to an operational amplifier U2, a multiplier U3, a multiplier U4 and a 0.2-order integrating circuit module U5, and a 0.2-order integrating circuit module U6.
  • the operational amplifier U2 is connected to a multiplier U3, a multiplier U4, and a 0.2-order integrating circuit.
  • Module U7, the multiplier U3 is connected to the operational amplifier U1, the multiplier U4 is connected to the operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of U1 through the resistor R9, and the second pin is connected to the first pin of U1 through the resistor R6, and the third, fifth, ten, and twelve pins are connected.
  • the fourth pin is connected to VCC
  • the eleventh pin is connected to VEE
  • the sixth pin is connected to the P pin of the 0.2-order integrating circuit module U6
  • the seventh pin is connected to the output y
  • the P3 lead of the 0.2-order integrating circuit module U6 is connected.
  • the first pin of the multiplier U4 is connected to the second pin through the resistor R5, connected to the 13th pin through the resistor R1, and the output pin x is connected to the 8th pin through the resistor R8 and the 6th pin.
  • the ninth pin Connected to the 9th pin through the resistor R4, connected to the P3 pin of the 0.2-order integrating circuit module U5, connected to the first pin of the multiplier U3, connected to the third pin of the multiplier U4, the ninth pin Connect the P pin of the 0.2-order integrating circuit module U5, the 13th pin is connected to the 14th pin through the resistor R2, and the 14th pin is connected to the 9th pin through the resistor R3;
  • the first, second, sixth, and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and 12th pins are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the eighth pin is outputted by z.
  • Connect the P3 pin of the 0.2-step integration circuit module U7 connect the third pin of the multiplier U3, connect the 9th pin through the resistor R12, and connect the 9th pin to the P pin of the 0.2-order integration circuit module U7.
  • the 13th pin is connected to the 14th pin through the resistor R11, and the 14th pin is connected to the 9th pin through the resistor R13:
  • the first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, the third pin is connected to the eighth pin of U2, the second, fourth, and sixth pins are grounded, and the fifth pin is connected to VEE.
  • the 7 pin is connected to the 6th pin of U1 through the resistor R7, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the seventh pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U1.
  • the second, fourth, and sixth pins are grounded, and the fifth pin is connected to the VEE.
  • the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and the 8th pin is connected to VCC;
  • the PI1, PI2, PO1, PO2, P1, P2, and P3 pins of the 0.2-order integrating circuit module U5 are left floating, the P pin is connected to the 9th pin of the operational amplifier U1, and the P4 pin is connected to the 8th of the operational amplifier U1. Pin
  • the PI1, PI2, PO1, PO2, P1, P2, and P3 pins of the 0.2-order integrating circuit module U6 are left floating, the P pin is connected to the sixth pin of the operational amplifier U1, and the P4 pin is connected to the seventh of the operational amplifier U1. Pin
  • the PI1, PI2, PO1, PO2, P1, P2, and P3 pins of the 0.2-order integrating circuit module U7 are suspended, the P pin is connected to the 9th pin of the operational amplifier U2, and the P4 pin is connected to the 8th of the operational amplifier U2. Pin.

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Abstract

一种基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路，链式分数阶积分电路模块，电阻Rx与电容Cx并联，形成第一部分，电阻Ry与电容Cy并联，形成第二部分，电阻Rz与电容Cz并联，形成第三部分，电阻Rw与电容Cw并联，形成第四部分，级联输入引脚PI1、PI2和输出引脚P接第一部分，第一部分接输出引脚P1和第二部分，第二部分接输出引脚P2和第三部分，第三部分接输出引脚P3和第四部分，第四部分接输出引脚P4和级联输出引脚P01、P02。采用链式结构，设计制作了PCB电路，0.2阶分数阶积分电路由五部分组成，采用这种方法的实现0.2阶分数阶混沌系统电路，可靠性高，不易出错。

Description

基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路 技术领域
本发明涉及一种通用分数阶积分电路模块及其0.2阶混沌系统电路实现，特别涉及一种基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路。
背景技术
因为实现分数阶混沌系统的电路的电阻和电容都是非常规电阻和电容，一般采用电阻串联和电容并联的方法实现，目前，实现的主要方法是利用现有的电阻和电容在面包板上组合的方法，这种方法可靠性和稳定性比较低，并且存在容易出错，出错后不易查找等问题，本发明为克服这个问题，采用链式结构，设计制作了PCB电路，电路由四部分组成，每部分又由四个电阻和一个电位器串联后，与四个电容并联组成的通用分数阶积分模块电路，0.2阶分数阶积分电路正好由四部分组成，采用这种方法的实现0.2阶分数阶混沌系统电路，可靠性高，不易出错。
发明内容
本发明要解决的技术问题是提供一种基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路，本发明采用如下技术手段实现发明目的：
1、一种链式分数阶积分电路模块，其特征是在于：电阻Rx与电容Cx并联，形成第一部分，电阻Ry与电容Cy并联，形成第二部分，电阻Rz与电容Cz并联，形成第三部分，电阻Rw与电容Cw并联，形成第四部分，级联输入引脚PI1、PI2和输出引脚P接第一部分，第一部分接输出引脚P1和第二部分，第二部分接输出引脚P2和第三部分，第三部分接输出引脚P3和第四部分，第四部分接输出引脚P4和级联输出引脚PO1、PO2。
2、根据权利要求1所述一种链式分数阶积分电路模块，其特征在于：所述电阻Rx由电位器Rx1和电阻Rx2、Rx3、Rx4、Rx5串联组成，所述电容Cx由电容Cx1、Cx2、Cx3、Cx4并联组成；所述电阻Ry由电位器Ry1和电阻Ry2、Ry3、Ry4、Ry5串联组成，所述电容Cy由电容Cy1、Cy2、Cy3、Cy4，并联组成；所述电阻Rz由电位器Rz1和电阻Rz2、Rz3、Rz4、Rz5串联组成，所述电容Cz由电容Cz1、Cz2、Cz3、Cz4并联组成；所述电阻Rw由电位器Rw1和电阻Rw2、Rw3、Rw4、Rw5串联组成，所述电容Cw由电容Cw1、Cw2、Cw3、Cw4并联组成。
3、根据权利要求1所述一种链式分数阶积分电路模块，所述0.2阶积分电路模块，其特征在于：所述级联输入引脚PI1、PI2悬空，所述输出引脚P1、P2、P3悬空，所述级联输出引脚PO1、PO2悬空，所述电阻Rx＝1.13M，所述电位器Rx1＝1M，所述电阻Rx2＝100K、 Rx3＝20K、Rx4＝10K、Rx5＝0K，所述电容Cx＝27.99uF，所述电容Cx1＝10uF、Cx2＝10uF、Cx3＝4.7uF、Cx4＝3.2.7uF；所述电阻Ry＝0.607M，所述电位器Ry1＝5.1K，所述电阻Ry2＝500K、Ry3＝100K、Ry4＝2K、Ry5＝0K，所述电容Cy＝2.93uF，所述电容Cy1＝2.2uF、Cy2＝220nF、Cy3＝470nF、Cy4＝47nF；所述电阻Rz＝0.35M，所述电位器Rz1＝51K和所述电阻Rz2＝200K、Rz3＝100K、Rz4＝0K、Rz5＝0K，所述电容Cz＝0.285uF，所述电容Cz1＝220nF、Cz2＝47nF、Cz＝10nF、Cz4＝10nF；所述电阻Rw＝0.425M，所述电位器Rw1＝5.1K，所述电阻Rw2＝200K、Rw3＝200K、Rw4＝20K、Rw5＝0K，所述电容Cw＝13.2nF，所述电容Cw1＝10nF、Cw2＝3.3nF、Cw3悬空、Cw4悬空。
4、基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路，其特征在于：
(1)Chen阶混沌系统i为：
Figure PCTCN2014001021-appb-000001
(2)0.2阶Chen混沌系统ii为：
Figure PCTCN2014001021-appb-000002
(3)根据0.2阶Chen混沌系统ii构造模拟电路，利用运算放大器U1、运算放大器U2及电阻和0.2阶积分电路模块U5、0.2阶积分电路模块U6、0.2阶积分电路模块U7构成反相加法器和反相0.2阶积分器，利用乘法器U3和乘法器U4实现乘法运算，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3和乘法器U4采用AD633JN；
所述运算放大器U1连接运算放大器U2、乘法器U3、乘法器U4和0.2阶积分电路模块U5、0.2阶积分电路模块U6，所述运算放大器U2连接乘法器U3、乘法器U4和0.2阶积分电路模块U7，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2；
所述运算放大器U1的第1引脚通过电阻R9与U1的第6引脚相接，第2引脚通过电阻R6与U1的第1引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚接0.2阶积分电路模块U6的P引脚，第7引脚接输出y，接0.2阶积分电路 模块U6的P3引脚，接乘法器U4的第1引脚，通过电阻R5与第2引脚相接，通过电阻R1与第13引脚相接，第8引脚接输出x，通过电阻R8与第6引脚相接，通过电阻R4与第9引脚相接，接0.2阶积分电路模块U5的P3引脚，接乘法器U3的第1引脚，接乘法器U4的第3引脚，第9引脚接0.2阶积分电路模块U5的P引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
所述运算放大器U2的第1、2、6、7引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第8引脚输出z，接0.2阶积分电路模块U7的P3引脚，接乘法器U3的第3引脚，通过电阻R12与第9引脚相接，第9引脚接0.2阶积分电路模块U7的P引脚，第13引脚通过电阻R11与第14引脚相接，第14引脚接通过电阻R13与第9引脚相接；
所述乘法器U3的第1引脚接运算放大器U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R7接U1第6引脚，第8引脚接VCC；
所述乘法器U4的第1引脚接运算放大器U1的第7脚，第3引脚接运算放大器U1的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接运算放大器U2第13引脚，第8引脚接VCC；
所述0.2阶积分电路模块U5的PI1、PI2、PO1、PO2、P1、P2、P3引脚悬空，P引脚接运算放大器U1的第9引脚，P4引脚接接运算放大器U1的第8引脚；
所述0.2阶积分电路模块U6的P11、PI2、PO1、PO2、P1、P2、P3引脚悬空，P引脚接运算放大器U1的第6引脚，P4引脚接接运算放大器U1的第7引脚；
所述0.2阶积分电路模块U7的PI1、PI2、PO1、PO2、P1、P2、P3引脚悬空，P引脚接运算放大器U2的第9引脚，P4引脚接接运算放大器U2的第8引脚。
本发明的有益效果是：采用链式结构，设计制作了PCB电路，电路由四部分组成，每部分又由四个电阻和一个电位器串联后，与四个电容并联组成的通用分数阶积分模块电路，0.2阶分数阶积分电路正好由四部分组成，采用这种方法的实现0.2阶分数阶混沌系统电路，可靠性高，不易出错。
附图说明
图1为本发明的链式分数阶积分电路模块内部结构示意图(a)、内部实际连接图(b)和0.2阶积分电路实际连接图(c)。
图2为本发明优选实施例的电路连接结构示意图。
图3和图4为本发明的电路实际连接图。
具体实施方式
下面结合附图和优选实施例对本发明作更进一步的详细描述，参见图1-图4。
1、一种链式分数阶积分电路模块，其特征是在于：电阻Rx与电容Cx并联，形成第一部分，电阻Ry与电容Cy并联，形成第二部分，电阻Rz与电容Cz并联，形成第三部分，电阻Rw与电容Cw并联，形成第四部分，级联输入引脚PI1、PI2和输出引脚P接第一部分，第一部分接输出引脚P1和第二部分，第二部分接输出引脚P2和第三部分，第三部分接输出引脚P3和第四部分，第四部分接输出引脚P4和级联输出引脚PO1、PO2。
2、根据权利要求1所述一种链式分数阶积分电路模块，其特征在于：所述电阻Rx由电位器Rx1和电阻Rx2、Rx3、Rx4、Rx5串联组成，所述电容Cx由电容Cx1、Cx2、Cx3、Cx4并联组成；所述电阻Ry由电位器Ry1和电阻Ry2、Ry3、Ry4、Ry5串联组成，所述电容Cy由电容Cy1、Cy2、Cy3、Cy4，并联组成；所述电阻Rz由电位器Rz1和电阻Rz2、Rz3、Rz4、Rz5串联组成，所述电容Cz由电容Cz1、Cz2、Cz3、Cz4并联组成；所述电阻Rw由电位器Rw1和电阻Rw2、Rw3、Rw4、Rw5串联组成，所述电容Cw由电容Cw1、Cw2、Cw3、Cw4并联组成。
3、根据权利要求1所述一种链式分数阶积分电路模块，所述0.2阶积分电路模块，其特征在于：所述级联输入引脚PI1、PI2悬空，所述输出引脚P1、P2、P3悬空，所述级联输出引脚PO1、PO2悬空，所述电阻Rx＝1.13M，所述电位器Rx1＝1M，所述电阻Rx2＝100K、Rx3＝20K、Rx4＝10K、Rx5＝0K，所述电容Cx＝27.99uF，所述电容Cx1＝10uF、Cx2＝10uF、Cx3＝4.7uF、Cx4＝3.2.7uF；所述电阻Ry＝0.607M，所述电位器Ry1＝5.1K，所述电阻Ry2＝500K、Ry3＝100K、Ry4＝2K、Ry5＝0K，所述电容Cy＝2.93uF，所述电容Cy1＝2.2uF、Cy2＝220nF、Cy3＝470nF、Cy4＝47nF；所述电阻Rz＝0.35M，所述电位器Rz1＝51K和所述电阻Rz2＝200K、Rz3＝100K、Rz4＝0K、Rz5＝0K，所述电容Cz＝0.285uF，所述电容Cz1＝220nF、Cz2＝47nF、Cz＝10nF、Cz4＝10nF；所述电阻Rw＝0.425M，所述电位器Rw1＝5.1K，所述电阻Rw2＝200K、Rw3＝200K、Rw4＝20K、Rw5＝0K，所述电容Cw＝13.2nF，所述电容Cw1＝10nF、Cw2＝3.3nF、Cw3悬空、Cw4悬空。
4、基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路，其特征在于：
(1)Chen阶混沌系统i为：
Figure PCTCN2014001021-appb-000003
(2)0.2阶Chen混沌系统ii为：
Figure PCTCN2014001021-appb-000004
(3)根据0.2阶Chen混沌系统ii构造模拟电路，利用运算放大器U1、运算放大器U2及电阻和0.2阶积分电路模块U5、0.2阶积分电路模块U6、0.2阶积分电路模块U7构成反相加法器和反相0.2阶积分器，利用乘法器U3和乘法器U4实现乘法运算，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3和乘法器U4采用AD633JN；
所述运算放大器U1连接运算放大器U2、乘法器U3、乘法器U4和0.2阶积分电路模块U5、0.2阶积分电路模块U6，所述运算放大器U2连接乘法器U3、乘法器U4和0.2阶积分电路模块U7，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2；
所述运算放大器U1的第1引脚通过电阻R9与U1的第6引脚相接，第2引脚通过电阻R6与U1的第1引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚接0.2阶积分电路模块U6的P引脚，第7引脚接输出y，接0.2阶积分电路模块U6的P3引脚，接乘法器U4的第1引脚，通过电阻R5与第2引脚相接，通过电阻R1与第13引脚相接，第8引脚接输出x，通过电阻R8与第6引脚相接，通过电阻R4与第9引脚相接，接0.2阶积分电路模块U5的P3引脚，接乘法器U3的第1引脚，接乘法器U4的第3引脚，第9引脚接0.2阶积分电路模块U5的P引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
所述运算放大器U2的第1、2、6、7引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第8引脚输出z，接0.2阶积分电路模块U7的P3引脚，接乘法器U3的第3引脚，通过电阻R12与第9引脚相接，第9引脚接0.2阶积分电路模块U7的P引脚，第13引脚通过电阻R11与第14引脚相接，第14引脚接通过电阻R13与第9引脚相接：
所述乘法器U3的第1引脚接运算放大器U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R7接U1第6引脚，第8引脚接VCC；
所述乘法器U4的第1引脚接运算放大器U1的第7脚，第3引脚接运算放大器U1的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接运算放大器U2第13引脚，第8引脚接VCC；
所述0.2阶积分电路模块U5的PI1、PI2、PO1、PO2、P1、P2、P3引脚悬空，P引脚接运算放大器U1的第9引脚，P4引脚接接运算放大器U1的第8引脚；
所述0.2阶积分电路模块U6的PI1、PI2、PO1、PO2、P1、P2、P3引脚悬空，P引脚接运算放大器U1的第6引脚，P4引脚接接运算放大器U1的第7引脚；
所述0.2阶积分电路模块U7的PI1、PI2、PO1、PO2、P1、P2、P3引脚悬空，P引脚接运算放大器U2的第9引脚，P4引脚接接运算放大器U2的第8引脚。
电路中电阻R2＝R3＝R6＝R9＝R11＝R13＝10kΩ，R1＝R4＝2.86kΩ，R5＝3.57kΩ，R7＝R10＝1kΩ，R8＝14.286kΩ，R12＝33.33kΩ。
当然，上述说明并非对本发明的限制，本发明也不仅限于上述举例，本技术领域的普通技术人员在本发明的实质范围内所做出的变化、改型、添加或替换，也属于本发明的保护范围。

Claims (4)

  1. 一种链式分数阶积分电路模块，其特征是在于：电阻Rx与电容Cx并联，形成第一部分，电阻Ry与电容Cy并联，形成第二部分，电阻Rz与电容Cz并联，形成第三部分，电阻Rw与电容Cw并联，形成第四部分，级联输入引脚PI1、PI2和输出引脚P接第一部分，第一部分接输出引脚P1和第二部分，第二部分接输出引脚P2和第三部分，第三部分接输出引脚P3和第四部分，第四部分接输出引脚P4和级联输出引脚P01、P02。
  2. 根据权利要求1所述一种链式分数阶积分电路模块，其特征在于：所述电阻Rx由电位器Rx1和电阻Rx2、Rx3、Rx4、Rx5串联组成，所述电容Cx由电容Cx1、Cx2、Cx3、Cx4并联组成；所述电阻Ry由电位器Ry1和电阻Ry2、Ry3、Ry4、Ry5串联组成，所述电容Cy由电容Cy1、Cy2、Cy3、Cy4，并联组成；所述电阻Rz由电位器Rz1和电阻Rz2、Rz3、Rz4、Rz5串联组成，所述电容Cz由电容Cz1、Cz2、Cz3、Cz4并联组成；所述电阻Rw由电位器Rw1和电阻Rw2、Rw3、Rw4、Rw5串联组成，所述电容Cw由电容Cw1、Cw2、Cw3、Cw4并联组成。
  3. 根据权利要求1所述一种链式分数阶积分电路模块，所述0.2阶积分电路模块，其特征在于：所述级联输入引脚PI1、PI2悬空，所述输出引脚P1、P2、P3悬空，所述级联输出引脚P01、P02悬空，所述电阻Rx＝1.13M，所述电位器Rx1＝1M，所述电阻Rx2＝100K、Rx3＝20K、Rx4＝10K、Rx5＝0K，所述电容Cx＝27.99uF，所述电容Cx1＝10uF、Cx2＝10uF、Cx3＝4.7uF、Cx4＝3.2.7uF；所述电阻Ry＝0.607M，所述电位器Ry1＝5.1K，所述电阻Ry2＝500K、Ry3＝100K、Ry4＝2K、Ry5＝0K，所述电容Cy＝2.93uF，所述电容Cy1＝2.2uF、Cy2＝220nF、Cy3＝470nF、Cy4＝47nF；所述电阻Rz＝0.35M，所述电位器Rz1＝51K和所述电阻Rz2＝200K、Rz3＝100K、Rz4＝0K、Rz5＝0K，所述电容Cz＝0.285uF，所述电容Cz1＝220nF、Cz2＝47nF、Cz＝10nF、Cz4＝10nF；所述电阻Rw＝0.425M，所述电位器Rw1＝5.1K，所述电阻Rw2＝200K、Rw3＝200K、Rw4＝20K、Rw5＝0K，所述电容Cw＝13.2nF，所述电容Cw1＝10nF、Cw2＝3.3nF、Cw3悬空、Cw4悬空。
  4. 基于链式分数阶积分电路模块的0.2阶Chen混沌系统电路，其特征在于：
    (1)Chen阶混沌系统i为：
    Figure PCTCN2014001021-appb-100001
         i   a＝35，b＝3，c＝28
    (2)0.2阶Chen混沌系统ii为：
    Figure PCTCN2014001021-appb-100002
        ii   α＝35，b＝3，c＝28，α＝0.2
    (3)根据0.2阶Chen混沌系统ii构造模拟电路，利用运算放大器U1、运算放大器U2及电阻和0.2阶积分电路模块U5、0.2阶积分电路模块U6、0.2阶积分电路模块U7构成反相加法器和反相0.2阶积分器，利用乘法器U3和乘法器U4实现乘法运算，所述运算放大器U1和运算放大器U2采用LF347N，所述乘法器U3和乘法器U4采用AD633JN；
    所述运算放大器U1连接运算放大器U2、乘法器U3、乘法器U4和0.2阶积分电路模块U5、0.2阶积分电路模块U6，所述运算放大器U2连接乘法器U3、乘法器U4和0.2阶积分电路模块U7，所述乘法器U3连接运算放大器U1，所述乘法器U4连接运算放大器U2；
    所述运算放大器U1的第1引脚通过电阻R9与U1的第6引脚相接，第2引脚通过电阻R6与U1的第1引脚相接，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第6引脚接0.2阶积分电路模块U6的P引脚，第7引脚接输出y，接0.2阶积分电路模块U6的P3引脚，接乘法器U4的第1引脚，通过电阻R5与第2引脚相接，通过电阻R1与第13引脚相接，第8引脚接输出x，通过电阻R8与第6引脚相接，通过电阻R4与第9引脚相接，接0.2阶积分电路模块U5的P3引脚，接乘法器U3的第1引脚，接乘法器U4的第3引脚，第9引脚接0.2阶积分电路模块U5的P引脚，第13引脚通过电阻R2与第14引脚相接，第14引脚通过电阻R3与第9引脚相接；
    所述运算放大器U2的第1、2、6、7引脚悬空，第3、5、10、12引脚接地，第4引脚接VCC，第11引脚接VEE，第8引脚输出z，接0.2阶积分电路模块U7的P3引脚，接乘法器U3的第3引脚，通过电阻R12与第9引脚相接，第9引脚接0.2阶积分电路模块U7的P引脚，第13引脚通过电阻R11与第14引脚相接，第14引脚接通过电阻R13与第9引脚相接；
    所述乘法器U3的第1引脚接运算放大器U1的第8脚，第3引脚接U2的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R7接U1第6引脚，第8引脚接VCC；
    所述乘法器U4的第1引脚接运算放大器U1的第7脚，第3引脚接运算放大器U1的第8引脚，第2、4、6引脚均接地，第5引脚接VEE，第7引脚通过电阻R10接运算放大器U2 第13引脚，第8引脚接VCC；
    所述0.2阶积分电路模块U5的PI1、PI2、P01、P02、P1、P2、P3引脚悬空，P引脚接运算放大器U1的第9引脚，P4引脚接接运算放大器U1的第8引脚；
    所述0.2阶积分电路模块U6的PI1、PI2、P01、P02、P1、P2、P3引脚悬空，P引脚接运算放大器U1的第6引脚，P4引脚接接运算放大器U1的第7引脚；
    所述0.2阶积分电路模块U7的PI1、PI2、P01、P02、P1、P2、P3引脚悬空，P引脚接运算放大器U2的第9引脚，P4引脚接接运算放大器U2的第8引脚。
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