WO2014208201A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2014208201A1 WO2014208201A1 PCT/JP2014/062129 JP2014062129W WO2014208201A1 WO 2014208201 A1 WO2014208201 A1 WO 2014208201A1 JP 2014062129 W JP2014062129 W JP 2014062129W WO 2014208201 A1 WO2014208201 A1 WO 2014208201A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
Definitions
- the present invention relates to a semiconductor device including a semiconductor element having a vertical structure such as a diode, a field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET), or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor: IGBT).
- a semiconductor element having a vertical structure such as a diode, a field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET), or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor: IGBT).
- a depletion layer is formed in an active region that actively functions as a semiconductor element, and electric field concentration occurs at the boundary of the depletion layer, so that the breakdown voltage of the semiconductor device decreases. Therefore, by providing a termination region having a conductivity type opposite to the conductivity type of the semiconductor layer on the outer peripheral side of the active region, the depletion layer is expanded by the pn junction between the semiconductor layer and the termination region, and the electric field concentration is reduced. The breakdown voltage of the semiconductor device can be increased.
- the present invention has been made in view of the above-described problems, and provides a semiconductor device including a termination region capable of effectively mitigating electric field concentration while suppressing resist collapse during manufacturing, and a method for manufacturing the same. Objective.
- a semiconductor device of the present invention includes a semiconductor element formed on a semiconductor substrate made of a wide band gap semiconductor of the first conductivity type, and a plurality of second conductivity type formed on the semiconductor substrate surrounding the semiconductor element in plan view.
- a ring-shaped region, and at least one of the plurality of ring-shaped regions includes one or more spaced regions that communicate the inside and the outside of the ring-shaped region in plan view.
- the method for manufacturing a semiconductor device of the present invention includes (a) a step of forming a semiconductor element on a semiconductor substrate made of a wide band gap semiconductor of a first conductivity type, and (b) a position of the semiconductor substrate surrounding the semiconductor element in plan view. And (b1) separating the plurality of ring-shaped resists on the semiconductor substrate surrounding the semiconductor element in plan view, and forming at least one ring-shaped region.
- the resist includes a step of forming a resist connected to a neighboring resist by a bridge having a predetermined width, and (b2) a step of ion-implanting the semiconductor substrate using the resist.
- a semiconductor device of the present invention includes a semiconductor element formed on a semiconductor substrate made of a wide band gap semiconductor of the first conductivity type, and a plurality of second conductivity type formed on the semiconductor substrate surrounding the semiconductor element in plan view.
- a ring-shaped region, and at least one of the plurality of ring-shaped regions includes one or more spaced regions that communicate the inside and the outside of the ring-shaped region in plan view. Therefore, it is possible to effectively alleviate the electric field concentration in the termination region while suppressing the resist collapse when forming the ring-shaped region.
- the method for manufacturing a semiconductor device of the present invention includes (a) a step of forming a semiconductor element on a semiconductor substrate made of a wide band gap semiconductor of a first conductivity type, and (b) a position of the semiconductor substrate surrounding the semiconductor element in plan view. And (b1) separating the plurality of ring-shaped resists on the semiconductor substrate surrounding the semiconductor element in plan view, and forming at least one ring-shaped region.
- the resist includes a step of forming a resist connected to a neighboring resist by a bridge having a predetermined width, and (b2) a step of ion-implanting the semiconductor substrate using the resist. Therefore, resist collapse is suppressed in steps (b1) and (b2), and a semiconductor device that can effectively alleviate electric field concentration in the termination region can be manufactured with high yield.
- FIG. 2A and 2B are a plan view and a cross-sectional view illustrating a configuration of a semiconductor device according to the first embodiment.
- 8A and 8B are a plan view and a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.
- It is a top view which shows the FLR structure of a comparative example.
- 3 is a plan view showing the FLR structure of the first embodiment.
- FIG. It is a figure which shows the electric potential distribution in the FLR structure of a comparative example and Embodiment 1.
- FIG. 6 is a plan view showing a FLR structure of a modification of the first embodiment.
- FIG. 6 is a plan view showing a FLR structure of a modification of the first embodiment.
- FIG. 6 is a plan view showing a FLR structure of a modification of the first embodiment.
- FIG. 6 is a plan view showing a FLR structure of a modification of the first embodiment.
- FIG. 6 is a plan view showing an FLR structure according to a second embodiment.
- FIG. 10 is a plan view showing a manufacturing process of the FLR structure of the second embodiment.
- 6 is a plan view showing an FLR structure according to a second embodiment.
- FIG. 6 is a plan view showing an FLR structure of a third embodiment.
- FIG. FIG. 10 is a plan view showing a manufacturing process of the FLR structure of the third embodiment.
- 6 is a plan view showing an FLR structure of a third embodiment.
- FIG. FIG. 10 is a plan view showing a manufacturing process of the FLR structure of the third embodiment. It is the top view and sectional drawing which show the structure of the semiconductor device of a base technology. It is the top view and sectional view which show the manufacturing process of the semiconductor device of a base technology.
- a Schottky diode which is a semiconductor device that is a prerequisite technology of the present invention.
- the first conductivity type semiconductor is described as an n-type semiconductor
- the second conductivity type semiconductor is described as a p-type semiconductor.
- the present invention is not limited to this, and the first conductivity type semiconductor is A p-type semiconductor may be used, and the second conductivity type semiconductor may be an n-type semiconductor.
- SiC silicon carbide
- inside refers to the active region side that is the central portion side of the semiconductor device
- outside refers to the termination region side that is the outer edge side of the semiconductor device.
- FIG. 16 is a configuration diagram of the Schottky diode 101 according to the front technology of the present invention.
- FIG. 16A is a plan view of the Schottky diode 101
- FIG. 16B is a cross-sectional view of the Schottky diode 101.
- an n-type semiconductor layer 1 is provided on a 4H—SiC semiconductor substrate (not shown), and a metal electrode 3 is provided on the surface of the semiconductor layer 1.
- the region of the semiconductor layer 1 located below the metal electrode 3 becomes an active region 110 that functions as an active element, and the outside of the semiconductor layer 1 surrounding the active region 110 is a termination region 121 for holding the breakdown voltage of the semiconductor device.
- An insulating surface protective film (not shown) is formed on the termination region 121.
- a plurality of spaced apart p-type FLRs 20 are formed in the termination region 121.
- FIG. 17 shows a resist 40 for forming the FLR 20.
- the FLR 20 is formed by implanting acceptor ions such as Al using the resist 40 as an implantation mask.
- acceptor ions such as Al
- the line width of the resist 40 needs to be very narrow.
- such a resist 40 having a narrow line width is likely to fall, and if ion implantation is performed in a state where the resist 40 is tilted, a desired Schottky diode 101 cannot be obtained, so that the device breakdown voltage may be significantly reduced. There is. Further, even if it is attempted to reduce the interval between the FLRs 20 in order to further increase the element breakdown voltage, it has been difficult to realize due to the problem of resist collapse.
- FIG. 1 shows a configuration around a termination region 120 provided on the outer side of the Schottky diode 100 which is a semiconductor device according to the first embodiment.
- FIG. 1 (a) is a plan view, and FIG. A sectional view is shown in FIG.
- the Schottky diode 100 includes a 4H—SiC semiconductor substrate, an n-type semiconductor layer 1, a metal electrode 3, and a p-type FLR 2 (not shown).
- a semiconductor layer 1 is formed on a semiconductor substrate, and a metal electrode 3 is provided on the surface of the semiconductor layer 1.
- the semiconductor layer 1 is divided into an active region 110 below the metal electrode 3 that functions as an active element, and a termination region 120 surrounding the active region 110.
- An insulating surface protective film (not shown) is formed on the semiconductor layer 1 in the termination region 120.
- a plurality of spaced apart p-type FLRs 2 are formed on the surface layer of the semiconductor layer 1 in the termination region 120. Since the arrangement interval of the FLRs increases toward the outside of the Schottky diode 100, the electric field concentration in the termination region 120 is effectively mitigated and the breakdown voltage is improved.
- the FLR2 is formed in a ring shape surrounding the active region 110 in the termination region 120.
- the FLR 2 formed inside the termination region 120 is not a completely continuous ring shape, but includes one or more separation regions 5. Due to the separation region 5, the inner peripheral side and the outer peripheral side of the ring-shaped FLR 2 communicate with each other in plan view.
- the separation width of the separation region 5 is narrow on the inner peripheral side of the FLR 2 and wider on the outer peripheral side.
- the separation regions 5 do not have to be formed in all the FLRs 2, but are formed in the FLRs 2 arranged at a narrow interval inside the termination region 120.
- FIG. 2 shows a resist 4 for forming the FLR 2 of the Schottky diode 100 shown in FIG.
- FIG. 2A is a plan view of a state in which a resist 4 is formed on the semiconductor layer 1
- FIG. 2B is a cross-sectional view thereof.
- the FLR 2 is formed by implanting acceptor-type ions such as Al using the resist 4 as an implantation mask.
- the resist 4 includes a portion that covers the active region 110 of the semiconductor layer 1, a portion that covers the outside of the termination region 120, and a portion that is formed on the termination region 120 to form the FLR 2.
- the resist 4 formed on the termination region 120 has a bridge 6 corresponding to the separation region 5 of the FLR 2 to be formed, and adjacent ring-shaped resists 4 are joined by the bridge 6.
- the bridge 6 is formed so that its width is narrow on the inside and wide on the outside.
- resist collapse is suppressed.
- FIG. 3 shows the separation region 50 of the FLR 21 made of the resist of the comparative example
- FIG. 5A shows the potential distribution simulation result.
- the width of the separation region 50 is 4 ⁇ m. From FIG. 5A, it can be seen that in the FLR 2 having the separation region 50 having a uniform width, the electric field rapidly increases at the electric field concentration points 7 and 8 shown in FIG.
- the separation region 5 of the FLR 2 formed by the resist 4 of the first embodiment becomes larger from the inner peripheral side to the outer peripheral side of the FLR 2 as shown in FIG.
- FIG. 5B shows a potential distribution simulation result of FLR2.
- the width of the separation region 5 is 1 ⁇ m on the inner peripheral side of the smallest FLR 2 and 4 ⁇ m on the outer peripheral side of the widest FLR 2.
- FIG. 5B shows that the electric field concentration at the electric field concentration points 7 and 8 is reduced in the FLR 2 of the first embodiment as compared with the comparative example.
- the bridge 6 of the resist 4 of Embodiment 1 is narrowed on the inside and widened on the outside, in other words, the separation region 5 of the FLR2 is narrowed on the inner peripheral side of the FLR2 and wide on the outer peripheral side.
- the electric field concentration at the electric field concentration points 7 and 8 it is possible to suppress the electric field concentration at the electric field concentration points 7 and 8 to achieve a high breakdown voltage and to suppress resist collapse.
- the adjacent FLRs 2 are formed by shifting the separation region 5, thereby preventing excessive electric field concentration and obtaining a high breakdown voltage semiconductor device.
- the separation region 5 may be provided inside the termination region 120 where the spacing between the FLRs 2 is narrow, and the separation region 5 may be omitted outside the termination region 120 where the spacing between the FLRs 2 is wide.
- FIG. 4 shows a shape in which the width of the separation region 5 increases at a constant rate from the inner periphery side to the outer periphery side of the FLR 2 as an example of the separation region 5 that is formed narrower on the inner periphery side of the FLR 2 and wider on the outer periphery side.
- the separation region 5 may have a shape in which the width increases at a constant rate toward the outer peripheral side after maintaining a constant width on the inner peripheral side of the FLR 2. According to such a shape, compared with the separation region 5 shown in FIG. 4, the same width can be obtained on the outer peripheral side of the FLR 2, and the width can be made smaller near the inner peripheral side of the FLR 2.
- a plurality of regions where the width of the separation region 5 is constant may be provided, and the width of the separation region 5 may be increased stepwise from the inner periphery side to the outer periphery side of the FLR 2.
- the same width can be obtained on the outer peripheral side of the FLR 2, and the width can be made smaller near the inner peripheral side of the FLR 2.
- resist collapse is prevented, a rapid potential gradient in the vicinity of the inner peripheral side of FLR 2 where the width of the separation region 5 is the narrowest is suppressed, electric field concentration at the electric field concentration point 7 is further suppressed, and a high breakdown voltage semiconductor device is obtained.
- the lengths of the regions where the width of the separation region 5 is constant are the same, and the step-like change amount is shown to be equal in each step. These can be changed as appropriate.
- the bridge 6 may be curved to form the FLR 2 so that the increase amount of the width of the separation region 5 continuously increases from the inner peripheral side to the outer peripheral side of the FLR 2.
- the same width can be obtained on the outer peripheral side of the FLR 2, and the width can be made smaller near the inner peripheral side of the FLR 2. Therefore, resist collapse can be prevented, and an abrupt potential gradient in the vicinity of the FLR 2 inner peripheral side of the separation region 5 can be suppressed, so that electric field concentration at the electric field concentration point 7 can be further suppressed.
- the angle of the outer peripheral side end portion of the FLR 2 in the separation region 5 is increased, the curvature of the equipotential line at the electric field concentration point 8 is smaller than that in the cases of FIGS. Can be further suppressed.
- the semiconductor device according to the first embodiment is formed in the semiconductor layer 1 by surrounding the semiconductor element in a plan view and a semiconductor element formed on the first conductivity type semiconductor layer 1 (a semiconductor substrate made of a wide band gap semiconductor). And a plurality of second conductivity type FLRs 2 (ring-shaped regions), and at least one of the plurality of FLRs 2 includes one or more spaced regions 5 that communicate the inside and the outside of the FLR 2 in plan view. . Since the resist 4 forming the FLR 2 is coupled by a bridge corresponding to the separation region 5, even when the line width of the resist 4 becomes narrow, resist collapse during manufacturing can be suppressed. Therefore, it is possible to narrow the arrangement interval of FLR 2 inside the termination region 120, and the electric field concentration in the termination region can be effectively reduced.
- the positions of the separation regions 5 in the extending direction of the FLR 2 do not overlap with each other. Thereby, excessive electric field concentration can be prevented and a high breakdown voltage semiconductor device can be obtained.
- the electric field concentration at the electric field concentration points 7 and 8 can be reduced by increasing the width of the separation region 5 from the inner peripheral side to the outer peripheral side of the FLR 2.
- the separation region 5 may have a region having a constant width on the inner peripheral side of the FLR 2. Then, the width of the separation region 5 on the inner peripheral side of the FLR 2 can be reduced, so that resist collapse is prevented and a steep potential gradient near the inner peripheral side of the FLR 2 where the width of the separation region 5 is the narrowest. It is possible to suppress the concentration of the electric field to the electric field concentration point 7 and to obtain a high breakdown voltage semiconductor device.
- the width of the separation region 5 may be increased stepwise from the inner periphery side to the outer periphery side of the FLR 2. Then, the width of the separation region 5 on the inner peripheral side of the FLR 2 can be reduced, so that resist collapse is prevented and a steep potential gradient near the inner peripheral side of the FLR 2 where the width of the separation region 5 is the narrowest. Thus, the electric field concentration at the electric field concentration point 7 is further suppressed, and a high breakdown voltage semiconductor device can be obtained.
- the amount of increase in the width of the separation region 5 may be continuously increased from the inner peripheral side to the outer peripheral side of the FLR 2.
- the width of the separation region 5 on the inner peripheral side of the FLR 2 can be reduced, so that resist collapse is prevented and a rapid potential gradient in the vicinity of the inner peripheral side of the separation region 5 in the FLR 2 is suppressed. It is possible to further suppress the electric field concentration on the.
- the angle of the FLR 2 outer peripheral side end of the separation region 5 is increased, the curvature of the equipotential line at the electric field concentration point 8 is reduced, and the electric field concentration at the electric field concentration point 8 can be further suppressed.
- resist collapse is unlikely to occur in regions having curvature such as the corners of the four corners of the semiconductor device, and mainly occurs in straight portions.
- the bridge 6 may be provided only in the straight portion of the resist 4 and the separation region 5 may be disposed only in the straight portion of the FLR 2.
- the impurity concentration in forming the FLR 2 has a great influence on the breakdown voltage of the termination region.
- the impurity concentration is low, the potential distribution becomes unstable due to disturbance factors such as fixed charges, and the breakdown voltage tends to decrease.
- the impurity concentration is high, the potential distribution is stable, but the electric field concentration is increased in the outer ring and the breakdown voltage is reduced.
- the separation region 5 is provided as in the present invention, even when the injection amount is large, the potential is shared by the inner ring, so that a semiconductor device that stably maintains a high breakdown voltage can be obtained.
- the manufacturing method of the semiconductor device of the first embodiment includes (a) a step of forming an active region 110 (semiconductor element) in a first conductivity type semiconductor layer 1 (a semiconductor substrate made of a wide band gap semiconductor), and (b).
- the resist 4 Since the resist 4 is connected by the bridge 6, resist collapse can be suppressed even when the line width of the resist 4 becomes narrow. Therefore, the arrangement interval of FLRs 2 can be narrowed inside the termination region 120, and electric field concentration in the termination region can be effectively reduced, and a high breakdown voltage semiconductor device can be manufactured.
- FIG. 9 shows the FLR 2A in the termination structure of the Schottky diode that is the semiconductor device of the second embodiment.
- the Schottky diode of the second embodiment is provided with a p-type block region 9 separated from other portions of the FLR 2A on the outer peripheral side of the FLR 2A in the separation region 5, and the FLR 2 of the first embodiment shown in FIG. It is the same.
- FIG. 10 shows a resist 4A for forming FLR 2A.
- An opening for forming the block region 9 is formed in the resist 4A. Therefore, the bridge 6A of the resist 4A is coupled to the inner resist 4A at one inner position and is coupled to the outer resist 4A at two outer positions. The adjacent resists 4A are joined by the bridge 6A, and resist collapse is suppressed.
- the electric field concentration at the electric field concentration points 7 and 8 is effectively suppressed as compared with the FLR 2 of the first embodiment shown in FIG. 4, and a high breakdown voltage semiconductor device is obtained. be able to.
- FIG. 11 shows an FLR 2A in which a modification of the first embodiment shown in FIG. 6 is applied to the second embodiment.
- FLR 2A in FIG. 11 compared to FLR 2A shown in FIG. 10, separation region 5 can have the same width on the outer peripheral side of FLR 2A and can be made smaller in the vicinity of the inner peripheral side of FLR 2A. Therefore, in addition to the effect of FLR 2A shown in FIG. 10, a rapid potential gradient near the inner peripheral side of FLR 2 where the width of the separation region 5 is the narrowest is suppressed, electric field concentration at the electric field concentration point 7 is suppressed, and high breakdown voltage Can be obtained.
- the semiconductor device of the second embodiment includes the second conductivity type block region 9 separated from the FLR 2A on the outer peripheral side of the FLR 2A (ring-shaped region) in the separation region 5. Since the resist 4A forming the FLR 2A is coupled by the bridge 6A corresponding to the separation region 5, even when the A line width of the resist 4 becomes narrow, the resist collapse during manufacturing can be suppressed. Therefore, the arrangement interval of FLR 2A can be narrowed inside the termination region 120, and the electric field concentration in the termination region 120 can be effectively reduced. In addition, since the potential is held by the block region 9, electric field concentration at the electric field concentration points 7 and 8 can be effectively suppressed, and a semiconductor device with high breakdown voltage can be obtained.
- FIG. 12 shows the FLR 2B in the termination structure of the Schottky diode which is the semiconductor device of the third embodiment.
- the Schottky diode of the third embodiment includes two p-type block regions 9B separated from other portions of the FLR 2B on the inner and outer peripheral sides of the FLR 2B in the separation region 5.
- FIG. 13 shows a resist 4B for forming FLR 2B.
- An opening for forming the block region 9B is formed in the resist 4B.
- the bridge 6B of the resist 4B intersects, and is coupled to the inner resist 4B at two inner locations and is coupled to the outer resist 4B at two outer locations.
- the adjacent resists 4B are joined by the bridge 6B, and resist collapse is suppressed.
- the electric field concentration at the electric field concentration points 7 and 8 is effectively suppressed as compared with the FLR 2 of the first embodiment shown in FIG. 4, and a high breakdown voltage semiconductor device is obtained. be able to.
- three or more p-type block regions 9B separated from other portions of FLR 2B may be provided.
- the semiconductor device shown in FIG. 14 includes three p-type block regions 9B separated from other portions of the FLR 2B from the inner periphery side to the outer periphery side of the FLR 2B in the separation region 5.
- FIG. 15 shows a resist 4B for forming FLR 2B.
- An opening for forming the block region 9B is formed in the resist 4B.
- the bridge 6B of the resist 4B intersects at a plurality of locations, and is coupled to the inner resist 4B at two inner locations and is coupled to the outer resist 4B at two outer locations.
- the adjacent resists 4B are joined by the bridge 6B, and resist collapse is suppressed.
- the semiconductor device of the second embodiment includes a plurality of second conductivity type block regions 9B separated from the FLR 2B in the FLR 2B (ring-shaped region) in the separation region 5. Since the resist 4B forming the FLR 2B is coupled by the bridge 6B corresponding to the separation region 5, even when the line width of the resist 4A becomes narrow, resist collapse during manufacturing can be suppressed. Therefore, the FLR 2B arrangement interval can be narrowed inside the termination region 120, and the electric field concentration in the termination region 120 can be effectively reduced. Further, since the potential is held by the block region 9B, the electric field concentration at the electric field concentration points 7 and 8 can be effectively suppressed, and a high breakdown voltage semiconductor device can be obtained.
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Abstract
Description
まず、本発明の前提技術となる半導体装置であるショットキーダイオードの構成を説明する。以下の説明では、第1導電型の半導体をn型の半導体とし、第2導電型の半導体をp型の半導体として説明するが、これに限定されるものではなく、第1導電型の半導体をp型の半導体とし、第2導電型の半導体をn型の半導体としてもよい。また、以下において、半導体装置である炭化珪素(SiC)からなる縦型構造のショットキーダイオードに本発明を適用する場合について説明するが、他の半導体材料や、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)等の他の半導体装置に用いることもできる。さらに、以下の説明において、「内側」とは半導体装置の中央部側である活性領域側を指すものとし、「外側」とは半導体装置の外縁側である終端領域側を指すものとする。
<B-1.構成>
図1は、実施の形態1に係る半導体装置であるショットキーダイオード100のうち、外側に設けられた終端領域120周辺の構成を示しており、図1(a)に平面図を、図1(b)に断面図を示している。
図2は、図1に示すショットキーダイオード100のFLR2を形成するためのレジスト4を示している。図2(a)は半導体層1上にレジスト4を形成した状態の平面図、図2(b)はその断面図である。FLR2は、レジスト4を注入マスクとしてAl等のアクセプタ型のイオンを注入することにより形成される。レジスト4は、半導体層1の活性領域110を覆う部分と、終端領域120よりも外側を覆う部分と、FLR2を形成するため終端領域120上に形成される部分からなる。終端領域120上に形成されるレジスト4は、形成すべきFLR2の離間領域5に対応して、ブリッジ6を有しており、ブリッジ6により隣り合うリング状のレジスト4が結合している。
図4には、FLR2の内周側で狭く外周側で広く形成される離間領域5の一例として、FLR2の内周側から外周側にかけて離間領域5の幅が一定割合で増加する形状を示した。しかし、図6に示すように、離間領域5は、FLR2の内周側で一定幅を保った後、外周側にかけて幅が一定割合で増加する形状としても良い。このような形状によれば、図4に示す離間領域5と比べて、FLR2の外周側では同じ幅の大きさで、FLR2の内周側付近ではより幅を小さくすることができる。そのため、レジスト倒れを防ぐと共に、離間領域5の幅が最も狭くなるFLR2の内周側付近の急激な電位勾配を抑え、電界集中ポイント7への電界集中を抑制し、高耐圧な半導体装置を得ることができる。
実施の形態1の半導体装置は、第1導電型の半導体層1(ワイドバンドギャップ半導体からなる半導体基板)に形成される半導体素子と、半導体素子を平面視で取り囲んで半導体層1に形成される、第2導電型の複数のFLR2(リング状領域)とを備え、複数のFLR2のうち少なくとも1つは、当該FLR2の内側と外側とを平面視において連通させる1つ以上の離間領域5を備える。FLR2を形成するレジスト4は離間領域5に対応したブリッジによって結合されるため、レジスト4の線幅が細くなる場合でも製造時のレジスト倒れが抑制できる。そのため、終端領域120の内側ではFLR2の配置間隔を狭くすることが可能で、終端領域における電界集中を効果的に緩和することができる。
<C-1.構成>
図9は、実施の形態2の半導体装置であるショットキーダイオードの終端構造におけるFLR2Aを示している。実施の形態2のショットキーダイオードは、離間領域5内のFLR2Aの外周側に、FLR2Aの他の部分から分離したp型のブロック領域9を備える他は、図4に示す実施の形態1のFLR2と同様である。
実施の形態2の半導体装置は、離間領域5内のFLR2A(リング状領域)の外周側に、FLR2Aと分離した第2導電型のブロック領域9を備える。FLR2Aを形成するレジスト4Aは離間領域5に対応したブリッジ6Aによって結合されるため、レジスト4のA線幅が細くなる場合でも製造時のレジスト倒れが抑制できる。そのため、終端領域120の内側ではFLR2Aの配置間隔を狭くすることが可能で、終端領域120における電界集中を効果的に緩和することができる。また、ブロック領域9により電位が保持されるため、電界集中ポイント7、8での電界集中を効果的に抑制し、高耐圧な半導体装置を得ることができる。
<D-1.構成>
図12は、実施の形態3の半導体装置であるショットキーダイオードの終端構造におけるFLR2Bを示している。実施の形態3のショットキーダイオードは、離間領域5内のFLR2Bの内周側と外周側に、FLR2Bの他の部分から分離したp型のブロック領域9Bを、離間して2つ備えている。
実施の形態2の半導体装置は、離間領域5内のFLR2B(リング状領域)内に、FLR2Bと分離した第2導電型のブロック領域9Bを複数備える。FLR2Bを形成するレジスト4Bは離間領域5に対応したブリッジ6Bによって結合されるため、レジスト4Aの線幅が細くなる場合でも製造時のレジスト倒れが抑制できる。そのため、終端領域120の内側ではFLR2Bの配置間隔を狭くすることが可能で、終端領域120における電界集中を効果的に緩和することができる。また、ブロック領域9Bにより電位が保持されるため、電界集中ポイント7、8での電界集中を効果的に抑制し、高耐圧な半導体装置を得ることができる。
Claims (10)
- 第1導電型のワイドバンドギャップ半導体からなる半導体基板(1)に形成される半導体素子と、
前記半導体素子を平面視で取り囲んで前記半導体基板(1)に形成される、第2導電型の複数のリング状領域(2)とを備え、
前記複数のリング状領域(2)のうち少なくとも1つは、当該リング状領域(2)の内側と外側とを平面視において連通させる1つ以上の離間領域(5)を備える、
半導体装置。 - 隣同士の前記リング状領域(2)の夫々に前記離間領域(5)が形成される場合、前記リング状領域(2)の延伸方向における前記離間領域(5)の位置は両者で重ならない、
請求項1に記載の半導体装置。 - 前記離間領域(5)の幅は前記リング状領域(2)の内周側から外周側にかけて大きくなる、
請求項1又は2に記載の半導体装置。 - 前記離間領域(5)は前記リング状領域(2)の内周側で一定幅の領域を有する、
請求項3に記載の半導体装置。 - 前記離間領域(5)の幅は前記リング状領域(2)の内周側から外周側にかけて階段状に大きくなる、
請求項3に記載の半導体装置。 - 前記離間領域(5)の幅の増加量が、前記リング状領域(2)の内周側から外周側にかけて連続的に大きくなる、
請求項3に記載の半導体装置。 - 前記離間領域(5)内の前記リング状領域(2)の外周側に、前記リング状領域(2)と分離した第2導電型のブロック領域(9)を備える、
請求項3~6のいずれかに記載の半導体装置。 - 前記離間領域(5)内の前記リング状領域(2B)内に、前記リング状領域(2B)と分離した第2導電型の1つ以上のブロック領域(9B)を備える、
請求項1~7のいずれかに記載の半導体装置。 - 前記半導体基板は炭化珪素半導体基板である、
請求項1~8のいずれかに記載の半導体装置。 - (a)第1導電型のワイドバンドギャップ半導体からなる半導体基板(1)に半導体素子を形成する工程と、
(b)前記半導体基板(1)の、前記半導体素子を平面視で取り囲む位置に、複数のリング状領域(2)を形成する工程とを備え、
前記工程(b)は、
(b1)前記半導体素子を平面視で取り囲む前記半導体基板(1)上に、リング状の複数のレジスト(4,4A,4B)を離間し、かつ少なくとも1つの前記レジスト(4,4A,4B)は隣の前記レジスト(4,4A,4B)と所定幅のブリッジ(6,6A,6B)で連結して形成する工程と、
(b2)前記レジスト(4,4A,4B)をマスクとして用いて前記半導体基板(1)にイオン注入する工程とを備える、
半導体装置の製造方法。
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JPWO2021009828A1 (ja) * | 2019-07-16 | 2021-11-25 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
CN114072927A (zh) * | 2019-07-16 | 2022-02-18 | 三菱电机株式会社 | 半导体装置、电力变换装置以及半导体装置的制造方法 |
JP7254180B2 (ja) | 2019-07-16 | 2023-04-07 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
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JP6224100B2 (ja) | 2017-11-01 |
DE112014002993T5 (de) | 2016-03-03 |
CN105393363A (zh) | 2016-03-09 |
CN105393363B (zh) | 2018-01-02 |
US20160087031A1 (en) | 2016-03-24 |
JPWO2014208201A1 (ja) | 2017-02-23 |
US9704947B2 (en) | 2017-07-11 |
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