JP5676002B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5676002B2 JP5676002B2 JP2013536028A JP2013536028A JP5676002B2 JP 5676002 B2 JP5676002 B2 JP 5676002B2 JP 2013536028 A JP2013536028 A JP 2013536028A JP 2013536028 A JP2013536028 A JP 2013536028A JP 5676002 B2 JP5676002 B2 JP 5676002B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- impurity
- buried
- guard ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 143
- 239000010410 layer Substances 0.000 claims description 175
- 239000012535 impurity Substances 0.000 claims description 96
- 238000002347 injection Methods 0.000 claims description 61
- 239000007924 injection Substances 0.000 claims description 61
- 239000002344 surface layer Substances 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000002513 implantation Methods 0.000 description 90
- 230000005684 electric field Effects 0.000 description 44
- 239000000758 substrate Substances 0.000 description 39
- 230000015556 catabolic process Effects 0.000 description 20
- 230000000694 effects Effects 0.000 description 19
- 230000004048 modification Effects 0.000 description 13
- 238000012986 modification Methods 0.000 description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 12
- 229910010271 silicon carbide Inorganic materials 0.000 description 12
- 230000008859 change Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 238000002161 passivation Methods 0.000 description 8
- 238000000137 annealing Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
また、本発明の別の態様にかかる半導体装置は、第1導電型の半導体層表層に形成され、半導体素子を構成する第2導電型の活性領域と、前記半導体層表層に、各々が前記活性領域を平面視上囲むように互いに離間して埋め込まれて形成された、第2導電型の複数の第1不純物領域と、前記半導体層表層に埋め込まれ、複数の前記第1不純物領域の底部のうちの少なくとも2つを接続する、第2導電型の第2不純物領域とを備えることを特徴とする。
また、本発明の別の態様にかかる半導体装置によれば、第1導電型の半導体層表層に形成され、半導体素子を構成する第2導電型の活性領域と、前記半導体層表層に、各々が前記活性領域を平面視上囲むように互いに離間して埋め込まれて形成された、第2導電型の複数の第1不純物領域と、前記半導体層表層に埋め込まれ、複数の前記第1不純物領域の底部のうちの少なくとも2つを接続する、第2導電型の第2不純物領域とを備えることにより、埋め込み注入層を位置精度高く形成することなく、高耐圧かつ高信頼性を有する半導体装置を提供することができる。
<構成>
図3は、本発明の実施の形態1による終端構造101の構造を示す断面図である。
図7は、実施の形態1の変形例1である終端構造103を示す断面図である。埋め込み注入層24により、ベース2と一部のガードリングであるガードリング11〜ガードリング13が接続されている。ガードリング構造17のうち、ガードリング14〜ガードリング16は、埋め込み注入層24に接続されていない。
図8は、実施の形態1の変形例2である終端構造104を示す断面図である。実施の形態1の終端構造101の埋め込み注入層18に加えて、半導体層表層に埋め込まれた埋め込みガードリング25〜埋め込みガードリング27を備える埋め込みガードリング構造28(第3不純物領域)を、ベース2を囲むガードリング構造17(第1不純物領域)の、平面視外側の領域に形成している。
本発明にかかる実施の形態によれば、半導体装置において、第1導電型の半導体層表層に形成され、半導体素子を構成する第2導電型の活性領域としてのベース2と、半導体層表層に、各々がベース2を平面視上囲むように互いに離間して形成された、第2導電型の複数の第1不純物領域としてのガードリング11〜ガードリング16と、半導体層表層に埋め込まれ、複数のガードリング11〜ガードリング16の底部のうちの少なくとも2つを接続する、第2導電型の第2不純物領域としての埋め込み注入層18とを備えることで、狭い間隔で形成されたガードリングを備える場合であっても、位置精度よく形成された注入層を用いることなく、ガードリング構造17の性能を活かすことにより高耐圧かつ高信頼性を有する半導体装置を提供することができる。
<構成>
図9は、本発明の実施の形態2による終端構造201を示す断面図である。埋め込み注入層30(第2不純物領域)はガードリング11〜ガードリング16の底部を接続しているが、実施の形態1における場合と異なり、活性領域としてのベース2には接続されていない。
本発明にかかる実施の形態によれば、半導体装置において、第2不純物領域としての埋め込み注入層30が、活性領域としてのベース2と接続されないことで、順方向電圧印加時のアノード電極4への電流集中を抑制することができる。
<構成>
図11は、本発明の実施の形態3による終端構造301を示す断面図である。ベース2の平面視外側に、ベース2よりも深く注入され埋め込まれた埋め込みガードリング40〜埋め込みガードリング46(第1不純物領域)から成る第1埋め込み注入層47が形成されている。埋め込みガードリング40〜埋め込みガードリング46は、互いに離間して、ベース2を平面視上囲んで形成されている。
実施の形態3においては、以下に示す変形例も可能である。
本発明にかかる実施の形態によれば、半導体装置において、第2不純物領域としての第2埋め込み注入層51が、活性領域としてのベース2と接続されることで、さらに、空乏層が最外周のガードリング46まで繋がりやすくなる。よって、高耐圧かつ高信頼性を実現することができる。
<構成>
図15は、本発明の実施の形態4による終端構造401を示す断面図である。図15に示すものは、ショットキーバリアダイオードの終端構造であるが、ショットキー電極59の端部の下に位置する注入層60を、PINダイオードのベースと捉えれば、実施の形態1〜3に示した構成と同様の構成を適用することができる。
実施の形態1〜4では、ガードリングの数を固定しているが、ガードリングの数は求める耐圧、個々のガードリング幅、個々のガードリング間隔によって変わる。一般的に、ガードリングの数は耐圧が上がるほど、多く必要である。これは、例えば図8に示した、埋め込み注入層と同時に形成する埋め込みガードリングでも同様である。
Claims (14)
- 第1導電型の半導体層表層に形成され、半導体素子を構成する第2導電型の活性領域と、
前記半導体層表層に、各々が前記活性領域を平面視上囲むように互いに離間して形成された、第2導電型の複数の第1不純物領域と、
前記半導体層表層に埋め込まれ、複数の前記第1不純物領域の底部のうちの少なくとも2つを接続する、第2導電型の第2不純物領域とを備えることを特徴とする、
半導体装置。 - 前記第2不純物領域が、前記活性領域と接続されることを特徴とする、
請求項1に記載の半導体装置。 - 前記第2不純物領域が、前記活性領域の底部に接続されることを特徴とする、
請求項1または2に記載の半導体装置。 - 前記第2不純物領域が、前記活性領域と接続されないことを特徴とする、
請求項1に記載の半導体装置。 - 前記第2不純物領域が、複数の前記第1不純物領域の底部の全てに接続されることを特徴とする、
請求項1または2に記載の半導体装置。 - 前記第2不純物領域が、前記活性領域を平面視上最も外側から囲む前記第1不純物領域のさらに平面視上外側まで形成されることを特徴とする、
請求項5に記載の半導体装置。 - 前記第2不純物領域が、前記第1不純物領域より不純物濃度の低いことを特徴とする、
請求項1または2に記載の半導体装置。 - 互いに離間して前記半導体層表層に埋め込まれ、各々が前記第1不純物領域を平面視上囲む、第2導電型の複数の第3不純物領域をさらに備えることを特徴とする、
請求項1または2に記載の半導体装置。 - 前記第3不純物領域が、前記第2不純物領域と同じ深さに埋め込まれることを特徴とする、
請求項8に記載の半導体装置。 - 前記第1不純物領域が、前記半導体層表面に形成されることを特徴とする、
請求項1または2に記載の半導体装置。 - 最も内側の前記第1不純物領域上に、絶縁膜を介して、前記活性領域に接続された配線層を備えることを特徴とする、
請求項10に記載の半導体装置。 - 第1導電型の半導体層表層に形成され、半導体素子を構成する第2導電型の活性領域と、
前記半導体層表層に、各々が前記活性領域を平面視上囲むように互いに離間して埋め込まれて形成された、第2導電型の複数の第1不純物領域と、
前記半導体層表層に埋め込まれ、複数の前記第1不純物領域の底部のうちの少なくとも2つを接続する、第2導電型の第2不純物領域とを備えることを特徴とする、
半導体装置。 - 前記第1不純物領域が、前記第2不純物領域と同じ深さに埋め込まれて形成されることを特徴とする、
請求項12に記載の半導体装置。 - 前記半導体素子がショットキーバリアダイオードであり、前記活性領域の端部がショットキー電極の端部に配置される第2導電型の注入層であることを特徴とする、
請求項1または2に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013536028A JP5676002B2 (ja) | 2011-09-28 | 2012-07-31 | 半導体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011211980 | 2011-09-28 | ||
JP2011211980 | 2011-09-28 | ||
PCT/JP2012/069407 WO2013046908A1 (ja) | 2011-09-28 | 2012-07-31 | 半導体装置 |
JP2013536028A JP5676002B2 (ja) | 2011-09-28 | 2012-07-31 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP5676002B2 true JP5676002B2 (ja) | 2015-02-25 |
JPWO2013046908A1 JPWO2013046908A1 (ja) | 2015-03-26 |
Family
ID=47994962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013536028A Active JP5676002B2 (ja) | 2011-09-28 | 2012-07-31 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9202940B2 (ja) |
JP (1) | JP5676002B2 (ja) |
CN (1) | CN103703565B (ja) |
DE (1) | DE112012004043B4 (ja) |
WO (1) | WO2013046908A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014207444A (ja) * | 2013-03-26 | 2014-10-30 | インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag | 炭化珪素装置および炭化珪素装置の形成方法 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6089733B2 (ja) * | 2013-01-30 | 2017-03-08 | 富士電機株式会社 | 半導体装置 |
US9035322B2 (en) | 2013-03-26 | 2015-05-19 | Infineon Technologies Ag | Silicon carbide device and a method for manufacturing a silicon carbide device |
JP2015032665A (ja) * | 2013-08-01 | 2015-02-16 | 住友電気工業株式会社 | ワイドバンドギャップ半導体装置 |
EP3012870A1 (en) * | 2014-10-20 | 2016-04-27 | ABB Technology AG | Edge termination for high voltage semiconductor devices |
CN106796961B (zh) * | 2014-11-05 | 2020-06-19 | 新电元工业株式会社 | 半导体元件 |
CN106328688B (zh) * | 2015-07-02 | 2020-03-06 | 北大方正集团有限公司 | 一种超结器件终端分压区的结构和制作方法 |
CN106340534A (zh) * | 2015-07-09 | 2017-01-18 | 北大方正集团有限公司 | 场限环和结终端扩展复合分压结构及该结构的制造方法 |
US10424635B2 (en) * | 2016-04-06 | 2019-09-24 | Littelfuse, Inc. | High voltage semiconductor device with guard rings and method associated therewith |
CN107359119B (zh) * | 2016-05-09 | 2020-07-14 | 北大方正集团有限公司 | 一种超结功率器件及其制造方法 |
JP6740759B2 (ja) * | 2016-07-05 | 2020-08-19 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
WO2018012159A1 (ja) * | 2016-07-15 | 2018-01-18 | 富士電機株式会社 | 炭化珪素半導体装置 |
JP6611943B2 (ja) * | 2016-07-20 | 2019-11-27 | 三菱電機株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP6760134B2 (ja) * | 2017-03-01 | 2020-09-23 | 株式会社豊田中央研究所 | 半導体装置 |
TWI641152B (zh) * | 2017-03-24 | 2018-11-11 | 王中林 | 電壓增加而電阻值增加的電阻元件 |
CN107425054A (zh) * | 2017-08-07 | 2017-12-01 | 电子科技大学 | 一种功率半导体器件的终端结构 |
DE102017127848A1 (de) * | 2017-11-24 | 2019-05-29 | Infineon Technologies Ag | Siliziumcarbid-Halbleiterbauelement mit Randabschlussstruktur |
US11450734B2 (en) | 2019-06-17 | 2022-09-20 | Fuji Electric Co., Ltd. | Semiconductor device and fabrication method for semiconductor device |
JP7107284B2 (ja) * | 2019-07-08 | 2022-07-27 | 株式会社デンソー | 半導体装置とその製造方法 |
JP7208417B2 (ja) * | 2019-12-03 | 2023-01-18 | 株式会社デンソー | 半導体装置 |
CN114497181B (zh) * | 2021-12-16 | 2023-04-18 | 陕西半导体先导技术中心有限公司 | 一种功率器件的体内复合终端结构及制备方法 |
JP2024060452A (ja) * | 2022-10-19 | 2024-05-02 | 株式会社デンソー | 半導体装置とその製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003101039A (ja) * | 2001-07-17 | 2003-04-04 | Toshiba Corp | 高耐圧半導体装置 |
JP2006269633A (ja) * | 2005-03-23 | 2006-10-05 | Toshiba Corp | 電力用半導体装置 |
JP2008004643A (ja) * | 2006-06-20 | 2008-01-10 | Toshiba Corp | 半導体装置 |
JP2008147362A (ja) * | 2006-12-08 | 2008-06-26 | Toyota Central R&D Labs Inc | 半導体装置 |
JP2010067737A (ja) * | 2008-09-10 | 2010-03-25 | Sony Corp | 半導体装置およびその製造方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3971059A (en) * | 1974-09-23 | 1976-07-20 | National Semiconductor Corporation | Complementary bipolar transistors having collector diffused isolation |
US4027325A (en) * | 1975-01-30 | 1977-05-31 | Sprague Electric Company | Integrated full wave diode bridge rectifier |
CH668147A5 (de) * | 1985-05-22 | 1988-11-30 | Landis & Gyr Ag | Einrichtung mit einem hallelement in integrierter halbleitertechnologie. |
JP3221673B2 (ja) * | 1989-11-01 | 2001-10-22 | 新電元工業株式会社 | 高耐圧半導体装置 |
US6096618A (en) * | 1998-01-20 | 2000-08-01 | International Business Machines Corporation | Method of making a Schottky diode with sub-minimum guard ring |
JP4597284B2 (ja) * | 1999-04-12 | 2010-12-15 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US6525394B1 (en) * | 2000-08-03 | 2003-02-25 | Ray E. Kuhn | Substrate isolation for analog/digital IC chips |
GB2373634B (en) * | 2000-10-31 | 2004-12-08 | Fuji Electric Co Ltd | Semiconductor device |
JP2002231965A (ja) | 2001-02-01 | 2002-08-16 | Hitachi Ltd | 半導体装置 |
JP2003347547A (ja) * | 2002-05-27 | 2003-12-05 | Mitsubishi Electric Corp | 電力用半導体装置及びその製造方法 |
JP2006005275A (ja) * | 2004-06-21 | 2006-01-05 | Toshiba Corp | 電力用半導体素子 |
JP2006210667A (ja) * | 2005-01-28 | 2006-08-10 | Mitsubishi Electric Corp | 半導体装置 |
US7511346B2 (en) * | 2005-12-27 | 2009-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Design of high-frequency substrate noise isolation in BiCMOS technology |
JP2007266123A (ja) * | 2006-03-27 | 2007-10-11 | Toyota Central Res & Dev Lab Inc | 半導体装置 |
US7737469B2 (en) | 2006-05-16 | 2010-06-15 | Kabushiki Kaisha Toshiba | Semiconductor device having superjunction structure formed of p-type and n-type pillar regions |
DE102006055151B4 (de) | 2006-11-22 | 2011-05-12 | Infineon Technologies Austria Ag | Halbleiterbauelement mit Halbleiterzone sowie Verfahren zu dessen Herstellung |
CN101345254A (zh) * | 2007-07-12 | 2009-01-14 | 富士电机电子技术株式会社 | 半导体器件 |
KR101220568B1 (ko) * | 2008-03-17 | 2013-01-21 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
US8324705B2 (en) * | 2008-05-27 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Schottky diodes having low-voltage and high-concentration rings |
JP5376365B2 (ja) * | 2009-04-16 | 2013-12-25 | 三菱電機株式会社 | 半導体装置 |
JP5224289B2 (ja) * | 2009-05-12 | 2013-07-03 | 三菱電機株式会社 | 半導体装置 |
JP5383357B2 (ja) * | 2009-07-08 | 2014-01-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
WO2011013379A1 (en) * | 2009-07-31 | 2011-02-03 | Fuji Electric Systems Co., Ltd. | Semiconductor apparatus |
JP2011071160A (ja) * | 2009-09-24 | 2011-04-07 | Toshiba Corp | 半導体装置 |
JP5509908B2 (ja) * | 2010-02-19 | 2014-06-04 | 富士電機株式会社 | 半導体装置およびその製造方法 |
WO2012056704A1 (ja) * | 2010-10-29 | 2012-05-03 | パナソニック株式会社 | 半導体素子および半導体装置 |
-
2012
- 2012-07-31 CN CN201280036061.2A patent/CN103703565B/zh active Active
- 2012-07-31 DE DE112012004043.0T patent/DE112012004043B4/de active Active
- 2012-07-31 JP JP2013536028A patent/JP5676002B2/ja active Active
- 2012-07-31 WO PCT/JP2012/069407 patent/WO2013046908A1/ja active Application Filing
- 2012-07-31 US US14/239,375 patent/US9202940B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003101039A (ja) * | 2001-07-17 | 2003-04-04 | Toshiba Corp | 高耐圧半導体装置 |
JP2006269633A (ja) * | 2005-03-23 | 2006-10-05 | Toshiba Corp | 電力用半導体装置 |
JP2008004643A (ja) * | 2006-06-20 | 2008-01-10 | Toshiba Corp | 半導体装置 |
JP2008147362A (ja) * | 2006-12-08 | 2008-06-26 | Toyota Central R&D Labs Inc | 半導体装置 |
JP2010067737A (ja) * | 2008-09-10 | 2010-03-25 | Sony Corp | 半導体装置およびその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014207444A (ja) * | 2013-03-26 | 2014-10-30 | インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag | 炭化珪素装置および炭化珪素装置の形成方法 |
Also Published As
Publication number | Publication date |
---|---|
DE112012004043T5 (de) | 2014-07-24 |
US20140203393A1 (en) | 2014-07-24 |
US9202940B2 (en) | 2015-12-01 |
CN103703565A (zh) | 2014-04-02 |
WO2013046908A1 (ja) | 2013-04-04 |
CN103703565B (zh) | 2017-09-01 |
DE112012004043B4 (de) | 2018-03-22 |
JPWO2013046908A1 (ja) | 2015-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5676002B2 (ja) | 半導体装置 | |
US10115834B2 (en) | Method for manufacturing an edge termination for a silicon carbide power semiconductor device | |
US8716717B2 (en) | Semiconductor device and method for manufacturing the same | |
JP4621708B2 (ja) | 半導体装置及びその製造方法 | |
US10840238B2 (en) | Semiconductor device | |
CN105097934B (zh) | 半导体器件及其制造方法 | |
JP5406171B2 (ja) | SiC半導体装置 | |
JP6415749B2 (ja) | 炭化珪素半導体装置 | |
US11195908B2 (en) | Semiconductor device with carrier lifetime control | |
US9142687B2 (en) | Semiconductor diode device | |
JP2008004643A (ja) | 半導体装置 | |
KR20140015412A (ko) | 오버랩 도핑 영역을 갖는 쇼트키 다이오드를 포함하는 반도체 디바이스 및 그 제조 방법 | |
KR20140023942A (ko) | 우묵한 종단 구조 및 우묵한 종단 구조를 포함하는 전자 장치를 제조하는 방법 | |
US9196488B2 (en) | Semiconductor device and manufacturing method thereof | |
JP6833848B2 (ja) | 面積効率の良いフローティングフィールドリング終端 | |
JP2023065461A (ja) | 半導体装置 | |
US20180047855A1 (en) | Power semiconductor element and power semiconductor module using same | |
US9620600B2 (en) | Semiconductor device having termination region with laterally heterogeneous insulating films | |
JP5735611B2 (ja) | SiC半導体装置 | |
US20230187489A1 (en) | Silicon carbide semiconductor device | |
US20160276441A1 (en) | Semiconductor device | |
JP7280213B2 (ja) | 半導体装置 | |
WO2024084778A1 (ja) | 半導体装置とその製造方法 | |
US11430862B2 (en) | Superjunction semiconductor device including parallel PN structures and method of manufacturing thereof | |
JP2022137613A (ja) | SiC-MOSFET |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141125 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141224 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5676002 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |