JPWO2021009828A1 - 半導体装置、電力変換装置および半導体装置の製造方法 - Google Patents
半導体装置、電力変換装置および半導体装置の製造方法 Download PDFInfo
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Abstract
Description
本発明の実施形態の説明に入る前に、前提技術としてのスーパージャンクション構造を備える半導体装置について説明する。図1は、前提技術としての半導体装置の平面模式図である。この半導体装置は、特許文献1に開示されたものに相当する。また、図2は、図1のA1−A2線に沿った断面図であり、図3は、図1のC1−C2線に沿った断面図である。
図5は、本発明の実施の形態1に係る半導体装置の構造を示す図であり、半導体装置における終端構造のコーナー部近傍の平面模式図である。また、図6は、図5のD1−D2線に沿った断面図であり、図7は、図5のE1−E2線に沿った断面図である。これらの図において、図1〜図3に示したものと同様の機能を有する要素には同一符号を付してある。
図20は、本発明の実施の形態2に係る半導体装置の構成を示す平面図である。ただし、作図の都合上、説明に不要な構成要素(ショットキーコンタクト電極87、アノード電極88等)の記載は省略している。また、実施の形態2に係る半導体装置の構成要素の大部分は実施の形態1と同様であるため、ここでは、実施の形態1と同様の構成要素の説明は省略し、実施の形態2に特有の構成について説明する。
図21は、本発明の実施の形態3に係る半導体装置の構成を示す平面図である。ただし、作図の都合上、説明に不要な構成要素(ショットキーコンタクト電極87、アノード電極88等)の記載は省略している。また、実施の形態3に係る半導体装置の構成要素の大部分は実施の形態2と同様であるため、ここでは、実施の形態2と同様の構成要素の説明は省略し、実施の形態3に特有の構成について説明する。
図22は、本発明の実施の形態4に係る半導体装置の構成を示す平面図である。ただし、作図の都合上、説明に不要な構成要素(ショットキーコンタクト電極87、アノード電極88等)の記載は省略している。また、実施の形態4に係る半導体装置の構成要素の大部分は実施の形態3と同様であるため、ここでは、実施の形態3と同様の構成要素の説明は省略し、実施の形態4に特有の構成について説明する。
図23は、本発明の実施の形態5に係る半導体装置の構成を示す平面図である。ただし、作図の都合上、説明に不要な構成要素(ショットキーコンタクト電極87、アノード電極88等)の記載は省略している。また、実施の形態5に係る半導体装置の構成要素の大部分は実施の形態4と同様であるため、ここでは、実施の形態4と同様の構成要素の説明は省略し、実施の形態5に特有の構成について説明する。
図24は、本発明の実施の形態6に係る半導体装置の構成を示す平面図である。ただし、作図の都合上、説明に不要な構成要素(ショットキーコンタクト電極87、アノード電極88等)の記載は省略している。また、実施の形態6に係る半導体装置の構成要素の大部分は実施の形態5と同様であるため、ここでは、実施の形態5と同様の構成要素の説明は省略し、実施の形態6に特有の構成について説明する。
図25は、本発明の実施の形態7に係る半導体装置の構成を示す平面図である。ただし、作図の都合上、説明に不要な構成要素(ショットキーコンタクト電極87、アノード電極88等)の記載は省略している。また、実施の形態7に係る半導体装置の構成要素の大部分は実施の形態6と同様であるため、ここでは、実施の形態6と同様の構成要素の説明は省略し、実施の形態7に特有の構成について説明する。
図26は、本発明の実施の形態8に係る半導体装置の構成を示す平面図である。ただし、作図の都合上、説明に不要な構成要素(ショットキーコンタクト電極87、アノード電極88等)の記載は省略している。また、実施の形態8に係る半導体装置の構成要素の大部分は実施の形態7と同様であるため、ここでは、実施の形態7と同様の構成要素の説明は省略し、実施の形態8に特有の構成について説明する。
実施の形態9では、実施の形態1〜8に係る半導体装置を電力変換装置に適用する。ここでは特に、実施の形態1〜8に相当するスーパージャンクション層15および耐圧保持構造56を備えるスイッチング素子(例えばMOSFET)および整流素子(例えばSBD)を、3相のインバータに適用した場合について説明する。
実施の形態1〜8では、半導体装置の例としてSBDを示したが、半導体装置はSBDに限られず、JBS(junction barrier diode)、pn接合ダイオード、MOSFET、JFET(junction field-effect transistor)、IGBT等でもよい。
Claims (17)
- 半導体基板と、
前記半導体基板上に形成され、第1導電型の第1ピラー層および第2導電型の第2ピラー層が交互に配置されたスーパージャンクション層を含む半導体層と、
前記半導体層の上層部に活性領域を取り囲むように形成された、第2導電型の複数の耐圧保持構造と、
を備え、
少なくとも1つの前記耐圧保持構造は、平面視で前記スーパージャンクション層と重なっており、
前記スーパージャンクション層と平面視で重なる前記耐圧保持構造の少なくとも1つは、当該耐圧保持構造の途切れた部分である間隙を有している、
半導体装置。 - 前記スーパージャンクション層における前記第1ピラー層および前記第2ピラー層の配置は、平面視で回転非対称である、
請求項1に記載の半導体装置。 - 全ての前記耐圧保持構造が、前記間隙を有している、
請求項1または請求項2に記載の半導体装置。 - 最内周の前記耐圧保持構造は、前記間隙を有しておらず、
最内周の前記耐圧保持構造を除く全ての前記耐圧保持構造は、前記間隙を有している、
請求項1または請求項2に記載の半導体装置。 - 全ての前記耐圧保持構造が、平面視で前記スーパージャンクション層と重なっており、且つ、前記間隙を有している、
請求項1または請求項2に記載の半導体装置。 - 全ての前記耐圧保持構造は、平面視で前記スーパージャンクション層と重なっており、
最内周の前記耐圧保持構造は、前記間隙を有しておらず、
最内周の前記耐圧保持構造を除く全ての前記耐圧保持構造は、前記間隙を有している、
請求項1または請求項2に記載の半導体装置。 - 前記スーパージャンクション層において、前記第1ピラー層および前記第2ピラー層はストライプ状に配置されている、
請求項1から請求項6のいずれか一項に記載の半導体装置。 - 前記間隙は、前記耐圧保持構造の曲線部に形成されている、
請求項1から請求項7のいずれか一項に記載の半導体装置。 - 前記間隙は、前記耐圧保持構造の直線部には形成されていない、
請求項8に記載の半導体装置。 - 前記間隙は、前記第1ピラー層と前記第2ピラー層とに跨がるように形成されており、
前記間隙とそれが属する前記耐圧保持構造との間の2つの境界線は、前記第1ピラー層と前記第2ピラー層との境界線に接しておらず、
前記間隙とそれが属する前記耐圧保持構造との間の2つの境界線のうち、前記第2ピラー層の長手方向に平行な前記活性領域の中心線に近い側の境界線は、平面視で前記第2ピラー層に内包されており、前記活性領域の前記中心線から遠い側の境界線は、平面視で前記第1ピラー層に内包されている、
請求項1から請求項9のいずれか一項に記載の半導体装置。 - 前記間隙とそれが属する前記耐圧保持構造との間の2つの境界線のうち、前記活性領域の前記中心線から近い側の境界線を内包する前記第2ピラー層と、前記活性領域の前記中心線から遠い側の境界線を内包する前記第1ピラー層とが隣り合っている、
請求項10に記載の半導体装置。 - 隣り合う前記耐圧保持構造の前記間隙同士は、平面視で、前記耐圧保持構造の径方向に隣り合わないように、互いにずらして配置されている、
請求項1から請求項11のいずれか一項に記載の半導体装置。 - 前記半導体基板はオフ角を有する、
請求項1から請求項12のいずれか一項に記載の半導体装置。 - 前記半導体基板は炭化珪素基板である、
請求項1から請求項13のいずれか一項に記載の半導体装置。 - 前記耐圧保持構造の第2導電型の不純物濃度は、1×1013cm−2以上である、
請求項14に記載の半導体装置。 - 請求項1から請求項15のいずれか一項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
前記半導体装置を駆動する駆動信号を前記半導体装置に出力する駆動回路と、
前記駆動回路を制御する制御信号を前記駆動回路に出力する制御回路と、
を備えた電力変換装置。 - 半導体基板上に第1導電型の第1半導体層を形成する工程と、
前記第1半導体層にストライプ状のトレンチを形成し、前記トレンチに第2導電型の第2半導体層を埋め込むことで、前記第1半導体層から成る第1ピラー層および第2半導体層から成る第2ピラー層が交互に配置されたスーパージャンクション層を形成する工程と、
注入マスクを用いたイオン注入によって、前記スーパージャンクション層を含む前記第1半導体層および前記第2半導体層の上層部に、活性領域を取り囲む第2導電型の複数の耐圧保持構造を形成する工程と、
を備え、
少なくとも1つの前記耐圧保持構造は、平面視で前記スーパージャンクション層と重なっており、
前記スーパージャンクション層と平面視で重なる前記耐圧保持構造の少なくとも1つは、当該耐圧保持構造の途切れた部分である間隙を有している、
半導体装置の製造方法。
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