WO2014186988A1 - 主动元件阵列基板及其制造方法 - Google Patents

主动元件阵列基板及其制造方法 Download PDF

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Publication number
WO2014186988A1
WO2014186988A1 PCT/CN2013/076519 CN2013076519W WO2014186988A1 WO 2014186988 A1 WO2014186988 A1 WO 2014186988A1 CN 2013076519 W CN2013076519 W CN 2013076519W WO 2014186988 A1 WO2014186988 A1 WO 2014186988A1
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WO
WIPO (PCT)
Prior art keywords
hole
layer
inorganic
protective layer
array substrate
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Application number
PCT/CN2013/076519
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English (en)
French (fr)
Inventor
柯聪盈
王品凡
许慈轩
李威德
Original Assignee
友达光电股份有限公司
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Publication of WO2014186988A1 publication Critical patent/WO2014186988A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the invention relates to an active device array substrate and a method of manufacturing the same.
  • the industry has introduced a display made of a soft material as a substrate material. Since the display itself has a certain degree of flexibility, it can be used to replace conventional paper or advertising billboards.
  • the material of the substrate is a soft material, in order to facilitate the process, most of the manufacturers need to fix the substrate on the carrier board to be suitable for the existing machine. After the manufacturing is completed, the substrate is self-loaded. The plate is peeled off.
  • One aspect of the present invention is to provide an active device array substrate for solving or improving the problems mentioned in the prior art.
  • an active device array substrate includes a flexible substrate, an inorganic barrier layer, and at least one active device.
  • the inorganic barrier layer covers the flexible substrate.
  • the inorganic barrier layer described above has at least a uniform perforation therein, and the through hole exposes the flexible substrate.
  • the active component is on the inorganic barrier layer.
  • the active device may include a gate, a gate dielectric layer, a channel layer, a source and a drain.
  • the gate is on the inorganic barrier layer.
  • the gate dielectric layer covers at least the gate.
  • the channel layer is on the gate dielectric layer above the gate.
  • the source and the drain are respectively located on both sides of the channel layer.
  • the gate dielectric layer covers the gate and the inorganic barrier layer, and the gate dielectric layer has at least a uniform via hole therein, wherein the through hole of the gate dielectric layer is connected to the inorganic layer Resistance Through hole of the barrier layer.
  • the inorganic barrier layer has a pitch between the through hole and the gate.
  • the active device array substrate may further include an inorganic protective layer, an organic protective layer, and a pixel electrode.
  • An inorganic protective layer covers the active device, and the inorganic protective layer has at least a uniform perforation therein, wherein the through hole of the inorganic protective layer at least partially overlaps the through hole of the gate dielectric layer and the through hole of the inorganic barrier layer.
  • the organic protective layer covers the inorganic protective layer.
  • the pixel electrode is located on the organic protective layer and electrically connected to the active component.
  • the active device array substrate further includes an inorganic protective layer covering the active device and having at least a uniform perforation therein, wherein the inorganic protective layer has a through hole and an inorganic barrier The through holes of the barrier layer at least partially overlap.
  • the active device array substrate may further include an organic protective layer covering the active device.
  • the organic protective layer may have at least a uniform perforation therein, wherein the through hole of the organic protective layer at least partially overlaps the through hole of the inorganic barrier layer.
  • At least a portion of the organic protective layer may be filled in the through holes of the inorganic barrier layer.
  • the active device array substrate further includes a pixel electrode, and the pixel electrode is located on the active device and electrically connected to the active device.
  • the pixel electrode may have at least a uniform via therein, wherein the through hole of the pixel electrode at least partially overlaps the through hole of the inorganic barrier layer.
  • the pixel electrode may cover a through hole of the inorganic barrier layer.
  • the active device array substrate further includes at least one inorganic filler that conformally covers the through hole of the inorganic barrier layer.
  • the active device array substrate further includes a photographic release film disposed on a surface of the flexible substrate opposite to the inorganic barrier layer.
  • Another aspect of the present invention provides a method of fabricating an active device array substrate.
  • a method for manufacturing an active device array substrate includes the following steps (it should be understood that the steps mentioned in the present embodiment may be specified unless otherwise specified Adjust the order before and after the actual needs, or even simultaneously or partially. :):
  • the soft substrate is adhered to the carrier with a photosensitive release film.
  • the photosensitive release film is irradiated with a light source.
  • the above step (3) may comprise the following sub-steps: (3.1) Forming a gate on the inorganic barrier layer.
  • Source and drain are formed on both sides of the channel layer.
  • the method for fabricating the active device array substrate further includes: forming a through hole in the gate dielectric layer, wherein the through hole of the gate dielectric layer and the through hole of the inorganic barrier layer A communicating vent is formed to expose the flexible substrate.
  • the method for fabricating the active device array substrate further includes: forming a through hole in the gate dielectric layer. Forming an inorganic protective layer, the inorganic protective layer covering the active device, and the inorganic protective layer has at least a uniform perforation therein, wherein the through hole of the inorganic protective layer communicates with the through hole of the gate dielectric layer and the through hole of the inorganic barrier layer, To form a vent. An organic protective layer is formed on the inorganic protective layer. Forming a pixel electrode on the organic protective layer and electrically connecting the active device.
  • the method for manufacturing an active device array substrate may further include: forming an inorganic protective layer covering the active device, wherein the inorganic protective layer has a through hole that is at least uniformly perforated therein, the inorganic protective layer A through hole communicating with the through hole of the inorganic barrier layer is formed to expose the flexible substrate.
  • the method for fabricating the active device array substrate may further include: forming an inorganic filler in the through hole of the inorganic barrier layer. National day against the sun
  • FIGS. 2A to 2L are cross-sectional views showing a manufacturing process of the active device array substrate of FIG. As shown in line ii of Figure 1;
  • 3A to 3D are cross-sectional views showing the manufacturing process of the active device array substrate according to the second embodiment of the present invention, the cross-sectional positions of which are the same as those of Figs. 2A to 2J;
  • FIGS. 4A to 4G are cross-sectional views showing the manufacturing process of the active device array substrate according to the third embodiment of the present invention, and the cross-sectional positions thereof are the same as those of Figs. 2A to 2G;
  • FIGS. 5A to 5E are cross-sectional views showing a manufacturing process of an active device array substrate according to a fourth embodiment of the present invention, and the cross-sectional positions thereof are the same as those of Figs. 4A to 4B;
  • 6A to 6E are cross-sectional views showing a manufacturing process of an active device array substrate according to a fifth embodiment of the present invention, and the cross-sectional position thereof is the same as that of FIG. 5A;
  • FIG. 7A to 7E are cross-sectional views showing a manufacturing process of an active device array substrate according to a sixth embodiment of the present invention, the cross-sectional positions of which are the same as those of Figs. 2A to 2H;
  • FIG. 8 is a graph showing a load-to-displacement curve of a comparative example of the present invention.
  • Figure 9 illustrates a load versus displacement curve for an embodiment of the present invention.
  • FIG. 1 is a top plan view of an active device array substrate 100 in accordance with a first embodiment of the present invention.
  • 2A to 2L are cross-sectional views showing the manufacturing process of the active device array substrate 100 of Fig. 1, the cross-sectional position of which is shown in line I-I of Fig. 1. It should be understood that the top view of the active device array substrate 100 of FIG. 1 is for illustrative purposes only, and is not limited to the above-described drawings. Those skilled in the art to which the present invention pertains may appropriately change the design according to actual needs.
  • the manufacturer can first adhere the flexible substrate 110 to the carrier 200 with the photosensitive release film 300 to facilitate subsequent processes. Specifically, the manufacturer may first form the photosensitive release film 300 on the carrier 200 by chemical vapor deposition and then form the soft substrate 110 on the photosensitive release film 300 by spin coating. Of course, if conditions permit, the manufacturer may also choose to adhere the flexible substrate 110 to the carrier 200 through the photosensitive release film 300 in a compliant manner.
  • the material of the carrier 200 described above may be any hard material such as transparent glass.
  • the thickness of the carrier 200 may be about 0.7 mm (mm); the material of the millimeter photosensitive release film 300 may be an organic material sensitive to ultraviolet light or sensitive to light of a specific wavelength band, such as poly(p-xylylene). Or the thickness of the photosensitive release film 300 may be about 300 nm (nanometer).
  • the material of the flexible substrate 110 may be any flexible material, such as polyimide (Polyimide; PI), poly Polyethylene terephthalate (PET), Polyethylene Naphthalate (PEN), or any combination thereof.
  • the flexible substrate 110 may have a thickness of about 10 to 100. ⁇ (;micron; micrometer;).
  • the manufacturer can form an inorganic barrier layer 120 at this time, and the inorganic barrier layer 120 covers the flexible substrate 110.
  • the material of the inorganic barrier layer 120 may be any inorganic dielectric material capable of blocking water oxygen, such as silicon nitride, silicon oxide, silicon oxynitride or any combination thereof.
  • the inorganic barrier layer 120 may have a thickness of about 10 to 1000 nm (nanometer; nanometer:).
  • the inorganic barrier layer 120 may be formed by, for example, a chemical vapor deposition method.
  • the manufacturer can form a gate 132 on the inorganic barrier layer 120 at this time. Specifically, the manufacturer may first form a first conductive layer on the inorganic barrier layer 120, and The first conductive layer is patterned to form a gate 132.
  • the material of the first conductive layer may be titanium, molybdenum, chromium, tantalum, aluminum, copper, silver, gold or any combination or alloy thereof.
  • the first conductive layer (or gate 132) may have a thickness of about 10 to 500 nm (nanometer: nanometer:).
  • the first conductive layer may be formed by a physical vapor deposition method such as sputtering.
  • the manner in which the first conductive layer is patterned may be, for example, lithography and etching.
  • the manufacturer can form a gate dielectric layer 134 at this time.
  • the gate dielectric layer 134 covers the gate 132 and the inorganic barrier layer 120.
  • the material of the gate dielectric layer 134 may be any dielectric material such as silicon nitride, silicon oxide, silicon oxynitride or any combination thereof.
  • the gate dielectric layer 134 may have a thickness of about 100 to 1000 nm (nanometer; nanometer;).
  • the gate dielectric layer 134 may be formed by, for example, a chemical vapor deposition method.
  • the manufacturer can form a channel layer 136 on the gate dielectric layer 134 over the gate 132 at this time.
  • the manufacturer may first form a semiconductor layer on the gate dielectric layer 134 and subsequently pattern the semiconductor layer to form the channel layer 136.
  • the material of the above semiconductor layer may be any semiconductor material such as amorphous silicon, polycrystalline silicon, single crystal silicon, oxide semiconductor or any combination thereof.
  • the semiconductor layer (or the channel layer 136) may have a thickness of about 10 to 500 nm (nanometer; the nanometer ⁇ semiconductor layer may be formed by, for example, a chemical vapor deposition method.
  • the manner of patterning the semiconductor layer may be, for example, lithography and etching. Law.
  • the manufacturer can form source 138 and drain 139 on both sides of channel layer 136 at this time. Specifically, the manufacturer may first form a second conductive layer on the channel layer 136 and the gate dielectric layer 134, and then pattern the second conductive layer to form the source 138 and the drain 139.
  • the second conductive layer (or the source 138 and the drain 139) may be made of titanium, molybdenum, chromium, tantalum, aluminum, copper, silver, gold or any combination or alloy thereof.
  • the second conductive layer (or source 138 and drain 139) may have a thickness of about 10 to 500 nm (; nanometer;
  • the second conductive layer can be formed by physical vapor deposition, such as sputtering.
  • the manner in which the second conductive layer is patterned may be, for example, lithography and etching.
  • gate 132, gate dielectric layer 134, channel layer 136, source 138 and drain 139 will collectively form active device 130.
  • active device 130 is illustrated as a bottom gate thin film transistor in this embodiment, the present invention is not limited thereto. In fact, the active device 130 may also be Other forms of active components, such as top-gate thin film transistors, one of ordinary skill in the art to which the present invention pertains, may flexibly select embodiments of the active component 130 as desired.
  • the manufacturer can form an inorganic protective layer 140 at this time, which covers the active device 130.
  • the material of the inorganic protective layer 140 may be any inorganic dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride or any combination thereof.
  • the inorganic protective layer 140 may have a thickness of about 100 to 1000 nm (nanometer; nanometer:).
  • the inorganic protective layer 140 may be formed by, for example, a chemical vapor deposition method.
  • the manufacturer can form an organic protective layer 150 at this time, and the organic protective layer 150 covers the active device 130.
  • the organic protective layer 150 covers the inorganic protective layer 140, but this does not limit the invention. If the active device 130 or the inorganic protective layer 140 has other layers thereon, such as other dielectric layers or barrier layers, organic Protective layer 150 can also cover these laminates. That is, the organic protective layer 150 may directly or indirectly cover the inorganic protective layer 140.
  • the material of the organic protective layer 150 described above may be any organic dielectric material such as an acrylic polymer.
  • the organic protective layer 150 may have a thickness of about 3 ⁇ m (micrometers;
  • the organic protective layer 150 may be formed by, for example, a spin coating method.
  • the manufacturer can form a pixel electrode 160 at this time, and the pixel electrode 160 is electrically connected to the active device 130. Specifically, the manufacturer may first form a pixel electrode communication hole TH which penetrates the stack above the drain electrode 139 to expose the drain electrode 139.
  • the laminate over the drain electrode 139 includes the inorganic protective layer 140 and the organic protective layer 150, the pixel electrode communication hole TH penetrates through the inorganic protective layer 140 and the organic protective layer 150, exposing the drain electrode 139.
  • the manufacturer can form a third conductive layer covering the organic protective layer 150 and the pixel electrode communication hole TH, and then pattern the third conductive layer to form the pixel electrode 160.
  • the formed pixel electrode 160 is electrically connected to the drain electrode 139 through the pixel electrode communication hole TH.
  • the material of the third conductive layer may be any conductive material.
  • the material of the third conductive layer (or the pixel electrode 160) may be a transparent conductive material, such as: indium tin oxide, indium zinc oxide, zinc aluminum oxide or other conductive oxide or any combination thereof.
  • the material of the third conductive layer (or the pixel electrode 160) may be other opaque conductive materials, such as titanium, molybdenum, chromium, tantalum, aluminum, copper, silver, gold, or any combination or alloy thereof.
  • the third conductive layer (or, in other words, the pixel electrode 160) may have a thickness of about 10 to 500 nm (nanometer; nanometer:).
  • the third conductive layer may be formed by, for example, physical vapor deposition or chemical vapor deposition.
  • the manner in which the pixel electrode communication hole TH and the patterned third conductive layer are formed may be, for example, lithography and etching.
  • the manufacturer can form at least one vent GH at this time, the vent GH extending at least through the inorganic barrier layer 120 to expose the flexible substrate 110.
  • the position of the vent GH can be selected at a position around the active device 130, that is, it does not need to pass through the gate 132, the channel layer source 138 and the drain 139 on the flexible substrate 110. position.
  • the stack through which the vent GH is required to pass it depends on the stack above the flexible substrate 110 at this position.
  • the vent GH will penetrate the pixel electrode 160, the organic protective layer 150, the inorganic protective layer 140, the gate dielectric layer 134, and the inorganic barrier layer 120, so that the flexible substrate 110 is exposed. That is, the steps will form through holes 162, 152, 142, 135, 122 in the pixel electrode 160, the organic protective layer 150, the inorganic protective layer 140, the gate dielectric layer 134 and the inorganic barrier layer 120, respectively.
  • the through holes 162, 152, 142, 135, 122 will constitute a communicating vent GH.
  • the manner in which the vent GH is formed may be, for example, lithography and etching.
  • the manufacturer can irradiate the photosensitive release film 300 with the light source at this time, so that the adhesion between the photo-oxidized photosensitive release film 300 and the carrier 200 is lowered.
  • the manufacturer can mount the light source on the back side of the carrier 200 with respect to the photosensitive release film 300 such that light emitted from the light source passes through the carrier 200 to illuminate the photosensitive release film 300.
  • the inorganic barrier layer is not permeable to oxygen and there is no vent hole, even if the material of the flexible substrate is permeable to oxygen, the oxygen cannot pass through the inorganic barrier layer and cannot contact the photosensitive release film.
  • Adjacent to the front side of the flexible substrate it can only contact the exposed side portion of the photosensitive release film.
  • the oxygen may also contact the photosensitive release film 300 through the vent hole GH and the flexible substrate 110.
  • the front side makes the photo-release film 300 lightly oxidize faster, reducing the time required for the process.
  • the above light source may be an ultraviolet light, such as: Ultraviolet A Light (UVA Light), Ultraviolet B Light (UVB Light) or Short Wave Ultraviolet Light
  • the material of the carrier 200 may be selected to be a material that can transmit light emitted from the light source, for example, transparent glass.
  • the manufacturer can peel off the photosensitive release film 300 and load at this time.
  • the board 200 is used to obtain the active device array substrate 100.
  • the active device array substrate 100 of FIG. 2L includes a flexible substrate 110, an inorganic barrier layer 120, and at least one active device 130.
  • the inorganic barrier layer 120 covers the flexible substrate 110.
  • the inorganic barrier layer 120 has at least a uniform via 122 therein, and the through hole 122 exposes the flexible substrate 110.
  • the active component 130 is located on the inorganic barrier layer 120.
  • the active device array substrate 100 further includes a photosensitive release film 300 disposed on the flexible substrate 110 and disposed on the surface of the flexible substrate 110 opposite to the inorganic barrier layer 120.
  • active device 130 can include a gate 132, a gate dielectric layer 134, a channel layer 136, a source 138, and a drain 139.
  • the gate 132 is on the inorganic barrier layer 120.
  • Gate dielectric layer 134 covers gate 132 and inorganic barrier layer 120.
  • the gate dielectric layer 134 has at least a uniform via 135 therein, wherein the through via 135 of the gate dielectric layer 134 is in communication with the through via 122 of the inorganic barrier layer 120. That is, the vertical projection of the through via 135 of the gate dielectric layer 134 on the flexible substrate 110 at least partially overlaps the vertical projection of the through via 122 of the inorganic barrier layer 120 on the flexible substrate 110.
  • the channel layer 136 is located on the gate dielectric layer 134 above the gate 132.
  • the source 138 and the drain 139 are respectively located at the channel layer 136.
  • the through hole 122 of the inorganic barrier layer 120 is a vent hole. A part of GH, and because of the position of the vent GH, it is possible to select a position on the flexible substrate 110 that does not need to pass through the gate 132, the channel layer 136, the source 138 and the drain 139, and thus the through hole of the inorganic barrier layer 120 described above.
  • There is a spacing between 122 and the gate 132 (as indicated by the spacing G1:). More specifically, the vertical projection of the through hole 122 of the inorganic barrier layer 120 on the flexible substrate 110, and the vertical projection of the gate 132, the channel layer 136, the source 138 and the drain 139 on the flexible substrate 110 are both Do not overlap.
  • the through hole 135 of the gate dielectric layer 134 is also a part of the vent hole GH, and since the position of the vent hole GH can be selected on the flexible substrate 110, it is not required to pass through the gate 132, the channel layer 136, and the source 138.
  • the bit S of the drain 139 therefore also has a spacing (as indicated by the spacing G1) between the through via 135 of the gate dielectric layer 134 and the gate 132. More specifically, the vertical projection of the through hole 135 of the gate dielectric layer 134 on the flexible substrate 110 and the vertical projection of the gate 132, the channel layer 136, the source 138 and the drain 139 on the flexible substrate 110 are both Do not overlap.
  • the active device array substrate 100 further includes an inorganic protective layer 140 covering the active device 13G and having at least a uniform via 142 therein.
  • the through hole 142 of the inorganic protective layer 140 is also a part of the vent hole GH. Therefore, the through hole 142 of the inorganic protective layer 140 also communicates with the through hole 135 of the gate dielectric layer 134 and the through hole 122 of the inorganic barrier layer 120.
  • the vertical projection of the through hole 142 of the inorganic protective layer 140 on the flexible substrate 110 at least partially overlaps with the vertical projection of the through hole 122 of the inorganic barrier layer 120 on the flexible substrate 110.
  • the vertical projection of the through hole 142 of the inorganic protective layer 140 on the flexible substrate 110 and the vertical projection of the through hole 135 of the gate dielectric layer 134 on the flexible substrate 110 also at least partially overlap.
  • the inorganic protective layer 140 described above There is a spacing between the through holes 142 and the drain 139 of the active device 130 (as indicated by the spacing G2). More specifically, the vertical projection of the through hole 142 of the inorganic protective layer 140 on the flexible substrate 110 is not perpendicular to the vertical projection of the gate 132, the channel layer 136, the source 138 and the drain 139 on the flexible substrate 110. overlapping.
  • the active device array substrate 100 further includes an organic protective layer 150 covering the active device 130.
  • the organic protective layer 150 covers the inorganic protective layer 140 and has at least a uniform perforation 152 therein.
  • the through hole 152 of the organic protective layer 150 is also a part of the vent hole GH. Therefore, the through hole 152 of the organic protective layer 150 is also connected to the through hole 142 of the inorganic protective layer 140, the through hole 135 of the gate dielectric layer 134, and the inorganic barrier.
  • the through hole 122 of the layer 120 is also connected to the through hole 142 of the inorganic protective layer 140, the through hole 135 of the gate dielectric layer 134, and the inorganic barrier.
  • the vertical projection of the through hole 152 of the organic protective layer 150 on the flexible substrate 110 at least partially overlaps with the vertical projection of the through hole 122 of the inorganic barrier layer 120 on the flexible substrate 110.
  • the vertical projection of the through hole 152 of the organic protective layer 150 on the flexible substrate 110 at least partially overlaps with the vertical projection of the through via 135 of the gate dielectric layer 134 on the flexible substrate 110.
  • the vertical projection of the through hole 152 of the organic protective layer 150 on the flexible substrate 110 at least partially overlaps with the vertical projection of the through hole 142 of the inorganic protective layer 140 on the flexible substrate 110.
  • the position of the vent GH can be selected on the flexible substrate 110 without passing through the positions of the gate 132, the channel layer 136, the source 138 and the drain 139, the above-mentioned organic protective layer 150
  • the vertical projection of the through hole 152 of the organic protective layer 150 on the flexible substrate 110 is not perpendicular to the vertical projection of the gate 132, the channel layer 136, the source 138 and the drain 139 on the flexible substrate 110. overlapping.
  • the active device array substrate 100 further includes a pixel electrode 160 disposed on the active device 130 and electrically connected to the active device 130.
  • the pixel electrode 160 is located on the organic protective layer 150 and has at least a uniform via 162 therein. Pixel electrode The through hole 162 of the 160 is also a part of the vent hole GH. Therefore, the through hole 162 of the pixel electrode 160 is also connected to the through hole 152 of the organic protective layer 150, the through hole 142 of the inorganic protective layer 140, and the through hole of the gate dielectric layer 134.
  • the vertical projection of the through hole 162 of the pixel electrode 160 on the flexible substrate 110 at least partially overlaps with the vertical projection of the through hole 135 of the gate dielectric layer 134 on the flexible substrate 110.
  • the vertical projection of the through hole 162 of the pixel electrode 160 on the flexible substrate 110 at least partially overlaps with the vertical projection of the through hole 142 of the inorganic protective layer 140 on the flexible substrate 110.
  • the vertical projection of the through hole 162 of the pixel electrode 160 on the flexible substrate 110 at least partially overlaps with the vertical projection of the through hole 152 of the organic protective layer 150 on the flexible substrate 110.
  • the position of the vent GH can be selected on the flexible substrate 110 without passing through the positions of the gate 132, the channel layer 136, the source 138 and the drain 139, the through hole 162 of the pixel electrode 160
  • the vertical projection on the flexible substrate 110 does not overlap with the vertical projection of the gate 132, the channel layer 136, the source 138 and the drain 139 on the flexible substrate 110.
  • FIGS. 3A to 3D are cross-sectional views showing the manufacturing process of the active device array substrate 100 according to the second embodiment of the present invention, and the cross-sectional positions thereof are the same as those of Figs. 2A to 2J.
  • the present embodiment is different from the first embodiment in that, in the present embodiment, after the photo-sensitive release film 300 is photo-oxidized, an inorganic filler 170 is formed in the vent GH to protect the laminate exposed by the vent GH.
  • the manufacturer can irradiate the photosensitive release film 300 with the light source at this time, so that the adhesion between the photo-oxidized photosensitive release film 300 and the carrier 200 is lowered.
  • the oxygen can also contact the front surface of the photosensitive release film 300 through the vent hole GH and the flexible substrate 110, thereby sensitizing. The speed of photo-oxidation of the release film 300 becomes faster, reducing the time required for the process.
  • the manufacturer can form the inorganic filler 170 in the vent GH at this time. Specifically, the manufacturer may first form an inorganic filler 170 covering the organic protective layer 150 and the pixel electrode 160 and conformally covering the vent GH. Then, manufacture The inorganic filler 170 located outside the vent GH can be removed to form the inorganic filler 170 illustrated in FIG. 3C.
  • the inorganic filler 170 can be formed by a low-temperature process such as plasma-enhanced CVD (CVD) or low-temperature vacuum sputtering. plating.
  • the material of the inorganic filler 170 may be an inorganic dielectric material (for example: silicon nitride, silicon oxide, silicon oxynitride or any combination thereof) or a metal (for example: titanium, molybdenum, chromium, bismuth, aluminum, copper). , silver, gold or any combination or alloy of the above :).
  • the manner of removing the inorganic filler 170 located outside the vent GH may be, for example, an etching method.
  • the manufacturer can peel off the photosensitive release film 300 and the carrier 200 at this time to obtain the active device array substrate 100.
  • the active device array substrate 100 of FIG. 3D is mainly different from the first embodiment in that: the active device array substrate 100 of FIG. 3D further includes an inorganic filler 170 that at least conformally covers the inorganic The through hole 122 of the barrier layer 120 (shown in FIG. 3B).
  • the inorganic filler 170 conformally covers the entire vent GH, that is, the inorganic filler 170 conformally covers the through hole 122 of the inorganic barrier layer 120 (shown in FIG. 3B), the gate dielectric layer.
  • the through hole 135 of the 134 (shown in FIG. 3B ), the through hole 142 of the inorganic protective layer 140 (shown in FIG. 3B ), the through hole 152 of the organic protective layer 150 (shown in FIG. 3B ) and the pixel electrode 160 are penetrated. Hole 162 (shown in Figure 3B).
  • the inorganic filler 170 may only conformally cover a portion of the vent GH, for example, only conforming to the through-holes 122 of the inorganic barrier layer 120 (shown in FIG. 3B). Those having ordinary skill in the art to which the present invention pertains should flexibly select an embodiment of the inorganic filler 170 depending on actual needs.
  • FIGS. 4A to 4G are cross-sectional views showing the manufacturing process of the active device array substrate 100 according to the third embodiment of the present invention, and the cross-sectional positions of Figs. 2A to 2G are the same.
  • the present embodiment is different from the first embodiment in that: in the present embodiment, after the inorganic protective layer 140 is formed, the vent holes GH are formed, and the photosensitive release film 300 is photo-oxidized, and then the subsequent process is performed.
  • the manufacturer can form at least one vent GH at this time.
  • the stack above the flexible substrate 110 includes only the inorganic protective layer 140, the gate dielectric layer 134, and the inorganic barrier at the position where the vent holes GH are formed.
  • the barrier layer 120 therefore, the vent hole GH only needs to penetrate the inorganic protective layer 140, the gate dielectric layer 134, and the inorganic barrier layer 120, so that the flexible substrate 110 can be exposed.
  • the manufacturer can irradiate the photosensitive release film 300 with the light source at this time, so that the adhesion between the photo-oxidized photosensitive release film 300 and the carrier 200 is lowered.
  • the oxygen can also contact the front surface of the photosensitive release film 300 through the vent hole GH and the flexible substrate 110.
  • the photosensitive release film 300 is lightly oxidized at a faster rate, reducing the time required for the process.
  • the manufacturer can form an inorganic filler 170 in the vent GH at this time. Specifically, the manufacturer may first form an inorganic filler 170 that covers the inorganic protective layer 140 and conformally covers the vent GH. Then, the manufacturer can remove the inorganic filler 170 located outside the vent GH to form the inorganic filler 170 as shown in Fig. 4D.
  • the formation of the inorganic filler 170 can be selected from a low-temperature process such as plasma-enhanced chemical vapor deposition (Plasma-Enhanced CVD; PEC VD). ) or low temperature vacuum sputtering.
  • the material of the inorganic filler 170 may be an inorganic dielectric material (for example: silicon nitride, silicon oxide, silicon oxynitride or any combination thereof) or a metal (for example: titanium, molybdenum, chromium, bismuth, aluminum, copper). , silver, gold or any combination or alloy of the above :).
  • the manner of removing the inorganic filler 170 located outside the vent GH may be, for example, an etching method.
  • the manufacturer can form an organic protective layer 150 at this time, and the organic protective layer 150 covers the inorganic protective layer 140 and the inorganic filler 170. Since other processes, materials, and structural details associated with the organic protective layer 150 are the same as those of the first embodiment, the description thereof will not be repeated.
  • the manufacturer can form a pixel electrode 160 at this time.
  • the pixel electrode 160 is located on the active device 130 and electrically connected to the active device 130.
  • the manufacturer may first form a pixel electrode communication hole TH which penetrates the stack above the drain electrode 139 to expose the drain electrode 139.
  • the stack over the drain 139 includes the inorganic protective layer 140 and the organic protective layer 150, the pixel electrode vias TH will penetrate through the inorganic protective layer 140 and the organic protective layer 150, exposing the drain 139.
  • the manufacturer may form a third conductive layer covering the organic protective layer 150 and the pixel electrode communication hole TH, and then pattern the third conductive layer to form the pixel electrode 160.
  • the formed pixel electrode 160 is electrically connected to the drain electrode 139 through the pixel electrode communication hole TH. Since the photosensitive release film 300 has been photo-oxidized when the third conductive layer is formed, the third conductive layer can be formed in a low-temperature process, for example: plasma enhanced chemical vapor deposition
  • the material of the third conductive layer (or the pixel electrode 160) may be a transparent conductive material such as indium tin oxide, indium zinc oxide, zinc aluminum oxide or other conductive oxide or any combination thereof.
  • the material of the third conductive layer (or the pixel electrode 160) may be other opaque conductive materials such as titanium, molybdenum, chromium, ruthenium, aluminum, copper, silver, gold or any combination or alloy of the above.
  • the third conductive layer (or pixel electrode 160) may have a thickness of about 10 to 500 nm (nanometer; nanometer:).
  • the manner in which the pixel electrode communication hole TH and the patterned third conductive layer are formed may be, for example, lithography and etching.
  • the manufacturer can peel off the photosensitive release film 300 and the carrier 200 at this time to obtain the active device array substrate 100.
  • the active device array substrate 100 of FIG. 4G is mainly different from the first embodiment in that: the vent hole GH of FIG. 4G penetrates only the inorganic barrier layer 120, the gate dielectric layer 134, and the inorganic protective layer 140, but The organic protective layer 150 and the pixel electrode 160 are penetrated.
  • the active device array substrate 100 of FIG. 4G further includes an inorganic filler 170 that conformally covers the vent GH.
  • both the organic protective layer 150 and the pixel electrode 160 will cover above the vent GH. That is, the organic protective layer 150 and the pixel electrode 160 both cover the through hole 122 of the inorganic barrier layer 120, the through hole 135 of the gate dielectric layer 134, and the through hole 142 of the inorganic protective layer 140.
  • FIGS. 5A to 5E are cross-sectional views showing the manufacturing process of the active device array substrate 100 according to the fourth embodiment of the present invention, and the cross-sectional positions thereof are the same as those of Figs. 4A to 4B.
  • the present embodiment is different from the third embodiment in that: in the present embodiment, after the photo-sensitized photosensitive release film 300 is formed, the inorganic filler 170 is not formed in the vent GH, and at least a portion of the organic protective layer 150 is directly filled. In the vent GH.
  • the manufacturer can irradiate the photosensitive release film 300 with the light source at this time, so that the adhesion between the photo-oxidized photosensitive release film 300 and the carrier 200 is lowered.
  • the oxygen can also contact the positive surface of the photosensitive release film 300 through the vent hole GH and the flexible substrate 110. In this way, the speed of photo-oxidation of the photosensitive release film 300 is made faster, and the time required for the process is reduced.
  • the manufacturer can form an organic protective layer 150 at this time, the organic protective layer 150 covering the inorganic protective layer 140, and at least a portion of the organic protective layer 150 will be filled in the vent GH.
  • the material of the organic protective layer 150 described above may be any organic dielectric material such as an acrylic polymer.
  • the organic protective layer 150 may have a thickness of about 3 ⁇ m (micrometers;
  • the organic protective layer 150 may be formed by, for example, a spin coating method.
  • the manufacturer can form a pixel electrode 160 at this time.
  • the pixel electrode 160 is disposed on the active device 130 and electrically connected to the active device 130. Since other processes, materials, and structural details associated with this pixel electrode 160 are the same as in the third embodiment, the description thereof will not be repeated.
  • the manufacturer can peel off the photosensitive release film 300 and the carrier 200 at this time to obtain the active device array substrate 100.
  • the active device array substrate 100 of FIG. 5E is mainly different from the third embodiment in that: the vent hole GH of FIG. 5E has no inorganic filler 170, and at least a portion of the organic protective layer 150 is filled in the vent GH. in. That is, the through hole 122 of the inorganic barrier layer 120, the through hole 135 of the gate dielectric layer 134, and the through hole 142 of the inorganic protective layer 140 will have no inorganic filler 170, and at least a portion of the organic protective layer 150 will be filled. The through hole 122 of the inorganic barrier layer 120, the through hole 135 of the gate dielectric layer 134, and the through hole 142 of the inorganic protective layer 140.
  • FIG. 6A to 6E are cross-sectional views showing the manufacturing process of the active device array substrate 100 according to the fifth embodiment of the present invention, and the cross-sectional positions thereof are the same as those in Fig. 5A.
  • the present embodiment is different from the fourth embodiment in that, in the present embodiment, after the organic protective layer 150 and the pixel electrode 160 are formed, the photosensitive release film 300 is photooxidized.
  • the manufacturer can form an organic protective layer 150 at this time, the organic protective layer 150 covering the inorganic protective layer 140, and at least a portion of the organic protective layer 150 will be filled in the vent GH.
  • the material of the organic protective layer 150 may be an organic dielectric material capable of permeable to oxygen, for example, an acrylic polymer. Due to this organic protective layer 150 Other related process and structural details are the same as those of the fourth embodiment, and thus the description thereof will not be repeated.
  • FIG. 6C As shown, the manufacturer can form a pixel electrode 160 at this time. The pixel electrode 160 is located on the active device 130 and electrically connected to the active device 130.
  • the material of the pixel electrode 160 may be an oxygen-permeable conductive material such as indium tin oxide, indium zinc oxide, zinc aluminum oxide or other conductive oxide or any combination thereof. Since other process and structural details related to this pixel electrode 160 are the same as those of the fourth embodiment, the description thereof will not be repeated.
  • the manufacturer can irradiate the photosensitive release film 300 with the light source at this time, so that the adhesion between the photo-oxidized photosensitive release film 300 and the carrier 200 is lowered.
  • the material of the organic protective layer 150 and the pixel electrode 160 can be permeable to oxygen, oxygen can pass through the pixel electrode 160, the organic protective layer 150 and the flexible substrate 110, and contact the front surface of the photosensitive release film 300 to accelerate the sensitization. The speed at which the release film 300 is photooxidized.
  • the manufacturer can peel off the photosensitive release film 300 and the carrier 200 at this time to obtain the active device array substrate 100.
  • the structure of the active device array substrate 100 of Fig. 6E is substantially the same as that of the active device array substrate 100 of Fig. 5E.
  • FIG. 7A to 7E are cross-sectional views showing the manufacturing process of the active device array substrate 100 according to the sixth embodiment of the present invention, and the cross-sectional positions thereof are the same as those of Figs. 2A to 2H.
  • the difference between this embodiment and the first embodiment is that, in the present embodiment, after the organic protective layer 150 is formed, the pixel electrode communication hole TH and the vent hole GH are formed first, so that the subsequently formed pixel electrode 160 covers the vent hole GH.
  • the manufacturer can form the pixel electrode communication hole TH and the vent hole GH at this time.
  • the pixel electrode communication hole TH penetrates through the inorganic protective layer 140 and the organic protective layer 150 to expose the drain 139
  • the vent hole GH penetrates through the inorganic barrier layer 120, the gate dielectric layer 134, the inorganic protective layer 140, and the organic protective layer 150. , the soft substrate 110 is exposed.
  • the manner in which the pixel electrode communication hole TH and the vent hole GH are formed may be, for example, lithography and etching.
  • the manufacturer can irradiate the photosensitive release film 300 with the light source at this time, so that the adhesion between the photo-oxidized photosensitive release film 300 and the carrier 200 is lowered.
  • the oxygen can also contact the positive surface of the photosensitive release film 300 through the vent hole GH and the flexible substrate 110. In this way, the speed of photo-oxidation of the photosensitive release film 300 is made faster, and the time required for the process is reduced.
  • the manufacturer can form a pixel electrode 160 at this time.
  • the pixel electrode 160 is disposed on the active device 130 and electrically connected to the active device 130.
  • the manufacturer may form a third conductive layer covering the organic protective layer 15 (the X pixel electrode communication hole TH and the vent hole GH, and then pattern the third conductive layer to form the pixel electrode 160.
  • the formed pixel The electrode 160 will be electrically connected to the drain 139 through the pixel electrode communication hole TH and cover the vent GH.
  • the third conductive layer can be formed in a low-temperature process, for example: plasma enhanced chemical vapor deposition
  • the material of the third conductive layer (or the pixel electrode 160) may be a transparent conductive material such as indium tin oxide, indium zinc oxide, zinc aluminum oxide or other conductive oxide or any combination thereof.
  • the material of the third conductive layer (or the pixel electrode 160) may be other opaque conductive materials such as titanium, molybdenum, chromium, ruthenium, aluminum, copper, silver, gold or any combination or alloy of the above.
  • the third conductive layer (or pixel electrode 160) may have a thickness of about 10 to 500 nm (nanometer; nanometer:).
  • the manner in which the third conductive layer is patterned may be, for example, lithography and etching.
  • the manufacturer can peel off the photosensitive release film 300 and the carrier 200 at this time to obtain the active device array substrate 100.
  • the active element array substrate 100 of Fig. 7E is mainly different from the first embodiment in that the pixel electrode 160 of the present embodiment covers the vent hole GH. That is, the pixel electrode 160 of the present embodiment covers the through hole 152 of the organic protective layer 150, the through hole 142 of the inorganic protective layer 140, the through hole 135 of the gate dielectric layer 134, and the through hole 122 of the inorganic barrier layer 120.
  • the active device array substrate 100 provided by the above embodiments can be applied to various displays, including but not limited to: liquid crystal display (LCD), electro-optical display (EPD) and active matrix organic LED display
  • active device array substrate 100 (Active-Matrix Organic Light-Emitting Diode Display; AMOLED Display). It should be understood that the application range of the active device array substrate 100 is merely exemplary and is not intended to limit the present invention. Those skilled in the art to which the present invention pertains should flexibly select the application of the active device array substrate 100 according to actual needs. the way.
  • a carrier plate made of transparent glass which has a size of 320 mm (mm; millimeter) x 400 mm (mm; millimeter) x 0.7 mm (mm; mimmete! ⁇ is formed on the carrier board.
  • Photosensitive release film the photosensitive release film is made of poly(p-xylylene) or Parylene, and has a thickness of 300 nm (nano; nanometer).
  • a soft substrate is formed on the photosensitive release film.
  • the material of the flexible substrate is polyimide (Polyimide; PI) and the thickness is ⁇ ⁇ (micrometer).
  • the inorganic substrate is formed with a barrier layer on the soft substrate.
  • the material of the inorganic barrier layer is silicon nitride.
  • the difference between the comparative example and the embodiment is that the comparative example does not form a vent hole, and the embodiment is formed with a gas permeable through the inorganic barrier layer and exposing the soft substrate. Uniformly distributed in the inorganic barrier layer, the diameter of the vent hole is 5 ⁇ (micrometer), and the spacing between any two adjacent vent holes is 250 ⁇ m (micrometer;
  • FIG. 8 shows the test results of the comparative example
  • FIG. 9 illustrates the embodiment. Test results. It can be seen from Fig. 8 that after 10 minutes of ultraviolet light irradiation, the connection interface between the photosensitive release film of the comparative example and the flexible substrate is destroyed, and a force of about 950 gf is still required. In contrast, it can be seen from Fig. 9 that after 10 minutes of ultraviolet light irradiation, the connection interface between the photosensitive release film of the embodiment and the flexible substrate is destroyed, as long as the force of about 1 gf is obtained.
  • the utility model has the advantages that the vent hole is arranged on the active device array substrate, and the oxygen can contact the exposed portion of the photosensitive release film through the vent hole and the flexible substrate, and the front surface of the photosensitive release film can also be contacted through the vent hole and the soft substrate. , the speed of photo-oxidation of the photosensitive release film is made faster, and the time required for the process is reduced.

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Abstract

一种主动元件阵列基板（100）及其制造方法，主动元件阵列基板（100）包含软质基板（110）、无机阻障层（120）与至少一主动元件（130）。无机阻障层（120）覆盖软质基板（110）。无机阻障层（120）具有至少一贯穿孔（122）于其中，此贯穿孔（122）暴露出软质基板（110）。主动元件（130）位于无机阻障层（120）上。

Description

主动元件阵列基板及其制造方法
技术领域
本发明涉及一种主动元件阵列基板及其制造方法。
近来， 业界推出了一种以软质材料作为基板材质的显示器， 由于这种显示 器本身具有一定程度的可挠性， 因此可用来取代传统的纸张或广告看板。 但 是， 也因为基板的材质为软质材料， 因此为了方便工艺进行， 制造者大多需先 将基板固定在载板上， 以适用于现有的机台， 待制造完成后， 再将基板自载板 上剥离下来。
一般来说， 目前剥离基板与载板的方式有激光取下与光氧化两种。激光取 下的成本高昂， 且不易降低。 在光氧化技术中， 基板与载板之间具有感光离型 膜。 待制造完成后， 制造者会以紫外光照射感光离型膜， 借此光氧化感光离型 膜， 以降低基板与载板之间的粘着力。 然而， 由于一般基板上大多会覆盖一层 无机阻障层， 这层无机阻障层会阻障氧气接触感光离型膜， 使得氧气只能接触 感光离型膜暴露出来的侧面部分， 因此感光离型膜光氧化的速度极慢， 不利于 实际应用。 发明公开
本发明的一技术态样在于提供一种主动元件阵列基板用以解决或改善以 上现有技术所提到的问题。
根据本发明一实施方式， 一种主动元件阵列基板包含软质基板、 无机阻障 层与至少一主动元件。 无机阻障层覆盖软质基板。 上述的无机阻障层具有至少 一贯穿孔于其中， 此贯穿孔暴露出软质基板。 主动元件位于无机阻障层上。
在本发明一或多个实施方式中， 上述的主动元件可包含栅极、 栅介电层、 通道层、 源极与漏极。 栅极位于无机阻障层上。 栅介电层至少覆盖栅极。 通道 层位于栅极上方的栅介电层上。 源极与漏极分别位于通道层的两侧。
在本发明一或多个实施方式中， 上述的栅介电层覆盖栅极与无机阻障层， 且此栅介电层具有至少一贯穿孔于其中， 其中栅介电层的贯穿孔连通于无机阻 障层的贯穿孔。
在本发明一或多个实施方式中， 上述的无机阻障层的贯穿孔与栅极之间具 有一间距。
在本发明一或多个实施方式中， 上述的主动元件阵列基板更可包含无机保 护层、 有机保护层与像素电极。 无机保护层覆盖该主动元件， 且此无机保护层 具有至少一贯穿孔于其中， 其中无机保护层的贯穿孔与栅介电层的贯穿孔以及 无机阻障层的贯穿孔至少部分重叠。 有机保护层覆盖于无机保护层。 像素电极 位于有机保护层上， 并电性连接主动元件。
在本发明一或多个实施方式中， 上述的主动元件阵列基板更可包含无机保 护层， 此无机保护层覆盖主动元件， 且具有至少一贯穿孔于其中， 其中无机保 护层的贯穿孔与无机阻障层的贯穿孔至少部分重叠。
在本发明一或多个实施方式中， 上述的主动元件阵列基板更可包含有机保 护层， 此有机保护层覆盖于主动元件。
在本发明一或多个实施方式中， 上述的有机保护层可具有至少一贯穿孔于 其中， 其中有机保护层的贯穿孔与无机阻障层的贯穿孔至少部分重叠。
在本发明一或多个实施方式中， 至少部分的有机保护层可填充于无机阻障 层的贯穿孔中。
在本发明一或多个实施方式中， 上述的主动元件阵列基板更可包含像素电 极， 此像素电极位于主动元件上， 并电性连接主动元件。
在本发明一或多个实施方式中， 上述的像素电极可具有至少一贯穿孔于其 中， 其中像素电极的贯穿孔与无机阻障层的贯穿孔至少部分重叠。
在本发明一或多个实施方式中， 上述的像素电极可覆盖无机阻障层的贯穿 孔。
在本发明一或多个实施方式中， 上述的主动元件阵列基板更可包含至少一 无机填充材， 此无机填充材共形地覆盖无机阻障层的贯穿孔。
在本发明一或多个实施方式中， 上述的主动元件阵列基板更可包含一感光 离型膜， 此感光离型膜设置于软质基板相反于无机阻障层的一表面。
本发明的另一技术态样是提供一种主动元件阵列基板的制造方法。
根据本发明另一实施方式， 一种主动元件阵列基板的制造方法包含下列歩 骤 (应了解到， 在本实施方式中所提及的歩骤， 除特别叙明其顺序者外， 均可 依实际需要调整其前后顺序， 甚至可同时或部分同时执行。 ：)：
(1) 以感光离型膜将软质基板粘着于载板上。
(2) 形成无机阻障层覆盖软质基板。
(3)在无机阻障层上形成至少一主动元件。
(4) 于无机阻障层中形成至少一贯穿孔， 以暴露出软质基板。
(5) 以光源照射感光离型膜。
(6) 剥离感光离型膜与载板。
在本发明一或多个实施方式中， 上述的歩骤 (3)可包含下列子歩骤： (3.1) 于无机阻障层上形成栅极。
(3.2) 形成栅介电层至少覆盖栅极。
(3.3) 于栅极上方的栅介电层上形成通道层。
(3.4) 于通道层的两侧形成源极与漏极。
在本发明一或多个实施方式中， 上述的主动元件阵列基板的制造方法更可 包含： 形成贯穿孔于栅介电层中， 其中栅介电层的贯穿孔与无机阻障层的贯穿 孔构成连通的通气孔， 以暴露出软质基板。
在本发明一或多个实施方式中， 上述的主动元件阵列基板的制造方法更可 包含： 形成贯穿孔于栅介电层中。 形成无机保护层， 此无机保护层覆盖主动元 件， 且此无机保护层具有至少一贯穿孔于其中， 其中无机保护层的贯穿孔连通 于栅介电层的贯穿孔以及无机阻障层的贯穿孔， 以构成通气孔。 形成有机保护 层于无机保护层上。 形成像素电极于有机保护层上， 并电性连接主动元件。
在本发明一或多个实施方式中， 上述的主动元件阵列基板的制造方法更可 包含： 形成无机保护层覆盖主动元件， 其中无机保护层具有至少一贯穿孔于其 中， 此无机保护层的贯穿孔与无机阻障层的贯穿孔构成连通的通气孔， 以暴露 出软质基板。
在本发明一或多个实施方式中， 上述的主动元件阵列基板的制造方法更可 包含： 于无机阻障层的贯穿孔中形成无机填充材。 國麵兑日月
图 1绘示依照本发明第一实施方式的主动元件阵列基板的俯视图； 图 2A〜2L绘示图 1的主动元件阵列基板的制造流程剖面图， 其剖面位置 如图 1的线段 i-i所示；
图 3A〜3D绘示依照本发明第二实施方式的主动元件阵列基板的制造流 程剖面图， 其剖面位置与图 2A〜2J相同；
图 4A〜4G绘示依照本发明第三实施方式的主动元件阵列基板的制造流 程剖面图， 其剖面位置与图 2A〜2G相同；
图 5A〜5E绘示依照本发明第四实施方式的主动元件阵列基板的制造流程 剖面图， 其剖面位置与图 4A〜4B相同；
图 6A〜6E绘示依照本发明第五实施方式的主动元件阵列基板的制造流程 剖面图， 其剖面位置与图 5A相同；
图 7A〜7E绘示依照本发明第六实施方式的主动元件阵列基板的制造流程 剖面图， 其剖面位置与图 2A〜2H相同；
图 8绘示本发明的比较例的荷重对位移曲线；
图 9绘示本发明的实施例的荷重对位移曲线。 其中， 附图标记
100： 主动元件阵列基 110
120 无机阻障层 122
130 主动元件 132
134 135
136 138 源极
139 140 无机保护层
142 贯穿孔 150 有机保护层
152 贯穿孔 160
162 贯穿孔 170 无机填充材
200 300 感光离型膜
TH: 像素 GH: 通气孔
1-1： 线段 G1 : 间距
G2: 间距 魏本 ^垂; ¾ 以下将以附图公开本发明的多个实施方式， 为明确说明起见， 许多实务上 的细节将在以下叙述中一并说明。 然而， 应了解到， 这些实务上的细节不应用 以限制本发明。 也就是说， 在本发明部分实施方式中， 这些实务上的细节是非 必要的。 此外， 为简化附图起见， 一些公知惯用的结构与元件在附图中将以简 单示意的方式绘示之。
图 1绘示依照本发明第一实施方式的主动元件阵列基板 100的俯视图。图 2A〜2L绘示图 1的主动元件阵列基板 100的制造流程剖面图， 其剖面位置如 图 1的线段 I-I所示。 应了解到， 图 1的主动元件阵列基板 100的俯视设计仅 用以说明， 并不限于上述的附图， 本发明所属技术领域中普通技术人员， 可依 照实际需求适当变化设计。
请先参照图 2A。 如图所示， 制造者在此时可先以感光离型膜 300将软质 基板 110粘着于载板 200上， 以利进行后续工艺。 具体而言， 制造者可先以化 学气相沉积法将感光离型膜 300形成于载板 200上然后再以旋涂法将软质基 板 110形成于感光离型膜 300上。 当然， 如果条件许可， 制造者亦可选择以对 贴的方式通过感光离型膜 300将软质基板 110粘着于载板 200上。
在本实施方式中， 上述的载板 200的材质可为任何硬质材料， 例如透明玻 璃。 载板 200的厚度可为约 0.7 mm (毫米； millimeter 感光离型膜 300的材 质可为对紫外光敏感或对特定波段的光线敏感的有机材料， 例如聚对二甲苯 (Poly(p-xylylene)或 Parylene)。 感光离型膜 300的厚度可为约 300 nm (纳米； nanometer)。 软质基板 110的材质可为任何具有可挠性的材料， 例如聚酰亚胺 (Polyimide; PI)、 聚对苯二甲酸乙二酯 (Polyethylene terephthalate; PET)、 聚 2， 6-萘二酸乙二醇酯 (Polyethylene Naphthalate; PEN)或上述的任意组合。 软 质基板 110的厚度可为约 10〜100 μιη(;微米； micrometer；)。
接着请参照图 2B。 如图所示， 制造者在此时可形成无机阻障层 120， 此 无机阻障层 120覆盖软质基板 110。 上述的无机阻障层 120的材质可为任何能 够阻隔水氧的无机介电材料， 例如： 氮化硅、 氧化硅、 氮氧化硅或上述的任意 组合。 无机阻障层 120的厚度可为约 10〜1000 nm (纳米； nanometer：)。 无 机阻障层 120的形成方式可为例如化学气相沉积法。
接着请参照图 2C。 如图所示， 制造者在此时可在无机阻障层 120上形成 栅极 132。 具体而言， 制造者可先在无机阻障层 120上形成第一导电层， 并随 之图案化此第一导电层， 以形成栅极 132。
在本实施方式中， 上述的第一导电层 (或者说， 栅极 132)的材质可为钛、 钼、 铬、 铱、 铝、 铜、 银、 金或上述的任意组合或合金。 第一导电层 (或者说， 栅极 132)的厚度可为约 10〜500 nm(纳米； nanometer：)。 第一导电层的形成方 式可为物理气相沉积法， 例如溅镀法。 图案化第一导电层的方式可为例如微影 及蚀刻法。
接着请参照图 2D。 如图所示， 制造者在此时可形成栅介电层 134， 此栅 介电层 134覆盖栅极 132与无机阻障层 120。 上述的栅介电层 134的材质可为 任何介电材料， 例如： 氮化硅、 氧化硅、 氮氧化硅或上述的任意组合。 栅介电 层 134的厚度可为约 100〜1000 nm (纳米； nanometer；)。 栅介电层 134的形成 方式可为例如化学气相沉积法。
接着请参照图 2E。 如图所示， 制造者在此时可于栅极 132上方的栅介电 层 134上形成通道层 136。 具体而言， 制造者可先在栅介电层 134上形成半导 体层， 并随之图案化此半导体层， 以形成通道层 136。
上述的半导体层 (或者说， 通道层 136)的材质可为任何半导体材料， 例如： 非晶硅、 复晶硅、 单晶硅、 氧化物半导体 (oxide semiconductor)或上述的任意组 合。 半导体层 (或者说， 通道层 136)的厚度可为约 10〜500 nm (纳米； nanometer^ 半导体层的形成方式可为例如化学气相沉积法。 图案化半导体层 的方式可为例如微影及蚀刻法。
接着请参照图 2F。 如图所示， 制造者在此时可于通道层 136的两侧形成 源极 138与漏极 139。 具体而言， 制造者可先在通道层 136及栅介电层 134上 形成第二导电层， 并随之图案化此第二导电层， 以形成源极 138与漏极 139。
在本实施方式中， 上述的第二导电层 (或者说， 源极 138与漏极 139)的材 质可为钛、 钼、 铬、 铱、 铝、 铜、 银、 金或上述的任意组合或合金。 第二导电 层 (；或者说， 源极 138与漏极 139)的厚度可为约 10〜500 nm (；纳米；
nanomete!^ 第二导电层的形成方式可为物理气相沉积法， 例如溅镀法。 图案 化第二导电层的方式可为例如微影及蚀刻法。
在此歩骤完成后， 栅极 132、 栅介电层 134、 通道层 136、 源极 138与漏 极 139将共同构成主动元件 130。 应了解到， 本实施方式虽然将主动元件 130 绘示为底栅型薄膜晶体管， 但此并不限制本发明， 实际上主动元件 130亦可为 其他形式的主动元件， 例如顶栅型薄膜晶体管， 本发明所属技术领域中普通技 术人员， 应视实际需要， 弹性选择主动元件 130的实施方式。
接着请参照图 2G。 如图所示， 制造者在此时可形成无机保护层 140， 此 无机保护层 140覆盖主动元件 130。 上述的无机保护层 140的材质可为任何无 机介电材料， 例如： 氮化硅、 氧化硅、 氮氧化硅或上述的任意组合。 无机保护 层 140的厚度可为约 100〜1000 nm (纳米； nanometer：)。 无机保护层 140的形 成方式可为例如化学气相沉积法。
接着请参照图 2H。 如图所示， 制造者在此时可形成有机保护层 150， 此 有机保护层 150覆盖于主动元件 130。 在本实施方式中， 有机保护层 150覆盖 无机保护层 140， 但此并不限制本发明， 若主动元件 130或无机保护层 140上 方具有其他叠层， 例如其他介电层或阻障层， 有机保护层 150亦可覆盖这些叠 层。 亦即， 有机保护层 150可直接或间接覆盖无机保护层 140。
上述的有机保护层 150的材质可为任何有机介电材料， 例如： 丙烯酸类聚 合物 (acrylic polymer)。 有机保护层 150的厚度可为约 3 μιη (微米；
micrometer：)。 有机保护层 150的形成方式可为例如旋涂法。
接着请参照图 21。 如图所示， 制造者在此时可形成像素电极 160， 此像素 电极 160电性连接主动元件 130。 具体而言， 制造者可先形成像素电极连通孔 TH, 此像素电极连通孔 TH贯穿漏极 139上方的叠层， 让漏极 139暴露出来。 在本实施方式中， 由于漏极 139上方的叠层包含无机保护层 140与有机保护层 150， 因此像素电极连通孔 TH将贯穿无机保护层 140与有机保护层 150， 让漏 极 139暴露出来。
然后， 制造者可形成第三导电层覆盖有机保护层 150与像素电极连通孔 TH, 并随之图案化此第三导电层， 以形成像素电极 160。 所形成的像素电极 160将通过像素电极连通孔 TH， 与漏极 139电性连接。
上述的第三导电层 (或者说， 像素电极 160)的材质可为任何导电材料。 在 本实施方式中， 第三导电层 (或者说， 像素电极 160)的材质可为透明导电材料， 例如： 氧化铟锡、 氧化铟锌、 氧化锌铝或其他导电氧化物或上述任意的组合。 或者， 第三导电层 (或者说， 像素电极 160)的材质亦可为其他不透明的导电材 料， 例如： 钛、 钼、 铬、 铱、 铝、 铜、 银、 金或上述的任意组合或合金。 第三 导电层 (；或者说， 像素电极 160)的厚度可为约 10〜500 nm(纳米； nanometer：)。 第三导电层的形成方式可为例如物理气相沉积法或化学气相沉积法。形成像素 电极连通孔 TH及图案化第三导电层的方式可为例如微影及蚀刻法。
接着请参照图 2J。 如图所示， 制造者在此时可形成至少一通气孔 GH， 此 通气孔 GH至少贯穿无机阻障层 120， 以暴露出软质基板 110。 具体而言， 在 本实施方式中， 通气孔 GH的位置可选择主动元件 130周边的位置， 亦即在软 质基板 110上不需要穿过栅极 132、通道层 源极 138与漏极 139的位置。 至于通气孔 GH所需贯穿的叠层则视该位置上软质基板 110上方的叠层而定。
在本实施方式中， 通气孔 GH将贯穿像素电极 160、 有机保护层 150、 无 机保护层 140、栅介电层 134与无机阻障层 120， 使得软质基板 110暴露出来。 亦即， 本歩骤将在像素电极 160、 有机保护层 150、 无机保护层 140、 栅介电 层 134与无机阻障层 120中分别形成贯穿孔 162、 152、 142、 135、 122， 且这 些贯穿孔 162、 152、 142、 135、 122将构成连通的通气孔 GH。 形成通气孔 GH的方式可为例如微影及蚀刻法。
接着请参照图 2K。 如图所示， 制造者在此时可以光源照射感光离型膜 300， 使得光氧化后的感光离型膜 300与载板 200之间的粘着力降低。 具体而 言， 制造者可将光源架设于载板 200相对于感光离型膜 300的背侧， 使得光源 所发出的光线穿过载板 200而照射感光离型膜 300。 在传统工艺中， 由于无机 阻障层不能透氧而且也不存在通气孔， 因此纵使软质基板的材质能够透氧， 氧 气也会因为无法透过无机阻障层， 而无法接触感光离型膜邻接软质基板的正 面， 而只能接触感光离型膜暴露出来的侧面部分。 但在本实施方式中， 由于通 气孔 GH的存在， 因此氧气除了能够接触感光离型膜 300暴露出来的侧面部分 夕卜， 也可以通过通气孔 GH与软质基板 110而接触感光离型膜 300的正面， 使 得感光离型膜 300光氧化的速度变快， 减少工艺所需要的时间。
上述的光源可为紫外光灯， 例如： 长波紫外光灯 (Ultraviolet A Light; UVA Light), 中波紫外光灯 (Ultraviolet B Light; UVB Light)或短波紫外光灯
(Ultraviolet C Light; UVC Light), 或其他能够让感光离型膜 300光氧化的光 源。此外， 若将光源架设于载板 200的背侧以背曝的方式照射感光离型膜 300， 则载板 200的材质可选择为能够透过光源所发出的光线的材料， 例如： 透明玻 璃。
接着请参照图 2L。 如图所示， 制造者在此时可剥离感光离型膜 300与载 板 200， 以获得主动元件阵列基板 100。 从结构上来看， 图 2L的主动元件阵 列基板 100包含软质基板 110、 无机阻障层 120与至少一主动元件 130。 无机 阻障层 120覆盖软质基板 110。 上述的无机阻障层 120具有至少一贯穿孔 122 于其中， 且此贯穿孔 122暴露出软质基板 110。 主动元件 130位于无机阻障层 120上。 此外， 主动元件阵列基板 100更包含感光离型膜 300， 此感光离型膜 300设置于软质基板 110上， 且设置于相反于无机阻障层 120的软质基板 110 的表面上。
在图 2L中， 主动元件 130可包含栅极 132、 栅介电层 134、 通道层 136、 源极 138与漏极 139。 栅极 132位于无机阻障层 120上。 栅介电层 134覆盖栅 极 132与无机阻障层 120。 栅介电层 134具有至少一贯穿孔 135于其中， 其中 栅介电层 134的贯穿孔 135连通于无机阻障层 120的贯穿孔 122。 亦即， 栅介 电层 134的贯穿孔 135在软质基板 110上的垂直投影， 与无机阻障层 120的贯 穿孔 122在软质基板 110上的垂直投影至少部分重叠。 通道层 136位于栅极 132上方的栅介电层 134上源极 138与漏极 139分别位于通道层 136的两個] ^ 在本实施方式中， 无机阻障层 120的贯穿孔 122为通气孔 GH的一部分， 且由于通气孔 GH的位置可选择在软质基板 110上不需要穿过栅极 132、 通道 层 136 源极 138与漏极 139的位置 因此上述的无机阻障层 120的贯穿孔 122 与栅极 132之间具有一间距 (如间距 G1所标示：)。更具体地说， 无机阻障层 120 的贯穿孔 122在软质基板 110上的垂直投影， 与栅极 132、 通道层 136、 源极 138与漏极 139在软质基板 110上的垂直投影均不重叠。
此外， 栅介电层 134的贯穿孔 135亦为通气孔 GH的一部分， 且由于通气 孔 GH的位置可选择在软质基板 110上不需要穿过栅极 132、 通道层 136、 源 极 138与漏极 139的位 S 因此栅介电层 134的贯穿孔 135与栅极 132之间亦 具有一间距 (如间距 G1所标示：)。 更具体地说， 栅介电层 134的贯穿孔 135在 软质基板 110上的垂直投影， 与栅极 132、 通道层 136、 源极 138与漏极 139 在软质基板 110上的垂直投影均不重叠。
在图 2L中， 主动元件阵列基板 100更可包含无机保护层 140， 此无机保 护层 140覆盖主动元件 13G且具有至少一贯穿孔 142于其中。无机保护层 140 的贯穿孔 142亦为通气孔 GH的一部分， 因此无机保护层 140的贯穿孔 142亦 连通于栅介电层 134的贯穿孔 135与无机阻障层 120的贯穿孔 122。 或者说， 无机保护层 140的贯穿孔 142在软质基板 110上的垂直投影， 与无机阻障层 120的贯穿孔 122在软质基板 110上的垂直投影至少部分重叠。 此外， 无机保 护层 140的贯穿孔 142在软质基板 110上的垂直投影， 与栅介电层 134的贯穿 孔 135在软质基板 110上的垂直投影亦至少部分重叠。
在本实施方式中， 由于通气孔 GH的位置可选择在软质基板 110上不需要 穿过栅极 132、 通道层 136、 源极 138与漏极 139的位置， 因此上述的无机保 护层 140的贯穿孔 142与主动元件 130的漏极 139之间具有一间距 (如间距 G2 所标示)。 更具体地说， 无机保护层 140的贯穿孔 142在软质基板 110上的垂 直投影， 与栅极 132、 通道层 136、 源极 138与漏极 139在软质基板 110上的 垂直投影均不重叠。
在图 2L中， 主动元件阵列基板 100更可包含有机保护层 150， 此有机保 护层 150覆盖于主动元件 130。 在本实施方式中， 有机保护层 150覆盖无机保 护层 140， 且具有至少一贯穿孔 152于其中。 有机保护层 150的贯穿孔 152亦 为通气孔 GH的一部分， 因此有机保护层 150的贯穿孔 152亦连通于无机保护 层 140的贯穿孔 142、 栅介电层 134的贯穿孔 135与无机阻障层 120的贯穿孔 122。 或者说， 有机保护层 150的贯穿孔 152在软质基板 110上的垂直投影， 与无机阻障层 120的贯穿孔 122在软质基板 110上的垂直投影至少部分重叠。 此外， 有机保护层 150的贯穿孔 152在软质基板 110上的垂直投影， 与栅介电 层 134的贯穿孔 135在软质基板 110上的垂直投影至少部分重叠。 再者， 有机 保护层 150的贯穿孔 152在软质基板 110上的垂直投影， 与无机保护层 140的 贯穿孔 142在软质基板 110上的垂直投影至少部分重叠。
在本实施方式中， 由于通气孔 GH的位置可选择在软质基板 110上不需要 穿过栅极 132、 通道层 136、 源极 138与漏极 139的位置， 因此上述的有机保 护层 150的贯穿孔 152与主动元件 130的漏极 139之间具有一间距 (如间距 G2 所标示)。 更具体地说， 有机保护层 150的贯穿孔 152在软质基板 110上的垂 直投影， 与栅极 132、 通道层 136、 源极 138与漏极 139在软质基板 110上的 垂直投影均不重叠。
在图 2L中， 主动元件阵列基板 100更可包含像素电极 160， 此像素电极 160位于主动元件 130上， 并电性连接主动元件 130。 在本实施方式中， 像素 电极 160位于有机保护层 150上， 且具有至少一贯穿孔 162于其中。像素电极 160的贯穿孔 162亦为通气孔 GH的一部分， 因此像素电极 160的贯穿孔 162 亦连通于有机保护层 150的贯穿孔 152、 无机保护层 140的贯穿孔 142、 栅介 电层 134的贯穿孔 135与无机阻障层 120的贯穿孔 122ο或者说像素电极 160 的贯穿孔 162在软质基板 110上的垂直投影， 与无机阻障层 120的贯穿孔 122 在软质基板 110上的垂直投影至少部分重叠。 此外， 像素电极 160的贯穿孔 162在软质基板 110上的垂直投影， 与栅介电层 134的贯穿孔 135在软质基板 110上的垂直投影至少部分重叠。 再者， 像素电极 160的贯穿孔 162在软质基 板 110上的垂直投影， 与无机保护层 140的贯穿孔 142在软质基板 110上的垂 直投影至少部分重叠。 另外， 像素电极 160的贯穿孔 162在软质基板 110上的 垂直投影， 与有机保护层 150的贯穿孔 152在软质基板 110上的垂直投影至少 部分重叠。
在本实施方式中， 由于通气孔 GH的位置可选择在软质基板 110上不需要 穿过栅极 132、 通道层 136、 源极 138与漏极 139的位置， 因此像素电极 160 的贯穿孔 162在软质基板 110上的垂直投影， 与栅极 132、 通道层 136、 源极 138与漏极 139在软质基板 110上的垂直投影均不重叠。
图 3A〜3D绘示依照本发明第二实施方式的主动元件阵列基板 100的制造 流程剖面图， 其剖面位置与图 2A〜2J相同。 本实施方式与第一实施方式的不 同点在于： 本实施方式在光氧化感光离型膜 300后， 会在通气孔 GH内形成无 机填充材 170， 以保护被通气孔 GH暴露出来的叠层。
请先参照图 3A。 如图所示， 制造者在此时可先进行如图 2A〜2J所绘示的 工艺。 由于这些工艺、 材料与结构细节， 均与第一实施方式相同， 因此不再重 复赘述之。
接着请参照图 3B。 如图所示， 制造者在此时可以光源照射感光离型膜 300， 使得光氧化后的感光离型膜 300与载板 200之间的粘着力降低。 同样地， 由于通气孔 GH的存在， 因此氧气除了能够接触感光离型膜 300暴露出来的侧 面部分外， 也可以通过通气孔 GH与软质基板 110而接触感光离型膜 300的正 面， 使得感光离型膜 300光氧化的速度变快， 减少工艺所需要的时间。
接着请参照图 3C。 如图所示， 制造者在此时可于通气孔 GH中形成无机 填充材 170。 具体而言， 制造者可先形成无机填充材 170， 此无机填充材 170 覆盖有机保护层 150与像素电极 160， 并共形地覆盖通气孔 GH。 然后， 制造 者可去除位于通气孔 GH外的无机填充材 170， 以形成图 3C所绘示的无机填 充材 170。
由于在形成无机填充材 170时， 感光离型膜 300已经光氧化， 因此无机填 充材 170的形成方式可选择低温工艺， 例如： 等离子增强化学气相沉积 法（Plasma-Enhanced CVD¾ PECVD)或低温真空溅镀。上述的无机填充材 170 的材质可为无机介电材料 (例如： 氮化硅、 氧化硅、 氮氧化硅或上述的任意组 合：)或金属 (例如： 钛、 钼、 铬、 铱、 铝、 铜、 银、 金或上述的任意组合或合金：)。 去除位于通气孔 GH外的无机填充材 170的方式可为例如蚀刻法。
接着请参照图 3D。 如图所示， 制造者在此时可剥离感光离型膜 300与载 板 200， 以获得主动元件阵列基板 100。 从结构上来看， 图 3D的主动元件阵 列基板 100与第一实施方式主要的不同点在于： 图 3D的主动元件阵列基板 100 更包含无机填充材 170， 此无机填充材 170至少共形地覆盖无机阻障层 120的 贯穿孔 122(绘示于图 3B)。 在本实施方式中， 无机填充材 170共形地覆盖整个 通气孔 GH亦即，无机填充材 170共形地覆盖无机阻障层 120的贯穿孔 122(绘 示于图 3B)、 栅介电层 134的贯穿孔 135(绘示于图 3B)、 无机保护层 140的贯 穿孔 142(绘示于图 3B)、 有机保护层 150的贯穿孔 152(绘示于图 3B)与像素电 极 160的贯穿孔 162(绘示于图 3B)。此外， 在部分实施方式中， 无机填充材 170 亦可仅共形地覆盖部分的通气孔 GH, 例如仅共形地覆盖无机阻障层 120的贯 穿孔 122(绘示于图 3B)。 本发明所属技术领域中具有通常知识者， 应视实际需 要， 弹性选择无机填充材 170的实施方式。
图 4A〜4G绘示依照本发明第三实施方式的主动元件阵列基板 100的制造 流程剖面图， 其剖面位置图 2A〜2G相同。 本实施方式与第一实施方式的不同 点在于： 本实施方式在形成无机保护层 140后就形成通气孔 GH, 并随之光氧 化感光离型膜 300， 然后再进行后续制程。
请先参照图 4A。 如图所示， 制造者在此时可先进行如图 2A〜2G所绘示 的制程。 由于这些工艺、 材料与结构细节， 均与第一实施方式相同， 因此不再 重复赘述之。
接着请参照图 4B。 如图所示， 制造者在此时可形成至少一通气孔 GH。 与第一实施方式不同的是， 在本实施方式中， 由于在通气孔 GH形成的位置 上， 软质基板 110上方的叠层仅包含无机保护层 140、 栅介电层 134与无机阻 障层 120， 因此通气孔 GH只需要贯穿无机保护层 140、 栅介电层 134与无机 阻障层 120， 就能够将软质基板 110暴露出来。
接着请参照图 4C。 如图所示， 制造者在此时可以光源照射感光离型膜 300， 使得光氧化后的感光离型膜 300与载板 200之间的粘着力降低。 同样地， 由于通气孔 GH的存在， 因此氧气除了能够接触感光离型膜 300暴露出来的侧 面部分外， 也可以透过通气孔 GH与软质基板 110而接触感光离型膜 300的正 面， 使得感光离型膜 300光氧化的速度变快， 减少工艺所需要的时间。
接着请参照图 4D。 如图所示， 制造者在此时可在通气孔 GH中形成无机 填充材 170。 具体而言， 制造者可先形成无机填充材 170， 此无机填充材 170 覆盖无机保护层 140， 并共形地覆盖通气孔 GH。 然后， 制造者可去除位于通 气孔 GH外的无机填充材 170， 以形成图 4D所绘示的无机填充材 170。
同样地， 由于在形成无机填充材 170时， 感光离型膜 300已经光氧化， 因 此无机填充材 170的形成方式可选择低温工艺， 例如： 等离子增强化学气相沉 积法（Plasma-Enhanced CVD; PEC VD)或低温真空溅镀。 上述的无机填充材 170的材质可为无机介电材料 (例如： 氮化硅、 氧化硅、 氮氧化硅或上述的任意 组合：)或金属 (例如： 钛、 钼、 铬、 铱、 铝、 铜、 银、 金或上述的任意组合或合 金：)。 去除位于通气孔 GH外的无机填充材 170的方式可为例如蚀刻法。
接着请参照图 4E。 如图所示， 制造者在此时可形成有机保护层 150， 此 有机保护层 150覆盖无机保护层 140与无机填充材 170。 由于与此有机保护层 150相关的其他工艺、 材料与结构细节， 均与第一实施方式相同， 因此不再重 复赘述之。
接着请参照图 4F。 如图所示， 制造者在此时可形成像素电极 160， 此像素 电极 160位于主动元件 130上， 并电性连接主动元件 130。 具体而言， 制造者 可先形成像素电极连通孔 TH, 此像素电极连通孔 TH贯穿漏极 139上方的叠 层， 让漏极 139暴露出来。 在本实施方式中， 由于漏极 139上方的叠层包含无 机保护层 140与有机保护层 150， 因此像素电极连通孔 TH将贯穿无机保护层 140与有机保护层 150， 让漏极 139暴露出来。
然后， 制造者可形成第三导电层覆盖有机保护层 150与像素电极连通孔 TH, 并随之图案化此第三导电层， 以形成像素电极 160。 所形成的像素电极 160将通过像素电极连通孔 TH， 与漏极 139电性连接。 由于在形成第三导电层时， 感光离型膜 300已经光氧化， 因此第三导电层 的形成方式可选择低温工艺， 例如： 等离子增强化学气相沉积
法（Plasma-Enhanced CVD; PECVD), 低温真空溅镀。 上述的第三导电层 (或 者说， 像素电极 160)的材质可为透明导电材料， 例如： 氧化铟锡、 氧化铟锌、 氧化锌铝或其他导电氧化物或上述任意的组合。 或者， 第三导电层 (或者说， 像素电极 160)的材质亦可为其他不透明的导电材料， 例如： 钛、 钼、 铬、 铱、 铝、 铜、 银、 金或上述的任意组合或合金。 第三导电层 (或者说， 像素电极 160) 的厚度可为约 10〜500 nm(纳米； nanometer：)。 形成像素电极连通孔 TH及图 案化第三导电层的方式可为例如微影及蚀刻法。
接着请参照图 4G。 如图所示， 制造者在此时可剥离感光离型膜 300与载 板 200， 以获得主动元件阵列基板 100。 从结构上来看， 图 4G的主动元件阵 列基板 100与第一实施方式主要的不同在于： 图 4G的通气孔 GH仅贯穿无机 阻障层 120、 栅介电层 134与无机保护层 140， 而未贯穿有机保护层 150与像 素电极 160。 此外， 图 4G的主动元件阵列基板 100更包含无机填充材 170， 此无机填充材 170共形地覆盖通气孔 GH。
由于无机填充材 170共形地覆盖通气孔 GH， 因此有机保护层 150与像素 电极 160将均覆盖通气孔 GH的上方。 亦即， 有机保护层 150与像素电极 160 将均覆盖无机阻障层 120的贯穿孔 122、 栅介电层 134的贯穿孔 135与无机保 护层 140的贯穿孔 142的上方。
图 5A〜5E绘示依照本发明第四实施方式的主动元件阵列基板 100的制造 流程剖面图， 其剖面位置与图 4A〜4B相同。 本实施方式与第三实施方式的不 同点在于： 本实施方式在光氧化感光离型膜 300后， 不会在通气孔 GH中形成 无机填充材 170， 而直接将至少部分的有机保护层 150填充于通气孔 GH中。
请先参照图 5A。 如图所示， 制造者在此时可先进行如图 4A〜4B所绘示 的工艺。 由于这些工艺、 材料与结构细节， 均与第三实施方式相同， 因此不再 重复赘述之。
接着请参照图 5B。 如图所示， 制造者在此时可以光源照射感光离型膜 300， 使得光氧化后的感光离型膜 300与载板 200之间的粘着力降低。 同样地， 由于通气孔 GH的存在， 因此氧气除了能够接触感光离型膜 300暴露出来的侧 面部分外， 也可以透过通气孔 GH与软质基板 110而接触感光离型膜 300的正 面， 使得感光离型膜 300光氧化的速度变快， 减少制程所需要的时间。
接着请参照图 5C。 如图所示， 制造者在此时可形成有机保护层 150， 此 有机保护层 150覆盖无机保护层 140， 且至少部分的有机保护层 150将填充于 通气孔 GH中。
上述的有机保护层 150的材质可为任何有机介电材料， 例如： 丙烯酸类聚 合物 (acrylic polymer)。 有机保护层 150的厚度可为约 3 μιη (微米；
micrometer：)。 有机保护层 150的形成方式可为例如旋涂法。
接着请参照图 5D。 如图所示， 制造者在此时可形成像素电极 160， 此像 素电极 160位于主动元件 130上， 并电性连接主动元件 130。 由于与此像素电 极 160相关的其他工艺、 材料与结构细节， 均与第三实施方式相同， 因此不再 重复赘述之。
接着请参照图 5E。 如图所示， 制造者在此时可剥离感光离型膜 300与载 板 200， 以获得主动元件阵列基板 100。 从结构上来看， 图 5E的主动元件阵 列基板 100与第三实施方式主要的不同在于： 图 5E的通气孔 GH中没有无机 填充材 170， 且至少部分的有机保护层 150将填充于通气孔 GH中。 亦即， 无 机阻障层 120的贯穿孔 122、 栅介电层 134的贯穿孔 135与无机保护层 140的 贯穿孔 142中将没有无机填充材 170， 且至少部分的有机保护层 150将填充于 无机阻障层 120的贯穿孔 122、 栅介电层 134的贯穿孔 135与无机保护层 140 的贯穿孔 142中。
图 6A〜6E绘示依照本发明第五实施方式的主动元件阵列基板 100的制造 流程剖面图， 其剖面位置与图 5A相同。 本实施方式与第四实施方式的不同点 在于： 本实施方式在有机保护层 150与像素电极 160形成后， 才光氧化感光离 型膜 300。
请先参照图 6A。 如图所示， 制造者在此时可先进行如图 5A所绘示的制 程。 由于这些工艺、 材料与结构细节， 均与第四实施方式相同， 因此不再重复 赘述之。
接着请参照图 6B。 如图所示， 制造者在此时可形成有机保护层 150， 此 有机保护层 150覆盖无机保护层 140， 且至少部分的有机保护层 150将填充于 通气孔 GH中。 在本实施方式中， 有机保护层 150的材质可为能够透氧的有机 介电材料， 例如： 丙烯酸类聚合物 (acrylic polymer：)。 由于与此有机保护层 150 相关的其他工艺与结构细节， 均与第四实施方式相同， 因此不再重复赘述之。 接着请参照图 6C。 如图所示， 制造者在此时可形成像素电极 160， 此像 素电极 160位于主动元件 130上 并电性连接主动元件 130。在本实施方式中， 像素电极 160的材质可为能够透氧的导电材料， 例如： 氧化铟锡、 氧化铟锌、 氧化锌铝或其他导电氧化物或上述任意的组合。 由于与此像素电极 160相关的 其他工艺与结构细节， 均与第四实施方式相同， 因此不再重复赘述之。
接着请参照图 6D。 如图所示， 制造者在此时可以光源照射感光离型膜 300， 使得光氧化后的感光离型膜 300与载板 200之间的粘着力降低。 此时由 于有机保护层 150与像素电极 160的材质能够透氧， 因此氧气将能穿过像素电 极 160、 有机保护层 150与软质基板 110， 而接触感光离型膜 300的正面， 以 加速感光离型膜 300光氧化的速度。
接着请参照图 6E。 如图所示， 制造者在此时可剥离感光离型膜 300与载 板 200， 以获得主动元件阵列基板 100。 从结构上来看， 图 6E的主动元件阵 列基板 100的结构与图 5E的主动元件阵列基板 100的结构大致相同。
图 7A〜7E绘示依照本发明第六实施方式的主动元件阵列基板 100的制造 流程剖面图， 其剖面位置与图 2A〜2H相同。 本实施方式与第一实施方式的不 同点在于： 本实施方式在形成有机保护层 150后， 会先形成像素电极连通孔 TH与通气孔 GH， 使得后续形成的像素电极 160覆盖通气孔 GH。
请先参照图 7A。 如图所示， 制造者在此时可先进行如第 2A〜2H图所绘 示的制程。 由于这些制程、 材料与结构细节， 均与第一实施方式相同， 因此不 再重复赘述之。
接着请参照图 7B。 如图所示， 制造者在此时可形成像素电极连通孔 TH 与通气孔 GH。 像素电极连通孔 TH贯穿无机保护层 140与有机保护层 150， 让漏极 139暴露出来， 而通气孔 GH则贯穿无机阻障层 120、 栅介电层 134、 无机保护层 140与有机保护层 150， 让软质基板 110暴露出来。 在本实施方式 中， 形成像素电极连通孔 TH与通气孔 GH的方式可为例如微影及蚀刻法。
接着请参照图 7C。 如图所示， 制造者在此时可以光源照射感光离型膜 300， 使得光氧化后的感光离型膜 300与载板 200之间的粘着力降低。 同样地， 由于通气孔 GH的存在， 因此氧气除了能够接触感光离型膜 300暴露出来的侧 面部分外， 也可以透过通气孔 GH与软质基板 110而接触感光离型膜 300的正 面， 使得感光离型膜 300光氧化的速度变快， 减少制程所需要的时间。
接着请参照图 7D。 如图所示， 制造者在此时可形成像素电极 160， 此像 素电极 160位于主动元件 130上， 并电性连接主动元件 130。 具体而言， 制造 者可形成第三导电层覆盖有机保护层 15(X像素电极连通孔 TH与通气孔 GH， 并随之图案化此第三导电层， 以形成像素电极 160。 所形成的像素电极 160将 通过像素电极连通孔 TH, 与漏极 139电性连接， 并覆盖通气孔 GH。
由于在形成第三导电层时， 感光离型膜 300已经光氧化， 因此第三导电层 的形成方式可选择低温工艺， 例如： 等离子增强化学气相沉积
法（Plasma-Enhanced CVD; PECVD), 低温真空溅镀。 上述的第三导电层 (或 者说， 像素电极 160)的材质可为透明导电材料， 例如： 氧化铟锡、 氧化铟锌、 氧化锌铝或其他导电氧化物或上述任意的组合。 或者， 第三导电层 (或者说， 像素电极 160)的材质亦可为其他不透明的导电材料， 例如： 钛、 钼、 铬、 铱、 铝、 铜、 银、 金或上述的任意组合或合金。 第三导电层 (或者说， 像素电极 160) 的厚度可为约 10〜500 nm(纳米； nanometer：)。 图案化第三导电层的方式可为 例如微影及蚀刻法。
接着请参照图 7E。 如图所示， 制造者在此时可剥离感光离型膜 300与载 板 200， 以获得主动元件阵列基板 100。 从结构上来看， 图 7E的主动元件阵 列基板 100与第一实施方式主要的不同在于： 本实施方式的像素电极 160覆盖 通气孔 GH。 亦即， 本实施方式的像素电极 160覆盖有机保护层 150的贯穿孔 152、 无机保护层 140的贯穿孔 142、 栅介电层 134的贯穿孔 135与无机阻障 层 120的贯穿孔 122。
以上各实施方式所提供的主动元件阵列基板 100可应用于各种显示器 中， 其包含但不限于： 液晶显示器 (Liquid Crystal Display; LCD), 电泳显示 器 (Electro-Phoretic Display; EPD)与主动矩阵有机发光二极管显示器
(Active-Matrix Organic Light-Emitting Diode Display; AMOLED Display)。 应 了解到， 以上所举的主动元件阵列基板 100的应用范围仅为例示， 并非用以限 制本发明， 本发明所属技术领域中普通技术人员， 应视实际需要弹性选择主动 元件阵列基板 100的应用方式。
以下将公开本发明的实施例， 借此说明上述实施方式的通气孔， 确实能够 增加感光离型膜光氧化的速度。 应了解到， 在以下叙述中， 已经在上述实施方 式中提到的参数将不再重复赘述， 仅就需进一歩界定者加以补充， 合先叙明。 在以下比较例及实施例中， 将提供材质为透明玻璃的载板， 尺寸为 320 mm (毫米； millimeter) x 400 mm (毫米； millimeter) x 0.7 mm (毫米； mimmete!^ 载板上形成有感光离型膜， 此感光离型膜的材质为聚对二甲苯 (Poly(p-xylylene)或 Parylene)， 厚度为 300 nm (纳米； nanometer)。 感光离型膜 上形成有软质基板， 此软质基板的材质为聚酰亚胺 (Polyimide; PI), 厚度为 ΙΟ μιη (微米； micrometer)。 软质基板上形成有无机阻障层， 此无机阻障层的 材质为氮化硅， 厚度为 200 nm(纳米； nanometer：)。 比较例与实施例的不同点 在于， 比较例没有形成通气孔， 实施例形成有贯穿无机阻障层， 且暴露出软质 基板的通气？ L 这些通气孔均匀分布于无机阻障层中，通气孔的直径为 5μηι (微 米； micrometer), 且任两相邻的通气孔之间的间距为 250μηι(;微米；
micrometer)。
接着， 从载板相对于感光离型膜的背侧照射紫外光 10分钟。 然后， 测试 感光离型膜与软质基板之间的连接介面的荷重对位移关系， 并将结果记录图 8 与图 9中， 其中图 8绘示比较例的测试结果， 图 9绘示实施例的测试结果。 从 图 8可以看得出来， 在紫外光照射 10分钟后， 要破坏比较例的感光离型膜与 软质基板之间的连接介面， 仍要约 950 gf的力量。 相对地， 从图 9可以看得出 来， 在紫外光照射 10分钟后， 要破坏实施例的感光离型膜与软质基板之间的 连接介面， 只要约 l gf的力量。
当然， 本发明还可有其它多种实施例， 在不背离本发明精神及其实质的情 况下， 熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形， 但 这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。 工业应用性
本发明的功效在于， 所提出的主动元件阵列基板上存在通气孔， 氧气除了 能够接触感光离型膜暴露出来的侧面部分外， 也可以通过通气孔与软质基板而 接触感光离型膜的正面， 使得感光离型膜光氧化的速度变快， 减少工艺所需要 的时间。

Claims

权利要求书
1. 一种主动元件阵列基板， 其特征在于， 包含：
一软质基板；
一无机阻障层，覆盖该软质基板，该无机阻障层具有至少一贯穿孔于其中， 该贯穿孔暴露出该软质基板； 以及
至少一主动元件， 位于该无机阻障层上。
2. 根据权利要求 1所述的主动元件阵列基板， 其特征在于， 其中该主动 元件包含：
一栅极， 位于该无机阻障层上；
一栅介电层， 至少覆盖该栅极；
一通道层， 位于该栅极上方的该栅介电层上； 以及
一源极与一漏极， 分别位于该通道层的两侧。
3. 根据权利要求 2所述的主动元件阵列基板， 其特征在于， 其中该栅介 电层覆盖该栅极与该无机阻障层， 且该栅介电层具有至少一贯穿孔于其中， 其 中该栅介电层的该贯穿孔连通于该无机阻障层的该贯穿孔。
4. 根据权利要求 3所述的主动元件阵列基板， 其特征在于， 其中该无机 阻障层的该贯穿孔与该栅极之间具有一间距。
5. 根据权利要求 3所述的主动元件阵列基板， 其特征在于， 还包含： 一无机保护层，覆盖该主动元件，该无机保护层具有至少一贯穿孔于其中， 其中该无机保护层的该贯穿孔与该栅介电层的该贯穿孔以及该无机阻障层的 该贯穿孔至少部分重叠；
一有机保护层， 覆盖于该无机保护层； 以及
一像素电极， 位于该有机保护层上， 并电性连接该主动元件。
6. 根据权利要求 1所述的主动元件阵列基板， 其特征在于， 还包含： 一无机保护层，覆盖该主动元件，该无机保护层具有至少一贯穿孔于其中， 其中该无机保护层的该贯穿孔与该无机阻障层的该贯穿孔至少部分重叠。
7. 根据权利要求 1所述的主动元件阵列基板， 其特征在于， 还包含： 一有机保护层， 覆盖于该主动元件。
8 根据权利要求 7所述的主动元件阵列基板， 其特征在于， 其中该有机保 护层具有至少一贯穿孔于其中，其中该有机保护层的该贯穿孔与该无机阻障层 的该贯穿孔至少部分重叠。
9. 根据权利要求 7所述的主动元件阵列基板， 其特征在于， 其中至少部 分的该有机保护层填充于该无机阻障层的该贯穿孔中。
10. 根据权利要求 1所述的主动元件阵列基板， 其特征在于， 还包含： 一像素电极， 位于该主动元件上， 并电性连接该主动元件。
11. 根据权利要求 10所述的主动元件阵列基板， 其特征在于， 其中该像 素电极具有至少一贯穿孔于其中，其中该像素电极的该贯穿孔与该无机阻障层 的该贯穿孔至少部分重叠。
12. 根据权利要求 10所述的主动元件阵列基板， 其特征在于， 其中该像 素电极覆盖该无机阻障层的该贯穿孔。
13. 根据权利要求 1所述的主动元件阵列基板， 其特征在于， 还包含： 至少一无机填充材， 共形地覆盖该无机阻障层的该贯穿孔。
14. 根据权利要求 1所述的主动元件阵列基板， 其特征在于， 还包含： 一感光离型膜， 设置于该软质基板相反于该无机阻障层的一表面。
15. 一种主动元件阵列基板的制造方法， 其特征在于， 包含：
以一感光离型膜将一软质基板粘着于一载板上；
形成一无机阻障层覆盖该软质基板；
在该无机阻障层上形成至少一主动元件；
于该无机阻障层中形成至少一贯穿孔， 以暴露出该软质基板；
以一光源照射该感光离型膜； 以及
剥离该感光离型膜与该载板。
16. 根据权利要求 15所述的主动元件阵列基板的制造方法， 其特征在于， 其中形成该主动元件的歩骤包含：
在该无机阻障层上形成一栅极；
形成一栅介电层至少覆盖该栅极；
于该栅极上方的该栅介电层上形成一通道层； 以及
于该通道层的两侧形成一源极与一漏极。
17. 根据权利要求 16所述的主动元件阵列基板的制造方法， 还包含： 形成一贯穿孔于该栅介电层中，其中该栅介电层的该贯穿孔与该无机阻障 层的该贯穿孔构成一连通的通气孔， 以暴露出该软质基板。
18. 根据权利要求 16所述的主动元件阵列基板的制造方法， 其特征在于， 还包含：
形成一贯穿孔于该栅介电层中；
形成一无机保护层， 覆盖该主动元件， 该无机保护层具有至少一贯穿孔于 其中，其中该无机保护层的该贯穿孔连通于该栅介电层的该贯穿孔以及该无机 阻障层的该贯穿孔， 以构成一连通的通气孔；
形成一有机保护层于该无机保护层上； 以及
形成一像素电极于该有机保护层上， 并电性连接该主动元件。
19. 根据权利要求 15所述的主动元件阵列基板的制造方法， 其特征在于， 还包含：
形成一无机保护层覆盖该主动元件，其中该无机保护层具有至少一贯穿孔 于其中，该无机保护层的该贯穿孔与该无机阻障层的该贯穿孔构成一连通的通 气孔， 以暴露出该软质基板。
20. 根据权利要求 15所述的主动元件阵列基板的制造方法， 其特征在于， 还包含：
于该无机阻障层的该贯穿孔中形成一无机填充材。
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