WO2014181509A1 - Substrat multicouche et dispositif électronique qui utilise ce dernier, ainsi que procédé permettant de fabriquer un dispositif électronique - Google Patents

Substrat multicouche et dispositif électronique qui utilise ce dernier, ainsi que procédé permettant de fabriquer un dispositif électronique Download PDF

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Publication number
WO2014181509A1
WO2014181509A1 PCT/JP2014/002248 JP2014002248W WO2014181509A1 WO 2014181509 A1 WO2014181509 A1 WO 2014181509A1 JP 2014002248 W JP2014002248 W JP 2014002248W WO 2014181509 A1 WO2014181509 A1 WO 2014181509A1
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WIPO (PCT)
Prior art keywords
layer
mold
land
multilayer substrate
electronic device
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PCT/JP2014/002248
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English (en)
Japanese (ja)
Inventor
俊浩 中村
正英 辰己
英二 藪田
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株式会社デンソー
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Publication of WO2014181509A1 publication Critical patent/WO2014181509A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present disclosure relates to a land on which electronic components are mounted and a multilayer substrate having a surface pattern electrically connected to an external circuit, an electronic device using the same, and a method for manufacturing the electronic device.
  • Patent Document 1 an electronic device in which an electronic component is mounted on one side of a substrate has been proposed (see, for example, Patent Document 1). Specifically, in this electronic device, a surface pattern that is electrically connected to lands and external circuits is formed on one surface of the substrate, and a solder resist that covers the surface pattern is formed. The solder resist has an opening for exposing a portion of the surface pattern that is connected to an external circuit. The electronic component is mounted on the land via solder or the like. In addition, one surface side of the substrate including the electronic component is sealed with a mold resin so that at least a portion of the surface pattern connected to the external circuit is exposed.
  • Such an electronic device is manufactured as follows. That is, first, a land and a surface pattern are formed on one surface of the substrate. And after forming the solder resist which covers a surface pattern, the opening part which exposes a part of surface pattern to a solder resist is formed. Next, the electronic component is mounted on the land via solder or the like. Subsequently, a mold having a recess formed on one surface is prepared, and one surface of the mold is pressed against one surface of the substrate so that the electronic component is disposed in the recess. Thereafter, the space between the substrate and the concave portion of the mold is filled with mold resin, whereby the electronic device in which one surface side of the substrate including the electronic component is sealed is manufactured.
  • the height of the portion of the solder resist that covers the surface pattern from the substrate surface is higher than the height of the portion of the solder resist that does not cover the surface pattern from the substrate surface. That is, the height of the solder resist from the substrate surface is different in each part in the part not sealed with the mold resin.
  • the one surface of the mold contacts with a portion of the solder resist that covers the surface pattern, and does not contact with a portion of the solder resist that does not cover the surface pattern.
  • a gap may be formed between one surface of the mold and a portion of the solder resist that does not cover the surface pattern. Therefore, when the gap and the space between the substrate and the concave portion of the mold communicate with each other, the mold resin flows out of the gap when the space between the substrate and the concave portion of the mold is filled with the mold resin. May end up. And the part exposed from a soldering resist among surface patterns may be covered with mold resin.
  • This disclosure is intended to provide a multilayer substrate capable of suppressing the surface pattern from being covered with a mold resin, an electronic device using the same, and a method for manufacturing the electronic device.
  • the multilayer substrate includes a core layer having a surface, an inner layer wiring formed on the surface of the core layer, and a buildup disposed in a state of covering the inner layer wiring on the surface of the core layer.
  • the layer is formed on one side of the build-up layer opposite to the core layer, and is formed on one side of the build-up layer and the land on which the electronic component is mounted, and is electrically connected to the land via the inner layer wiring.
  • a surface pattern that is electrically connected to an external circuit, and a protective film that covers the surface pattern and has an opening that exposes a part of the surface pattern are formed.
  • one surface of the build-up layer is insulated from the land and the surface pattern, surrounds the land and is formed between the land and the surface pattern, and a protective covering the surface layer conductor.
  • a height of the protective film from one side of the build-up layer on the mold step is a height from one side of the build-up layer of the protective film covering the surface pattern. More than that.
  • the mold step is always pressed against the mold.
  • the mold step is formed in a frame shape surrounding the land and is formed between the land and the surface pattern. Therefore, the mold resin can be prevented from flowing out of the space between the multilayer substrate and the mold, and the portion of the surface pattern exposed from the opening of the protective film can be prevented from being covered with the mold resin.
  • an electronic device seals the multilayer substrate according to the first aspect, the electronic component mounted on the land, and the inner edge side of the protective film in the electronic component, the land, and the mold step part. And a mold resin to be stopped.
  • the manufacturing method includes preparing a multilayer substrate, mounting electronic components on lands in the multilayer substrate, Forming a mold resin for sealing the inner edge side of the protective film in the electronic component, the land, and the mold step portion.
  • a mold resin for sealing the inner edge side of the protective film in the electronic component, the land, and the mold step portion.
  • a mold having a recess formed on one surface is prepared, and after pressing one surface of the mold against the mold step so that an electronic component is placed in the recess, the multilayer substrate and the recess Fill the space between the mold resin.
  • the mold resin can be prevented from flowing out from the space between the multilayer substrate and the concave portion of the mold, and the opening of the protective film in the surface pattern It can suppress that the part exposed from is covered with mold resin.
  • FIG. 1 is a cross-sectional view of an electronic device according to a first embodiment of the present disclosure. It is a top view of the electronic device shown in FIG.
  • FIG. 7 is a cross-sectional view showing a manufacturing process of the electronic device shown in FIG. 1.
  • FIG. 4 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 3.
  • FIG. 5 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 4.
  • FIG. 6 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 5. It is an enlarged view of the electronic device in a 2nd embodiment of this indication.
  • a first embodiment of the present disclosure will be described. Note that the electronic device of the present embodiment is preferably mounted on a vehicle such as an automobile, for example, and applied to drive various electronic devices for the vehicle.
  • the electronic device includes a multilayer substrate 10 having one surface 10a and another surface 10b, and electronic components 121 to 123 mounted on the one surface 10a of the multilayer substrate 10.
  • the electronic device is configured by sealing the one surface 10a side of the multilayer substrate 10 together with the electronic components 121 to 123 with the mold resin 150.
  • the multilayer substrate 10 includes a core layer 20 as an insulating resin layer, a build-up layer 30 on the surface 20a side disposed on the surface 20a of the core layer 20, and a back surface 20b side disposed on the back surface 20b side of the core layer 20.
  • the core layer 20 and the buildup layers 30 and 40 are composed of a prepreg formed by sealing both surfaces of a glass cloth with a resin, and examples of the prepreg resin include an epoxy resin.
  • the prepreg resin may contain a filler having excellent electrical insulation and heat dissipation, such as alumina and silica, as necessary.
  • a patterned surface-side inner layer wiring 51 (hereinafter simply referred to as an inner layer wiring 51) is formed at the interface between the core layer 20 and the buildup layer 30.
  • a patterned back side inner layer wiring 52 (hereinafter simply referred to as an inner layer wiring 52) is formed.
  • patterned surface side surface wirings 61 to 63 are formed on the surface 30a of the build-up layer 30, patterned surface side surface wirings 61 to 63 (hereinafter simply referred to as surface layer wirings 61 to 63) are formed.
  • the surface wirings 61 to 63 are bonding lands 61 on which the electronic components 121 to 123 are mounted and the bonding components 141 and 142 that are electrically connected to the electronic components 121 and 122 via the bonding wires 141 and 142.
  • the land 62 is a surface pattern 63 that is electrically connected to an external circuit.
  • patterned back surface side wirings 71 and 72 are formed on the front surface 40a of the buildup layer 40.
  • the surface layer wirings 71 and 72 are a back surface pattern 71 connected to the inner layer wiring 52 through a filled via described later, a heat sink pattern 72 provided with a heat sink for heat dissipation (hereinafter simply referred to as an HS pattern 72). ).
  • the surface 30 a of the buildup layer 30 is one surface of the buildup layer 30 opposite to the core layer 20, and is a surface that becomes the one surface 10 a of the multilayer substrate 10.
  • the surface 40 a of the buildup layer 40 is one surface of the buildup layer 40 opposite to the core layer 20, and is a surface that becomes the other surface 10 b of the multilayer substrate 10.
  • the inner layer wirings 51 and 52, the surface layer wirings 61 to 63, and the surface layer wirings 71 and 72, which will be specifically described later, are configured by appropriately laminating metal foil such as copper or metal plating.
  • the inner layer wiring 51 and the inner layer wiring 52 are electrically and thermally connected through a through via 81 provided through the core layer 20.
  • the through via 81 is configured such that a through electrode 81b such as copper is formed on the wall surface of the through hole 81a penetrating the core layer 20 in the thickness direction, and a filler 81c is filled in the through hole 81a. Has been.
  • the inner layer wiring 51 and the surface layer wirings 61 to 63, and the inner layer wiring 52 and the surface layer wirings 71 and 72 pass through the filled vias 91 and 101 provided through the respective buildup layers 30 and 40 in the thickness direction as appropriate. Connected electrically and thermally. Accordingly, the lands 61 and 62 and the surface layer wiring 63 are appropriately electrically connected via the inner layer wirings 51 and 52, the back surface pattern 71, the through via 81, and the filled vias 91 and 101.
  • the filled vias 91 and 101 are configured such that through holes 91a and 101a penetrating the build-up layers 30 and 40 in the thickness direction are filled with through electrodes 91b and 101b such as copper.
  • the filler 81c is made of resin, ceramic, metal, or the like, but is an epoxy resin in this embodiment.
  • the through electrodes 81b, 91b, 101b are configured by metal plating such as copper.
  • the solder resist 110 that covers the front surface pattern 63 and the back surface pattern 71 is formed on the front surfaces 30a and 40a of the buildup layers 30 and 40, respectively.
  • the solder resist 110 that covers the surface pattern 63 is formed with an opening 110a that exposes a portion of the surface pattern 63 that is connected to an external circuit.
  • the solder resist 110 that covers the surface pattern 63 corresponds to a protective film.
  • the electronic components 121 to 123 include a power element 121 that generates a large amount of heat, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a control element 122 such as a microcomputer, a passive such as a chip capacitor or a resistor. Element 123.
  • the electronic components 121 to 123 are mounted on the land 61 via the solder 130 and are electrically and mechanically connected to the land 61.
  • the power element 121 and the control element 122 are also electrically connected to the land 62 formed in the periphery via bonding wires 141 and 142 such as aluminum and gold.
  • the power element 121, the control element 122, and the passive element 123 are described as examples of the electronic components 121 to 123, but the electronic components 121 to 123 are not limited to these.
  • the mold resin 150 seals the lands 61 and 62 and the electronic components 121 to 123, and a general mold material such as an epoxy resin is formed by a transfer molding method using a mold, a compression molding method, or the like. Is.
  • the mold resin 150 is formed only on the one surface 10a of the multilayer substrate 10. That is, the electronic device of this embodiment has a so-called half mold structure. Further, on the other surface 10 b side of the multilayer substrate 10, although not particularly shown, a heat sink is provided on the HS pattern 72 via heat dissipation grease or the like.
  • the mold step part 64 is formed in the surface 30a of the buildup layer 30.
  • FIG. 1 the structure of the type
  • the mold step portion 64 is a portion to which a mold constituting the outer shape of the mold resin 150 is pressed when the mold resin 150 is formed, and a surface layer conductor 64 a formed on the surface 30 a of the buildup layer 30, and a surface layer conductor
  • the solder resist 110 covers the 64a.
  • the surface conductor 64 a has a frame shape surrounding the lands 61 and 62, and is formed between the lands 61 and 62 and the surface pattern 63. Further, the surface layer conductor 64 a is insulated from the lands 61 and 62 and the surface pattern 63. That is, the surface layer conductor 64a is a so-called dummy pattern for adjusting the height of the mold step 64.
  • the surface conductor 64a is completely covered with the solder resist 110 that covers the surface pattern 63. That is, the height of the solder resist 110 from the surface 30a of the buildup layer 30 in the mold step 64 is constant in the circumferential direction.
  • the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is set to be equal to or higher than the height from the surface 30a of the build-up layer 30 in the part covering the surface pattern 63 in the solder resist 110.
  • the film thickness of the surface pattern 63 and the surface layer conductor 64a is made equal, and the film thickness of each part of the solder resist 110 is also made equal.
  • the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is made equal to the height from the surface 30a of the build-up layer 30 in the part of the solder resist 110 that covers the surface pattern 63. ing.
  • the mold resin 150 seals the inner edge side portion of the solder resist 110 constituting the mold step portion 64 while exposing the outer edge side portion of the solder resist 110 constituting the die step portion 64. That is, it can be said that the mold step 64 is formed at the interface between the portion sealed with the mold resin 150 and the portion not sealed on the one surface 10 a of the multilayer substrate 10.
  • the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is, in other words, the build-up layer 30 from the surface opposite to the surface layer conductor 64a in the solder resist 110 covering the surface layer conductor 64a. It is the length to the surface 30a.
  • the surface pattern 63 and the surface layer conductor 64a are covered with the same solder resist 110.
  • the solder resist 110 that covers the surface pattern 63 and the solder resist 110 that covers the surface layer conductor 64a are separated. Good.
  • FIGS. 3 to 5 are cross-sectional views in the vicinity of a portion of the multilayer substrate 10 where the power element 121 is mounted.
  • FIG. 3 (a) a structure in which metal foils 161 and 162 such as copper foil are arranged on the front surface 20 a and the back surface 20 b of the core layer 20 is prepared. Then, as shown in FIG. 3B, a through hole 81a penetrating the metal foil 161, the core layer 20, and the metal foil 162 is formed by a drill or the like.
  • electroless plating or electroplating is performed to form a metal plating 163 such as copper on the wall surface of the through hole 81a and the metal foils 161 and 162.
  • a through electrode 81b composed of the metal plating 163 is formed on the wall surface of the through hole 81a.
  • catalysts such as palladium.
  • a filler 81 c is arranged in a space surrounded by the metal plating 163.
  • the through via 81 having the through hole 81a, the through electrode 81b, and the filler 81c is formed.
  • lid plating is performed by electroless plating, electroplating, or the like, and metal plating 164, 165 such as copper is formed on the metal plating 163 and the filler 81c.
  • a resist (not shown) is disposed on the metal platings 164 and 165. Then, wet etching or the like is performed using the resist as a mask, and the metal plating 164, the metal plating 163, and the metal foil 161 are appropriately patterned to form the inner layer wiring 51, and the metal plating 165, the metal plating 163, and the metal foil 162 are appropriately formed.
  • the inner layer wiring 52 is formed by patterning. That is, in this embodiment, the inner layer wiring 51 is configured by laminating the metal foil 161, the metal plating 163, and the metal plating 164, and the inner layer wiring 52 is configured by laminating the metal foil 162, the metal plating 163, and the metal plating 165. It is configured.
  • the metal foil 161, the metal plating 163, the metal plating 164, the metal foil 162, the metal plating 163, and the metal plating 165 are collectively shown as one layer.
  • a buildup layer 30 and a metal plate 166 such as copper are laminated on the inner layer wiring 51 on the surface 20a side of the core layer 20. Then, as shown in FIG. Further, the buildup layer 40 and a metal plate 167 such as copper are laminated on the inner layer wiring 52 on the back surface 20 b side in the core layer 20. In this way, a stacked body 168 is configured in which the metal plate 166, the buildup layer 30, the inner layer wiring 51, the core layer 20, the inner layer wiring 52, the buildup layer 30, and the metal plate 167 are sequentially stacked from the top.
  • the laminate 168 is integrated by heating while pressing from the lamination direction of the laminate 168. Specifically, by pressurizing the laminate 168, the resin constituting the buildup layer 30 is caused to flow to embed between the inner layer wirings 51, and the resin constituting the buildup layer 40 is caused to flow to cause the inner layer wirings 52 to flow. Embed between. And the buildup layers 30 and 40 are hardened by heating the laminated body 168, and the laminated body 168 is integrated.
  • a through hole 91a that penetrates the metal plate 166 and the buildup layer 30 and reaches the inner layer wiring 51 is formed by a laser or the like.
  • a through hole 101 a that penetrates the metal plate 167 and the buildup layer 40 and reaches the inner layer wiring 52 is formed in a cross section different from FIG.
  • the through electrode 91b and the through electrode 101b shown in FIG. 1 are configured by the metal plating 169 embedded in the through holes 91a and 101a formed in the buildup layers 30 and 40. Further, filled vias 91 and 101 in which through electrodes 91b and 101b are embedded in the through holes 91a and 101a are formed.
  • the metal plate 166 and the metal plating 169 are collectively shown as one layer.
  • a resist (not shown) is placed on the metal plate 166. Then, wet etching or the like is performed using the resist as a mask to pattern the metal plate 166, thereby forming the surface layer wirings 61 to 63 and the surface layer conductor 64a. For this reason, the surface layer wirings 61 to 63 and the surface layer conductor 64a have the same height from the surface 30a of the buildup layer 30.
  • a resist (not shown) is arranged on the metal plate 167, and the metal plate 167 is patterned by performing wet etching or the like using the resist as a mask, thereby forming the surface layer wirings 71 and 72.
  • the surface layer wirings 61 to 63 are configured to have the metal plate 166 and the metal plating 169, and the surface layer wirings 71 and 72 are configured to include the metal plate 167 and the metal plating 169.
  • the surface layer conductor 64 a is not electrically connected to the inner layer wiring 51, and the filled via 91 is not formed between the inner layer wiring 51, and thus is constituted only by the metal plate 166.
  • the solder resist 110 is disposed on the surfaces 30a and 40a of the buildup layers 30 and 40, respectively, and patterned appropriately.
  • the multilayer substrate 10 in which the mold step 64 is formed by the surface layer conductor 64a and the solder resist 110 is manufactured.
  • the mold step portion 64 is such that the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is a part of the build-up layer that covers the surface pattern 63 in the solder resist 110. 30 is equal to the height from the surface 30a.
  • the electronic components 121 to 123 are mounted on the land 61 via the solder 130. Then, wire bonding is performed between the power element 121 and the control element 122 and the land 62, and the power element 121 and the control element 122 and the land 62 are electrically connected.
  • a molding resin 150 is formed by a transfer molding method using a mold or a compression molding method so that the lands 61 and 62 and the electronic components 121 to 123 are sealed. To do.
  • a mold 200 is prepared in which a recess 201 constituting the outer shape of the mold resin 150 is formed on one surface 200a, and the surface 200a is multilayered so that the electronic components 121 to 123 are disposed in the recess 201.
  • the substrate 10 is in pressure contact with the one surface 10a side.
  • the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is from the surface 30a of the build-up layer 30 that covers the surface pattern 63 in the solder resist 110. Is equal to the height. For this reason, the mold step 64 is pressed against the mold 200. Moreover, since the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is constant in the circumferential direction, no gap is formed between the mold step 64 and the mold 200. .
  • the said electronic device is manufactured by filling the space between the multilayer substrate 10 and the recessed part 201 of the metal mold
  • the height from the surface 30 a of the buildup layer 30 is set to be equal to or higher than the height from the surface 30 a of the buildup layer 30 in the part of the solder resist 110 that covers the surface pattern 63.
  • the mold step 64 is formed. For this reason, when the one surface 200 a of the mold 200 is pressed against the one surface 10 a side of the multilayer substrate 10, the mold step 64 is always pressed against the mold 200.
  • the mold step 64 has a frame shape surrounding the lands 61 and 62 and is formed between the lands 61 and 62 and the surface pattern 63.
  • the surface conductor 64a of the present embodiment has a rounded corner on the opposite side to the buildup layer 30 side in the cross section in the thickness direction.
  • the lands 61 and 62 and the surface pattern 63 are portions for electrically connecting the electronic components 121 to 123 and the external circuit, and it is preferable to increase the current capacity. Therefore, as shown in FIG.
  • the cross section in the thickness direction is rectangular. That is, the lands 61 and 62 and the surface pattern 63 have a right-angled corner in the cross section opposite to the buildup layer 30 side in the cross section in the thickness direction.
  • FIG. 7 is an enlarged view corresponding to the area A in FIG.
  • the core layer 20 and the buildup layers 30 and 40 are illustrated as being composed of a single prepreg layer. It is good also as what is comprised from.
  • mold step part 64 is made from the surface 30a of the buildup layer 30 of the part which covers the surface pattern 63 among the solder resists 110.
  • the following may be performed.
  • metal plating or the like may be formed only on the surface layer conductor 64a.
  • the mold step 64 has been described in which the height from the surface 30a of the buildup layer 30 is constant in the circumferential direction. That is, even if a depression is formed in the solder resist 110 constituting the mold step 64, the height of the portion where the depression is formed in the mold depression 64 is slightly lower than the height of the other portions. Good. According to this, when forming mold resin 150, the void which may be generated in mold resin 150 can be discharged from a hollow part. In the case where such a mold step portion 64 is configured, even if the mold resin 150 flows out of the recess portion, a portion of the surface pattern 63 exposed from the solder resist 110 is not covered with the mold resin 150. It is preferable to form a depression.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

La présente invention se rapporte à un substrat multicouche. Selon l'invention, un pied de moule (64) est agencé sur une face (30a) d'une couche d'accumulation (30), le pied de moule (64) comprend un conducteur de couche superficielle en forme de cadre (64a) isolé d'une surface d'appui (61) et d'un motif de surface (63), entourant la surface d'appui (61) et étant formé entre la surface d'appui (61) et le motif de surface (63), ainsi qu'un film de protection (110) destiné à recouvrir le conducteur de couche superficielle (64a). La hauteur du film de protection (110) du pied de moule (64) par rapport à l'unique face (30a) de la couche d'accumulation (30) est égale ou supérieure à la hauteur d'une partie du film de protection (110) qui recouvre le motif de surface (63) de l'unique face (30a) de la couche d'accumulation (30). Une résine moulée peut, de ce fait, être empêchée de recouvrir le motif de surface.
PCT/JP2014/002248 2013-05-06 2014-04-22 Substrat multicouche et dispositif électronique qui utilise ce dernier, ainsi que procédé permettant de fabriquer un dispositif électronique WO2014181509A1 (fr)

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JP2013097227A JP6111832B2 (ja) 2013-05-06 2013-05-06 多層基板およびこれを用いた電子装置、電子装置の製造方法
JP2013-097227 2013-05-06

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