JP6044441B2 - 電子装置の製造方法およびこれに用いられる多層基板 - Google Patents
電子装置の製造方法およびこれに用いられる多層基板 Download PDFInfo
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- JP6044441B2 JP6044441B2 JP2013094374A JP2013094374A JP6044441B2 JP 6044441 B2 JP6044441 B2 JP 6044441B2 JP 2013094374 A JP2013094374 A JP 2013094374A JP 2013094374 A JP2013094374 A JP 2013094374A JP 6044441 B2 JP6044441 B2 JP 6044441B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
本発明の第1実施形態について説明する。なお、本実施形態の電子装置は、例えば、自動車等の車両に搭載され、車両用の各種電子装置を駆動するために適用されると好適である。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
20 コア層
30 ビルドアップ層
61 ランド
61a 一面
61c 側面
121〜123 電子部品
130 はんだ
150 モールド樹脂
180 マスキングインク
Claims (4)
- 表面(20a)を有するコア層(20)の表面に内層配線(51)を形成したのち、前記コア層の表面に前記内層配線を覆う状態で配置されるビルドアップ層(30)を形成し、さらに前記ビルドアップ層のうち前記コア層と反対側の一面(30a)に、電子部品(121〜123)が搭載されるランド(61)を含めて、前記内層配線と少なくとも一部が電気的に接続される表層配線(61〜63)をパターニングすることで多層基板(10)を用意する工程と、
前記ランドの外縁部を覆いつつ、前記ビルドアップ層のうち前記表層配線から露出させられている部分をマスキングインク(180)で覆う工程と、
前記マスキングインクにて覆った部分を保護しつつ、該マスキングインクで覆われていない前記ランドの内周位置にはんだ(130)を形成する工程と、
前記マスキングインクから露出させられた前記はんだの上に前記電子部品を搭載し、前記ランドのうちの内周位置に配置された前記はんだにより、前記電子部品を前記ランドと接続する工程と、
前記マスキングインクを除去する工程と、を含んでいることを特徴とする電子装置の製造方法。 - 前記マスキングインクで覆う工程では、前記ランドの中心から見て、該ランドの周囲のうち前記内層配線が形成されている方向において、前記マスキングインクで前記ランドの外縁部を覆うことを特徴とする請求項1に記載の電子装置の製造方法。
- 表面(20a)を有するコア層(20)と、
前記コア層の表面に形成された内層配線(51)と、
前記コア層の表面に前記内層配線を覆う状態で配置されたビルドアップ層(30)と、
前記ビルドアップ層のうち前記コア層と反対側の一面(30a)に形成され、はんだ(130)を介して電子部品(121〜123)が搭載されるランド(61)を含む表層配線(61〜63)と、を備え、
前記電子部品および前記ランドがモールド樹脂(150)にて封止される電子装置の製造に適用される多層基板であって、
前記ビルドアップ層の上に形成され、前記はんだを前記ランドの一面に配置する際に、前記はんだを配置する位置を露出させつつ前記はんだが配置される位置の外側の領域を覆うことで保護するマスキングインク(180)を備え、
前記マスキングインクは、前記ランドの外縁部を覆いつつ、該ランドの内周位置を露出させていることを特徴とする多層基板。 - 前記ランドの中心から見て、該ランドの周囲のうち前記内層配線が形成されている方向において、前記マスキングインクが前記ランドの外縁部を覆っていることを特徴とする請求項3に記載の多層基板。
Priority Applications (1)
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JP2013094374A JP6044441B2 (ja) | 2013-04-26 | 2013-04-26 | 電子装置の製造方法およびこれに用いられる多層基板 |
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JP2013094374A JP6044441B2 (ja) | 2013-04-26 | 2013-04-26 | 電子装置の製造方法およびこれに用いられる多層基板 |
Publications (2)
Publication Number | Publication Date |
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JP2014216563A JP2014216563A (ja) | 2014-11-17 |
JP6044441B2 true JP6044441B2 (ja) | 2016-12-14 |
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JP2013094374A Expired - Fee Related JP6044441B2 (ja) | 2013-04-26 | 2013-04-26 | 電子装置の製造方法およびこれに用いられる多層基板 |
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Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3556922B2 (ja) * | 2001-05-07 | 2004-08-25 | 富士通株式会社 | バンプ形成方法 |
JP2004119544A (ja) * | 2002-09-25 | 2004-04-15 | Kyocera Corp | 配線基板およびその製造方法 |
JP4855667B2 (ja) * | 2004-10-15 | 2012-01-18 | ハリマ化成株式会社 | 樹脂マスク層の除去方法およびはんだバンプ付き基板の製造方法 |
JP2009111299A (ja) * | 2007-10-31 | 2009-05-21 | Athene Kk | バンプ付き基板の製造方法 |
JP2009208259A (ja) * | 2008-02-29 | 2009-09-17 | Kyocer Slc Technologies Corp | 印刷マスクおよびこれを用いた配線基板の製造方法 |
WO2011007519A1 (ja) * | 2009-07-16 | 2011-01-20 | パナソニック株式会社 | モジュール部品とその製造方法 |
JP5512562B2 (ja) * | 2010-03-29 | 2014-06-04 | 日本特殊陶業株式会社 | 多層配線基板 |
JP2012209418A (ja) * | 2011-03-30 | 2012-10-25 | Kyocer Slc Technologies Corp | 配線基板およびその製造方法 |
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