WO2014155455A1 - 配線基板 - Google Patents
配線基板 Download PDFInfo
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- WO2014155455A1 WO2014155455A1 PCT/JP2013/007314 JP2013007314W WO2014155455A1 WO 2014155455 A1 WO2014155455 A1 WO 2014155455A1 JP 2013007314 W JP2013007314 W JP 2013007314W WO 2014155455 A1 WO2014155455 A1 WO 2014155455A1
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- WIPO (PCT)
- Prior art keywords
- pad
- substrate
- convex portion
- wiring board
- opening
- Prior art date
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Definitions
- the present invention relates to a wiring board in which a plurality of pads capable of forming solder bumps used for connection to a mother board are arranged on the back surface of the board.
- solder resist 103 is formed so as to cover the back surface 102 of the substrate, and a plurality of openings 105 for exposing the pads 104 are provided in the solder resist 103. ing.
- a solder bump 106 is formed in 105.
- the solder bump 106 is formed by, for example, a printing method or a solder ball method (microball method).
- the printing method is to form a solder bump 106 by printing a solder paste on a plurality of pads 104 formed on the substrate back surface 102 of the wiring substrate 101 using a metal mask and then heat-melting (reflowing). Is the method.
- the solder ball method is a method of forming solder bumps 106 by placing solder balls on a plurality of pads 104 and performing reflow.
- JP 2004-95864 A (FIG. 1 etc.) Japanese Patent No. 4502690 (FIG. 4 etc.)
- the present invention has been made in view of the above problems, and an object of the present invention is to provide a wiring board capable of improving reliability by reliably preventing the progress of cracks in solder bumps. is there.
- a substrate main body having a substrate main surface and a substrate back surface, and solder bumps arranged on the substrate back surface and used for connection to the mother substrate are formed on the surface.
- a wiring board comprising a plurality of possible pads and a solder resist that covers the back surface of the substrate and has a plurality of openings that expose the plurality of pads.
- a convex portion having a surface and an outer surface is formed, and the convex portion is set such that a height from the surface of the pad to the tip surface is smaller than a depth of the opening portion, and the outer surface is an inner portion of the opening portion.
- the wiring board of means 1 even if a crack is generated in the solder bump and the generated crack progresses along the interface between the solder bump and the pad, the progress of the crack is certain by reaching the convex portion. Can be suppressed. As a result, it is possible to prevent disconnection of the electrical path constituted by the solder bumps, thereby improving the reliability of the manufactured wiring board.
- the type of the substrate main body constituting the wiring board is not particularly limited and is arbitrary.
- a resin substrate main body or the like is used.
- the resin substrate main body include a substrate main body made of EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin), PPE resin (polyphenylene ether resin) and the like.
- a substrate body made of a composite material of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) may be used.
- a substrate body made of a composite material of these resins and organic fibers such as polyamide fibers may be used.
- a substrate body made of a resin-resin composite material in which a thermosetting resin such as an epoxy resin is impregnated with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used.
- a thermosetting resin such as an epoxy resin
- a three-dimensional network fluorine-based resin base material such as continuous porous PTFE
- various ceramics can be selected.
- the structure of the wiring board is not particularly limited, and examples thereof include a build-up multilayer wiring board having a build-up layer on one or both sides of the core board, and a coreless wiring board having no core board.
- a plurality of pads constituting the wiring board are arranged on the back surface of the board.
- the pad can be formed of a conductive metal material or the like.
- the metal material constituting the pad include gold, silver, copper, iron, cobalt, nickel, and the like.
- the pad may be formed mainly of copper. In this case, the resistance of the pad can be reduced and the conductivity of the pad can be improved as compared with the case where the pad is mainly formed of other materials.
- the pad is preferably formed by plating. In this way, the pad can be formed with high accuracy and uniformity. If the pads are formed by reflowing a metal paste, it is difficult to form the pads with high accuracy and uniformity, which may cause variations in the height of individual pads.
- the solder resist constituting the wiring board is made of a resin having insulating properties and heat resistance, and functions as a protective film for protecting the back surface of the substrate by covering the back surface of the substrate.
- Specific examples of the solder resist include a solder resist made of an epoxy resin or a polyimide resin.
- examples of the shape of the plurality of openings formed in the solder resist in a plan view include a circular shape in plan view, an elliptical shape in plan view, a triangular shape in plan view, a rectangular shape in plan view, and a square shape in plan view. .
- the convex portion constituting the wiring board is formed on a part of the surface of the pad.
- the material constituting the convex portion include copper, silver, iron, cobalt, nickel, and the like, and in particular, the material may be formed mainly of copper.
- the resistance of the convex portion can be reduced and the conductivity of the convex portion can be improved as compared with the case where the convex portion is mainly formed of another material.
- the convex portion may be formed mainly of the same conductive material as the pad. In this way, it is not necessary to prepare a material different from the pad when forming the convex portion. Therefore, since the material necessary for manufacturing the wiring board is reduced, the cost of the wiring board can be reduced.
- the height of the convex portion from the surface of the pad to the tip surface is set to be smaller than the depth of the opening, and the convex portion is arranged in the opening so that the outer surface faces the inner surface of the opening. It is similar to the shape of the opening in plan view.
- examples of the shape of the convex portion include a cylindrical shape, an elliptical shape, a cylindrical shape, a triangular prism shape, a triangular pyramid shape, a quadrangular prism shape, a quadrangular pyramid shape, and a spherical shape.
- examples of the shape of the projection in plan view include a circular shape in plan view, an elliptical shape in plan view, a triangular shape in plan view, and a rectangular shape in plan view.
- the projection and the opening are both in plan view circular shape, plan view elliptic shape, plan view triangle shape, plan view
- forming a rectangular shape when both the convex part and the opening form an angled shape (triangular shape in plan view, rectangular shape in plan view, etc.), that is, the convex part has a plurality of outer surfaces and the same number of openings as the outer surface.
- the inner side surface is provided, the outer side surface and the inner side surface are preferably arranged so as to face each other and parallel to each other.
- the convex portion is disposed in the opening portion so that the outer surface approaches the inner surface of the opening portion. If it does in this way, since it will come to a convex part as soon as a crack progresses, progress of a crack can be stopped quickly. Moreover, it is preferable that the size of the gap between the outer surface and the inner surface of the opening is uniform. If it does in this way, even if a crack progresses from which part of the perimeter part of a solder bump, since it reaches a convex part immediately, progress of a crack can be stopped more certainly. Further, the convex portion may have a rounded shape at the boundary portion between the tip surface and the outer surface.
- the convex portion As a method of forming the convex portion, a method of forming the convex portion by plating or the like can be mentioned. In this case, if the convex portion has a columnar shape, the convex portion can be easily formed by plating. Moreover, when a convex part is formed mainly, for example with copper, the convex part may be formed by copper plating. In this way, the conductivity of the convex portion is improved as compared with the case where the convex portion is formed of, for example, a conductive paste.
- a method of forming the convex portion by printing a conductive paste on the pad, or a method of forming the convex portion by performing only the step of attaching a conductive member on the pad.
- a method of forming a convex portion by applying a plate material having conductivity higher than that of the convex portion on the pad and then etching the plate material may be used.
- the surface of the pad, the tip surface, and the outer surface may be continuously covered with a plating layer.
- the solder is easily adhered to the surface of the pad and the surface of the convex portion (tip surface and outer surface), so that the solder bump can be reliably formed.
- a plurality of convex portions exist on the back side of the substrate, and at least a part of the plurality of convex portions may be alignment marks.
- at least a part of the convex portion can be effectively used as an alignment mark used for alignment of components and the like.
- the convex portion that becomes the alignment mark and the convex portion that does not become the alignment mark can be formed in the same process, the manufacturing cost of the wiring board can be kept low.
- the shape of the alignment mark in plan view may be different from the shape of the projection for connecting the mother board in plan view. In this way, the alignment mark can be easily recognized when performing alignment.
- solder bumps used for connection to the mother board can be formed on the surface of the pad.
- a solder material used for a solder bump For example, a tin lead eutectic solder (Sn / 37Pb: Melting
- Sn / Pb solder other than tin-lead eutectic solder for example, solder having a composition of Sn / 36Pb / 2Ag (melting point 190 ° C.) may be used.
- solder In addition to the above lead-containing solder, Sn-Ag solder, Sn-Ag-Cu solder, Sn-Ag-Bi solder, Sn-Ag-Bi-Cu solder, Sn-Zn solder It is also possible to select lead-free solder such as Sn—Zn—Bi solder.
- solder bumps may be formed on the surfaces of the convex portions arranged in at least one of the plurality of openings. In this way, cracks are generated in the solder bumps, and even if the generated cracks progress along the interface between the solder bumps and the pads, the progress of the cracks is reliably suppressed by reaching the convex portions. As a result, it is possible to prevent disconnection of the electrical path constituted by the solder bumps, thereby improving the reliability of the manufactured wiring board.
- FIG. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention.
- the schematic plan view which shows a wiring board.
- the principal part sectional view showing the 1st pad and the 1st convex part.
- Explanatory drawing which shows the manufacturing method of a wiring board.
- Explanatory drawing which shows the manufacturing method of a wiring board.
- Sectional drawing which shows the principal part which shows the problem in a prior art.
- the wiring board 10 of this embodiment is a wiring board for mounting an IC chip.
- the substrate body 11 constituting the wiring substrate 10 has a substantially rectangular plate shape having a substrate main surface 12 (upper surface in FIG. 1) and a substrate rear surface 13 (lower surface in FIG. 1).
- the substrate body 11 includes a substantially rectangular plate-shaped core substrate 21, a main surface side buildup layer 31 formed on the core main surface 22 of the core substrate 21, and a back surface formed on the core back surface 23 of the core substrate 21. And a side buildup layer 32.
- the core substrate 21 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm length ⁇ 25 mm width ⁇ 1.0 mm thickness.
- the core substrate 21 has a thermal expansion coefficient in the plane direction (XY direction) of 10 to 30 ppm / ° C. (specifically, 18 ppm / ° C.).
- the thermal expansion coefficient of the core substrate 21 is an average value of measured values between 0 ° C. and the glass transition temperature (Tg).
- Through-hole conductors 24 are formed at a plurality of locations on the core substrate 21. The through-hole conductor 24 connects and connects the core main surface 22 side and the core back surface 23 side of the core substrate 21.
- the inside of the through-hole conductor 24 is filled with a closing body 25 such as an epoxy resin.
- a conductor layer 41 made of copper is patterned on the core main surface 22 and the core back surface 23 of the core substrate 21, and each conductor layer 41 is electrically connected to the through-hole conductor 24.
- the main surface side buildup layer 31 is formed by alternately laminating two resin insulating layers 33 and 35 made of thermosetting resin (epoxy resin) and a conductor layer 42 made of copper. It has a structure.
- the thermal expansion coefficient of the resin insulating layers 33 and 35 is about 10 to 60 ppm / ° C. (specifically, about 30 ppm / ° C.).
- the thermal expansion coefficient of the resin insulating layers 33 and 35 is an average value of measured values between 30 ° C. and the glass transition temperature (Tg).
- terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin insulating layer 35.
- the surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37.
- An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37.
- a plurality of solder bumps 45 are provided on the surface of the terminal pad 44.
- Each solder bump 45 is electrically connected to a surface connection terminal 52 of an IC chip 51 having a rectangular flat plate shape.
- an area including the terminal pads 44 and the solder bumps 45 is an IC chip mounting area 53 on which the IC chip 51 can be mounted.
- the IC chip mounting area 53 is set on the surface of the main surface side buildup layer 31.
- via conductors 43 and 47 are provided in the resin insulation layers 33 and 35, respectively. These via conductors 43 and 47 electrically connect the conductor layer 42 and the terminal pad 44 to each other.
- the back surface side buildup layer 32 has substantially the same structure as the main surface side buildup layer 31 described above. That is, the back-side buildup layer 32 has a structure in which two resin insulating layers 34 and 36 made of a thermosetting resin (epoxy resin) and a conductor layer 42 are alternately laminated.
- the thermal expansion coefficients of 34 and 36 are about 10 to 60 ppm / ° C. (specifically, about 30 ppm / ° C.).
- a first pad 61 having a circular shape in a plan view is formed on the substrate back surface 13 of the wiring substrate 10 (on the lower surface of the second resin insulating layer 36).
- a plurality are arranged vertically and horizontally along the surface direction.
- Each first pad 61 is electrically connected to the conductor layer 42 via the via conductor 43.
- the outer diameter A1 of each first pad 61 is larger than the outer diameter of the via conductor 43 (50 ⁇ m to 100 ⁇ m in this embodiment) (300 ⁇ m to 700 ⁇ m in this embodiment). Is set.
- the thickness A2 of each first pad 61 in the present embodiment is set to 10 ⁇ m or more and 30 ⁇ m or less.
- a first convex portion 71 having a circular shape in plan view is fixed to a central portion of the lower surface 62 (front surface) of each first pad 61.
- the first convex portion 71 is formed separately from the first pad 61.
- a plurality of first convex portions 71 exist on the substrate rear surface 13 side, and are arranged one by one with respect to one first pad 61. Therefore, the number of first protrusions 71 is equal to the number of first pads 61.
- the first protrusion 71 is a copper post formed mainly of copper, which is the same conductive material as the first pad 61.
- each first convex portion 71 has a substantially rectangular cross section having a tip surface 72 and an outer surface 73. And the 1st convex part 71 has comprised the shape where the boundary part of the front end surface 72 and the outer surface 73 was rounded.
- the outer diameter A3 of each first protrusion 71 is set smaller than the outer diameter A1 (300 ⁇ m or more and 700 ⁇ m or less) of the first pad 61, and is set to 200 ⁇ m or more and 600 ⁇ m or less in this embodiment.
- the first protrusion 71 has a height A4 from the lower surface 62 to the tip surface 72 of the first pad 61 that is set to be greater than the thickness A2 (10 ⁇ m or more and 30 ⁇ m or less) of the first pad 61. In the embodiment, it is set to 15 ⁇ m or more and 35 ⁇ m or less.
- the central axis of the first convex portion 71 coincides with the central axis C ⁇ b> 1 of the first pad 61.
- the “center axis C1” refers to an axis that passes through a location that is the center of the first pad 61 in plan view.
- the plating layer 74 includes a nickel layer, a palladium layer, and a gold layer.
- the nickel layer is a plating layer formed by coating a part of the surface of the first pad 61 and the surface of the first protrusion 71 with electroless nickel plating.
- the palladium layer is a plating layer formed by coating the surface of the nickel layer with electroless palladium plating.
- the gold layer is a plating layer formed by coating the surface of the nickel layer with electroless gold plating.
- the 1st pad 61 and the 1st convex part 71 are directly connected, without interposing inclusions, such as a plating layer.
- the plating layer 74 of this embodiment has a structure consisting of a nickel layer, a palladium layer, and a gold layer, the layer structure can be changed as appropriate.
- second pads 63 each having a triangular shape in plan view are disposed on the outer peripheral portion (four corners) on the substrate back surface 13 of the wiring substrate 10.
- the outer diameter B1 (maximum diameter) of each second pad 63 is set larger than the outer diameter A1 (300 ⁇ m or more and 700 ⁇ m or less) of each first pad 61. It is set to 400 ⁇ m or more and 800 ⁇ m or less.
- the thickness B2 of each second pad 63 in the present embodiment is set to 10 ⁇ m or more and 30 ⁇ m or less.
- a second convex portion 75 having a triangular shape in plan view is fixed to the central portion of the lower surface 64 (front surface) of each second pad 63.
- the second protrusion 75 is formed separately from the second pad 63.
- a plurality of second convex portions 75 exist on the substrate back surface 13 side, and are arranged one by one with respect to one second pad 63. Therefore, the number of second protrusions 75 is equal to the number of second pads 63.
- the second protrusion 75 is a copper post formed mainly of copper, which is the same conductive material as the second pad 63.
- each second convex portion 75 has a substantially rectangular cross section having a tip surface 76 and an outer surface 77. And the 2nd convex part 75 has comprised the shape where the boundary part of the front end surface 76 and the outer surface 77 was rounded.
- the outer diameter B3 (maximum diameter) of each second protrusion 75 is set smaller than the outer diameter B1 (400 ⁇ m or more and 800 ⁇ m or less) of the second pad 63, and is set to 200 ⁇ m or more and 600 ⁇ m or less in this embodiment. Yes.
- the second protrusion 75 has a height B4 from the lower surface 64 to the tip surface 76 of the second pad 63 that is greater than the thickness B2 (10 ⁇ m or more and 30 ⁇ m or less) of the second pad 63 and the first protrusion It is set equal to the height A4 of the portion 71, and in this embodiment, it is set to 15 ⁇ m or more and 35 ⁇ m or less.
- the central axis of the second protrusion 75 coincides with the central axis C ⁇ b> 2 of the second pad 63.
- the “center axis C2” refers to an axis that passes through a location that is the center of the second pad 63 in plan view.
- the plating layer 78 includes a nickel layer, a palladium layer, and a gold layer, and has the same layer structure as the plating layer 74. Moreover, the 2nd pad 63 and the 2nd convex part 75 are directly connected, without interposing inclusions, such as a plating layer.
- the plating layer 78 of this embodiment has a structure consisting of a nickel layer, a palladium layer, and a gold layer, the layer structure can be changed as appropriate.
- the substrate rear surface 13 (the lower surface of the resin insulating layer 36) of the wiring substrate 10 is almost entirely covered with a solder resist 81.
- the solder resist 81 includes a plurality of first openings 82 that expose the first pads 61 and the first protrusions 71, and a plurality of second openings 83 that expose the second pads 63 and the second protrusions 75. Is formed.
- the first opening 82 has a circular shape in plan view, and the inner diameter is set to be 300 ⁇ m or more and 700 ⁇ m or less. Accordingly, the shape of the first opening 82 in plan view is similar to the shape of the first convex portion 71 in plan view.
- the first convex portion 71 is disposed in the first opening 82 so that the outer surface 73 faces the inner surface of the first opening 82, and the outer surface 73 is on the inner surface of the first opening 82. It arrange
- the size of the gap S1 between the outer surface 73 and the inner surface of the first opening 82 (about 50 ⁇ m in this embodiment) is uniform. Further, the height A4 (15 ⁇ m or more and 35 ⁇ m or less) of the first protrusion 71 is set to be smaller than the depth of the first opening 82 (20 ⁇ m or more and 40 ⁇ m or less in the present embodiment).
- the second opening 83 has a triangular shape in plan view, and the inner diameter (maximum diameter) is set to be 400 ⁇ m or more and 800 ⁇ m or less. Therefore, the shape of the second opening 83 in plan view is similar to the shape of the second convex portion 75 in plan view.
- the second convex portion 75 is disposed in the second opening 83 such that the outer surface 77 faces the inner surface of the second opening 83, and the outer surface 77 is formed on the inner surface of the second opening 83. It arrange
- the 2nd convex part 75 has the uniform magnitude
- the height B4 (15 ⁇ m or more and 35 ⁇ m or less) of the second convex portion 75 is set to be smaller than the depth of the second opening 83 (20 ⁇ m or more and 40 ⁇ m or less in the present embodiment).
- each first convex portion 71 is a convex portion for connecting the mother board 91
- each second convex portion 75 is a convex portion serving as an alignment mark.
- the shape of the second convex portion 75 in plan view (in this embodiment, a triangular shape in plan view) is different from the shape of the first convex portion 71 in plan view (in the present embodiment, a circular shape in plan view).
- This alignment mark is recognized by detecting the outer peripheral edge of the distal end surface 72 of the second convex portion 75 and the opening edge of the first opening 82 with a detection device (not shown).
- solder bumps 84 used for connection to a mother board 91 are formed on the surface of the first pad 61. More specifically, a solder bump 84 is formed on the surface (tip surface 72 and outer surface 73) of the first convex portion 71 disposed in the first opening 82 among the openings 82 and 83. .
- the solder bump 84 covers a region exposed in the first opening 82 on the lower surface 62 of the first pad 61 and covers the entire surface of the first convex portion 71. For this reason, the first pad 61 and the first convex portion 71 are covered with the solder bumps 84 and cannot be seen.
- the height of the solder bump 84 is higher than the height A4 (15 ⁇ m or more and 35 ⁇ m or less) of the first protrusion 71, and is set to 300 ⁇ m or more and 700 ⁇ m or less in the present embodiment.
- the solder bumps 84 of the present embodiment are made of Sn—Ag solder that is lead-free solder. As shown in FIG. 3, each first pad 61 is connected to a terminal 92 on the motherboard 91 side via a solder bump 84. That is, the solder bumps 84 are so-called BGA bumps used for electrical connection with the terminals 92 on the mother board 91 side.
- a substrate preparation process for preparing the substrate body 11 is performed. Specifically, first, a copper clad laminate in which copper foil is pasted on both surfaces of a substrate made of glass epoxy is prepared. And drilling is performed using a drill machine, and the through-hole which penetrates the front and back of a copper clad laminated board is previously formed in the predetermined position. And the through-hole conductor 24 is formed in a through-hole by performing electroless copper plating and electrolytic copper plating with respect to the inner surface of a through-hole. Thereafter, the cavity of the through-hole conductor 24 is filled with an insulating resin material (epoxy resin) to form the closing body 25.
- an insulating resin material epoxy resin
- the copper plating copper and copper foil are subjected to, for example, a subtractive method. To pattern. As a result, an intermediate product of the core substrate 21 on which the conductor layer 41 and the through-hole conductor 24 are formed is obtained.
- the intermediate product of the core substrate 21 is a multi-piece core substrate in which a plurality of regions to be the core substrate 21 are arranged vertically and horizontally along the plane direction.
- the main surface side buildup layer 31 is formed on the core main surface 22 of the core substrate 21, and the back surface side buildup layer 32 is formed on the core back surface 23 of the core substrate 21.
- a resin insulating layer 33 is formed by applying (sticking) a thermosetting epoxy resin on the core main surface 22.
- a resin insulating layer 34 is formed by depositing (attaching) a thermosetting epoxy resin on the core back surface 23.
- a thermosetting epoxy resin a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer (LCP: Liquid Crystalline Polymer) may be deposited.
- laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form a via hole at a position where the via conductor 47 is to be formed.
- a via hole penetrating the resin insulating layer 33 is formed, and the surface of the conductor layer 41 is exposed.
- a via hole penetrating the resin insulating layer 34 is formed to expose the surface of the conductor layer 41.
- electrolytic copper plating is performed according to a conventionally known method to form a via conductor 47 inside the via hole, and to form a conductor layer 42 on the resin insulating layers 33 and 34.
- thermosetting epoxy resin is deposited on the resin insulation layers 33 and 34 to form resin insulation layers 35 and 36.
- a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer may be deposited.
- a via hole is formed in the resin insulating layer 35 at a position where the via conductor 43 is to be formed by a laser processing machine or the like.
- electrolytic copper plating is performed according to a conventionally known method to form a via conductor 43 in the via hole of the resin insulating layer 35 and to form a terminal pad 44 on the resin insulating layer 35. At this point, the substrate body 11 is completed.
- pads 61 and 63 are formed on the substrate back surface 13 by plating on the outermost resin insulation layer 36 having the substrate back surface 13 (see FIG. 5).
- the pads 61 and 63 are patterned on the resin insulating layer 36 by performing a semi-additive method. Specifically, first, via processing is performed to form a via hole at a predetermined position of the resin insulating layer 36, and then desmear processing for processing smear in each via hole is performed. Next, after electroless copper plating is performed on the surface of the resin insulation layer 36, a dry film is laminated on the resin insulation layer 36 to form a first plating resist (not shown). Further, laser processing is performed on the first plating resist using a laser processing machine.
- a first opening whose inner diameter is set larger than the outer diameter of the via hole is formed in the resin insulating layer 36 at a position communicating with the via hole, and at the resin insulating layer 36 a position not communicating with the via hole.
- a second opening is formed.
- electrolytic copper plating is performed to form a via conductor 43 in each via hole, and the upper surface (substrate back surface 13) of the resin insulating layer 36 exposed through the first opening and the first opening.
- a first pad 61 mainly composed of copper (copper layer) is formed on the upper surface of the exposed via conductor 43.
- a second pad 63 mainly composed of copper (copper layer) is formed on the upper surface (substrate back surface 13) of the resin insulating layer 36 exposed through the second opening. Thereafter, the first plating resist is peeled off and an unnecessary electroless copper plating layer is removed.
- the thickness of the copper layer in the present embodiment is set to 10 ⁇ m or more and 30 ⁇ m or less.
- the copper layer of the present embodiment is formed by plating, but can be formed by other methods such as sputtering and CVD. However, in order to obtain a required height (10 ⁇ m or more and 30 ⁇ m or less) particularly in the copper layer, it is preferably formed by plating.
- a solder resist 81 is formed so as to cover the back surface 13 of the substrate by applying and curing a photosensitive epoxy resin on the resin insulating layer 36 on which the pads 61 and 63 are formed (FIG. 6). reference).
- exposure and development are performed in a state where a predetermined mask is disposed, and the openings 82 and 83 are patterned in the solder resist 81 (see FIG. 6).
- the convex portions 71 and 75 are formed on the lower surfaces 62 and 64 of the pads 61 and 63 by plating the pads 61 and 63 (see FIG. 7). Specifically, first, a dry film is laminated on the surface of the solder resist 81 to form a second plating resist (not shown). Next, laser processing using a laser processing machine is performed on the second plating resist. As a result, an opening that exposes the center of the lower surfaces 62 and 64 of the pads 61 and 63 is formed. Then, electrolytic copper plating is performed on the central portions of the lower surfaces 62 and 64 exposed through the openings. At this time, convex portions 71 and 75 mainly composed of copper (copper layer) are formed.
- the second plating resist is peeled off.
- the thickness of the copper layer constituting the convex portions 71 and 75 is set to 15 ⁇ m or more and 35 ⁇ m or less.
- the copper layer is formed by electrolytic plating, but it can also be formed by other methods such as electroless plating, sputtering, and CVD. However, in order to obtain a required height (15 ⁇ m or more and 35 ⁇ m or less) particularly in the copper layer, it is preferably formed by plating.
- electroless nickel plating is performed to form a nickel layer on the surfaces of the pads 61 and 63 (lower surfaces 62 and 64) and the surfaces of the convex portions 71 and 75 (tip surfaces 72 and 76 and outer surfaces 73 and 77).
- electroless palladium plating is performed to form a palladium layer on the nickel layer.
- electroless gold plating is performed to form a gold layer on the palladium layer.
- the thickness of the nickel layer, the palladium layer, and the gold layer is set to 0.01 ⁇ m or more and 15 ⁇ m or less.
- metal layer of this embodiment are formed by plating, it is also possible to form by other methods, such as a sputtering method and CVD.
- solder bumps 84 are formed on the plurality of first pads 61 formed on the substrate back surface 13 side of the wiring substrate 10. Specifically, each solder ball is placed on each first pad 61 using a solder ball mounting device (not shown), and then the solder ball is heated to a predetermined temperature to be heated and melted (reflowed). Solder bumps 84 are formed on the pads 61. Further, solder bumps 45 are formed on the plurality of terminal pads 44 formed on the substrate main surface 12 side of the wiring substrate 10. Specifically, after solder balls are arranged on each terminal pad 44 using a solder ball mounting device, the solder balls are heated to a predetermined temperature and heated and melted (reflowed). Solder bumps 45 are formed. At this point, the intermediate product of the wiring board 10 is completed.
- the intermediate product of the wiring board 10 is divided using a conventionally known cutting device or the like. As a result, the product parts are divided, and a large number of wiring boards 10 which are individual products are obtained simultaneously (see FIG. 1).
- an IC chip mounting process is performed. Specifically, first, the IC chip 51 is placed on the substrate main surface 12 side of the wiring substrate 10. At this time, the surface connection terminals 52 arranged on the bottom surface side of the IC chip 51 are placed on the solder bumps 45 arranged on the wiring board 10 side. Then, each solder bump 45 is heated and melted (reflowed) by heating to a temperature of about 230 ° C. to 260 ° C., whereby the terminal pad 44 is flip-chip connected to the surface connection terminal 52, and the IC chip is connected to the wiring substrate 10. 51 is mounted (see FIG. 1).
- the first convex portion 71 is fixed to a part of the lower surface 62 of the first pad 61, and has a convex shape as a whole. Therefore, if the solder bump 84 that covers the surface (the lower surface 62) of the first pad 61 and the surface (the front end surface 72 and the outer surface 73) of the first convex portion 71 is formed, the first convex portion 71 is formed in the solder bump 84. It will be in the fitted state. As a result, a contact area between the first pad 61 and the first protrusion 71 and the solder bump 84 is ensured.
- the adhesion strength between the surface of the first pad 61 and the solder bump 84 and the adhesion strength between the surface of the first protrusion 71 and the solder bump 84 can be increased, and as a result, the individual first pad 61 and the mother board can be increased. Connection failure with 91 can be prevented. That is, the reliability of the wiring board 10 can be further improved by providing the first pads 61 and the first protrusions 71 suitable for connection with the mother board 91.
- the height A4 from the lower surface 62 of the first pad 61 to the tip surface 72 in the first convex portion 71 is set to be smaller than the depth of the first opening portion 82.
- the shape of the first protrusion 71 for connecting the motherboard 91 in plan view (circular shape in plan view) and the shape of the second protrusion 75 serving as an alignment mark (triangular shape in plan view) ) are different from each other, but the shapes of the projections 71 and 75 in plan view may be equal to each other.
- one convex portion 71, 75 is formed for one pad 61, 63.
- the present invention is not limited to this, and two or more convex portions may be formed.
- the convex parts 71 and 75 of the said embodiment were the conductors (copper post) formed by copper plating, the conductors formed by printing a copper paste may be sufficient.
- the plating layers 74 and 78 that cover the pads 61 and 63 and the protrusions 71 and 75 are plating layers made of a nickel layer, a palladium layer, and a gold layer.
- it may be changed to another plating layer made of a nickel layer, a gold layer, or the like.
- solder bump 84 is formed by heating and melting (reflowing) the solder ball disposed on the first pad 61.
- solder bumps may be formed by heating and melting the solder paste printed on the first pad 61.
- a plurality of the convex portions are present on the substrate rear surface side, and at least a part of the plurality of convex portions are alignment marks, and the convex portions serving as the alignment marks. Is located on the outer peripheral portion on the back side of the substrate.
- a method of manufacturing the wiring board according to the above means 1, wherein a substrate preparation step for preparing the substrate body, a pad formation step for forming the plurality of pads on the substrate back surface, and the substrate back surface A method of manufacturing a wiring board, comprising: a solder resist forming step of forming the solder resist so as to cover the surface; and a convex portion forming step of forming the convex portions on a part of the surfaces of the plurality of pads.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
11…基板本体
12…基板主面
13…基板裏面
61…パッドとしての第1パッド
62,64…パッドの表面としての下面
63…パッドとしての第2パッド
71…凸部としての第1凸部
72,76…凸部の表面としての先端面
73,77…凸部の表面としての外側面
74,78…めっき層
75…凸部としての第2凸部
81…ソルダーレジスト
82…開口部としての第1開口部
83…開口部としての第2開口部
84…はんだバンプ
91…母基板としてのマザーボード
A4,B4…パッドの表面から先端面までの高さ
S1,S2…凸部の外側面と開口部の内側面との隙間
Claims (8)
- 基板主面及び基板裏面を有する基板本体と、
前記基板裏面上に配置され、母基板との接続に用いられるはんだバンプが表面上に形成可能な複数のパッドと、
前記基板裏面を覆うとともに、前記複数のパッドを露出させる複数の開口部が形成されたソルダーレジストと
を備える配線基板であって、
前記パッドの表面の一部に、先端面及び外側面を有する凸部が形成され、
前記凸部は、
前記パッドの表面から前記先端面までの高さが前記開口部の深さよりも小さく設定され、
前記外側面が前記開口部の内側面と向かい合うように前記開口部内に配置され、
平面視の形状が前記開口部の平面視の形状と相似形をなしている
ことを特徴とする配線基板。 - 前記凸部は、前記外側面が前記開口部の内側面に接近するように前記開口部内に配置されていることを特徴とする請求項1に記載の配線基板。
- 前記凸部は、前記外側面と前記開口部の内側面との隙間の大きさが均一であることを特徴とする請求項1または2に記載の配線基板。
- 前記凸部は、前記先端面と前記外側面との境界部分が丸みを帯びた形状をなしていることを特徴とする請求項1乃至3のいずれか1項に記載の配線基板。
- 前記パッドの表面の少なくとも一部、前記先端面及び前記外側面は、めっき層によって連続的に覆われていることを特徴とする請求項1乃至4のいずれか1項に記載の配線基板。
- 前記凸部は前記基板裏面側において複数存在しており、複数の前記凸部の少なくとも一部は位置合わせ用マークであることを特徴とする請求項1乃至5のいずれか1項に記載の配線基板。
- 前記位置合わせ用マークの平面視の形状は、母基板接続用の前記凸部の平面視の形状とは異なることを特徴とする請求項6に記載の配線基板。
- 前記複数の開口部のうち少なくとも1つの前記開口部内に配置された前記凸部の表面上に、前記はんだバンプが形成されていることを特徴とする請求項1乃至7のいずれか1項に記載の配線基板。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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CN201380071660.2A CN104956477A (zh) | 2013-03-26 | 2013-12-12 | 布线基板 |
KR1020157029234A KR20150130519A (ko) | 2013-03-26 | 2013-12-12 | 배선기판 |
US14/762,185 US20150357277A1 (en) | 2013-03-26 | 2013-12-12 | Wiring substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2013-063369 | 2013-03-26 | ||
JP2013063369A JP2014192176A (ja) | 2013-03-26 | 2013-03-26 | 配線基板 |
Publications (1)
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WO2014155455A1 true WO2014155455A1 (ja) | 2014-10-02 |
Family
ID=51622554
Family Applications (1)
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PCT/JP2013/007314 WO2014155455A1 (ja) | 2013-03-26 | 2013-12-12 | 配線基板 |
Country Status (6)
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US (1) | US20150357277A1 (ja) |
JP (1) | JP2014192176A (ja) |
KR (1) | KR20150130519A (ja) |
CN (1) | CN104956477A (ja) |
TW (1) | TW201503771A (ja) |
WO (1) | WO2014155455A1 (ja) |
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JP6510349B2 (ja) * | 2015-07-27 | 2019-05-08 | 京セラ株式会社 | 配線基板 |
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JP2018018868A (ja) * | 2016-07-26 | 2018-02-01 | イビデン株式会社 | コイル基板及びその製造方法 |
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KR102679481B1 (ko) * | 2018-10-22 | 2024-07-02 | 삼성전자주식회사 | 인쇄회로기판 및 이를 포함하는 반도체 패키지 |
US10978417B2 (en) * | 2019-04-29 | 2021-04-13 | Advanced Semiconductor Engineering, Inc. | Wiring structure and method for manufacturing the same |
US11626336B2 (en) * | 2019-10-01 | 2023-04-11 | Qualcomm Incorporated | Package comprising a solder resist layer configured as a seating plane for a device |
JP2021093417A (ja) * | 2019-12-09 | 2021-06-17 | イビデン株式会社 | プリント配線板、及び、プリント配線板の製造方法 |
US20220069489A1 (en) * | 2020-08-28 | 2022-03-03 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
KR20220041430A (ko) * | 2020-09-25 | 2022-04-01 | 삼성전자주식회사 | Ubm층을 가지는 팬 아웃 반도체 패키지 |
KR20220086321A (ko) | 2020-12-16 | 2022-06-23 | 삼성전기주식회사 | 인쇄회로기판 및 전자부품 패키지 |
US20230070275A1 (en) * | 2021-09-09 | 2023-03-09 | Qualcomm Incorporated | Package comprising a substrate with a pad interconnect comprising a protrusion |
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TW201503771A (zh) | 2015-01-16 |
CN104956477A (zh) | 2015-09-30 |
KR20150130519A (ko) | 2015-11-23 |
US20150357277A1 (en) | 2015-12-10 |
JP2014192176A (ja) | 2014-10-06 |
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