WO2014061713A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2014061713A1
WO2014061713A1 PCT/JP2013/078115 JP2013078115W WO2014061713A1 WO 2014061713 A1 WO2014061713 A1 WO 2014061713A1 JP 2013078115 W JP2013078115 W JP 2013078115W WO 2014061713 A1 WO2014061713 A1 WO 2014061713A1
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Prior art keywords
layer
oxide
electrode layer
film
oxide semiconductor
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PCT/JP2013/078115
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English (en)
French (fr)
Inventor
Shunpei Yamazaki
Hideomi Suzawa
Shinya Sasagawa
Tetsuhiro Tanaka
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020157010061A priority Critical patent/KR102224946B1/ko
Priority to CN201380054450.2A priority patent/CN104704638B/zh
Publication of WO2014061713A1 publication Critical patent/WO2014061713A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials

Definitions

  • One embodiment of the invention disclosed in this specification and the like relates to a semiconductor device and a method for fabricating the semiconductor device.
  • a semiconductor device refers to all types of devices which can function by utilizing semiconductor characteristics; an electro-optical device, an image display device, a semiconductor circuit, and an electronic device are all semiconductor devices.
  • a technique by which transistors are formed using semiconductor thin .films formed over a substrate having an insulating surface has been attracting attention.
  • Such a transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device).
  • IC integrated circuit
  • image display device also simply referred to as a display device.
  • a silicon-based semiconductor material is widely known as a material for a semiconductor thin film applicable to a transistor.
  • an oxide semiconductor has been attracting attention.
  • Patent Documents 1 and 2 For example, a technique for forming a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).
  • Patent Document 1 Japanese Published Patent Application No. 2007-123861
  • Patent Document 2 Japanese Published Patent Application No. 2007-096055
  • An object of one embodiment of the present invention is to obtain a semiconductor device including an oxide semiconductor, which has favorable electrical characteristics.
  • Another object is to provide a highly reliable semiconductor device including an oxide semiconductor by suppression of a change in its electrical characteristics.
  • an oxygen vacancy can be given as one of carrier supply sources of the oxide semiconductor.
  • Many oxygen vacancies in an oxide semiconductor including a channel formation region of a transistor lead to generation of electrons in the channel formation region, which causes defects in electrical characteristics; for example, the transistor becomes normal ly-on, leakage current increases, or threshold voltage is shifted due to stress application.
  • hydrogen, silicon, nitrogen, carbon, and a metal element except for that of a main component are impurities.
  • hydrogen in the oxide semiconductor layer forms a donor level, which increases carrier density.
  • Silicon forms impurity levels in an oxide semiconductor layer. The impurity levels serve as. traps and might cause electrical characteristics of the transistor to deteriorate.
  • oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer and a gate insulating layer provided over the oxide semiconductor layer to a region where a channel is formed, whereby oxygen vacancies which might be generated in the channel are filled. Further, extraction of oxygen from the oxide semiconductor layer by a source electrode layer or a drain electrode layer in the vicinity of the channel formed in the oxide semiconductor layer is suppressed, whereby an oxygen vacancy which may be generated in the channel is suppressed.
  • a protective insulating layer serving as a barrier layer having a low hydrogen content and a low oxygen-transmitting property over a gate electrode layer is formed, so that oxygen is effectively supplied to the region where a channel is formed while desorption of oxygen from the gate insulating layer and/or the base insulating layer is suppressed.
  • oxide layers containing one or more kinds of metal elements forming the oxide semiconductor layer are provided over and under and in contact with the oxide semiconductor layer where a channel is formed.
  • the channel can be separate from the gate insulating layer.
  • an interface state is unlikely to be formed at the interface between the oxide semiconductor layer and each of the oxide layers, and thus fluctuation in electrical characteristics of the transistors, such as a threshold voltage, can be reduced.
  • the concentration of an impurity in the oxide semiconductor layer serving as a channel (serving as a main carrier path) can be reduced so that the oxide semiconductor layer is highly purified to be a highly purified intrinsic oxide semiconductor layer.
  • Obtaining a highly purified intrinsic oxide semiconductor layer refers to purifying or substantially purifying the oxide semiconductor layer to be an intrinsic or substantially intrinsic oxide semiconductor layer. Note that in this specification and the like, in the case of the substantially purified oxide semiconductor layer, the carrier density thereof is lower than 1 x 10 17 /cm 3 , lower than 1 x 10 15 /cm 3 , or lower than 1 x 10 13 /cm 3 .
  • One embodiment of the present invention is a semiconductor device including a base insulating layer containing oxygen; an island-shaped oxide stack which is provided over the base insulating layer; a first source electrode layer and a first drain electrode layer each of which is in contact with a top surface of the island-shaped oxide stack and a side face thereof in a channel length direction; a second source electrode layer and a second drain electrode layer which are provided over the first source electrode layer and the first drain electrode layer, respectively, are in contact with the top surface of the oxide stack, and formed using a metal nitride film; a gate insulating layer which is provided over the second source electrode layer and the second drain electrode layer and in contact with the top surface of the oxide stack between the second source electrode layer and the second drain electrode layer; a gate electrode layer which overlaps with the oxide stack with the gate insulating layer provided therebetween; and a protective insulating layer which is provided over and in contact with the gate insulating layer and the gate electrode layer.
  • the oxide stack includes an oxide semiconductor layer in which at least a channel is formed; a first oxide layer which is provided between the oxide semiconductor layer and the base insulating layer; and a second oxide layer which is provided between the oxide semiconductor layer and the gate insulating layer.
  • the base insulating layer and the gate insulating layer are in contact with each other outside the island-shaped oxide stack.
  • the protective insulating layer has a lower oxygen-transmitting property than the gate insulating layer.
  • Another embodiment of the present invention is a semiconductor device including a base insulating layer containing oxygen; an island-shaped oxide stack which is provided over the base insulating layer; a first source electrode layer and a first drain electrode layer each of which is in contact with a top surface of the island-shaped oxide stack and a side face thereof in a channel length direction; a second source electrode layer and a second drain electrode layer which are provided over the first source electrode layer and the first drain electrode layer, respectively, are in contact with the top surface of the oxide stack, and formed using a metal nitride film; a gate insulating layer which is provided over the second source electrode layer and the second drain electrode layer and is in contact with the top surface of the oxide stack between the second source electrode layer and the second drain electrode layer; a gate electrode layer which overlaps with the oxide stack, part of the second source electrode layer, and part of the second drain electrode layer with the gate insulating layer provided therebetween; and a protective insulating layer which is provided over and in contact with the gate insulating layer and the gate electrode layer
  • the oxide stack includes an oxide semiconductor layer in which at least a channel is formed; a first oxide layer which is provided between the oxide semiconductor layer and the base insulating layer; and a second oxide layer which is provided between the oxide semiconductor layer and the gate insulating layer.
  • the base insulating layer and the gate insulating layer are in contact with each other outside the island-shaped oxide stack.
  • the protective insulating layer has a lower oxygen-transmitting property than the gate insulating layer.
  • the oxide semiconductor layer, the first oxide layer, and the second oxide layer be each formed using an In- -Zn oxide ( is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), and that an atomic ratio of to In (hereinafter, also referred to as indium) in each of the first oxide layer and the second oxide layer be higher than that in the oxide semiconductor layer.
  • an In- -Zn oxide is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf
  • indium an atomic ratio of to In
  • the oxide semiconductor layer include a crystal part and that a c-axis of the crystal part be parallel to a normal vector of a surface of the oxide semiconductor layer.
  • the first source electrode layer and the first drain electrode layer are each formed using a material which is bonded to oxygen more easily than a material used for the second source electrode layer and the second drain electrode layer.
  • the concentration of hydrogen in the protective insulating layer is preferably lower than 5 x lO 19 cm -3 .
  • a semiconductor device including an oxide semiconductor can have favorable electrical characteristics.
  • a highly reliable semiconductor device including an oxide semiconductor by suppression of a change in its electrical characteristics can be provided.
  • FIGS. 1A to ID are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device
  • FIGS. 2A to 2C are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device; .
  • FIGS. 3A to 3D are cross-sectional views illustrating one embodiment of a semiconductor device
  • FIGS. 4A to 4C are cross-sectional views illustrating an example of a method for fabricating a semiconductor device
  • FIGS. 5A to 5D are cross-sectional views illustrating an example of the method for fabricating a semiconductor device
  • FIGS. 6A and 6B illustrate a band structure of an oxide stack
  • FIGS. 7A and 7B illustrate a band structure of an oxide stack
  • FIG. 8 illustrates a band structure of an oxide stack
  • FIGS. 9A to 9C are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device
  • FIG. 10 is a conceptual view illustrating a stacked-Iayer structure of a transistor
  • FIGS. 11 A and 1 IB show SIMS measurement results
  • FIGS. 12A and 12B show SIMS measurement results
  • FIGS. 13A and 13B show SIMS measurement results
  • FIGS. 14A and 14B show SIMS measurement results
  • FIGS. 15A and 15B show measurement results of sheet resistances
  • FIG. 16 shows a measurement result of sheet resistance
  • FIGS. 17A and 17B show measurement results of sheet resistances
  • FIGS. 18A and 18B show TDS analysis results
  • FIG. 19 is a cross-sectional view illustrating one embodiment of a semiconductor device
  • FIGS. 20A and 20B are circuit diagrams each illustrating a semiconductor device of one embodiment of the present invention.
  • FIGS. 21 A to 21 C are circuit diagrams and a conceptual diagram of a semiconductor device of one embodiment of the present invention.
  • FIG. 22 is a block diagram of a semiconductor device of one embodiment of the present invention.
  • FIG. 23 is a block diagram of a semiconductor device of one embodiment of the present invention.
  • FIG. 24 is a block diagram of a semiconductor device of one embodiment of the present invention.
  • FIGS. 25A and 25B are views illustrating an electronic device in which a semiconductor device of one embodiment of the present invention can be used.
  • source and drain of a transistor may be switched in the case where transistors of different polarities are employed or in the case where the direction of a current flow changes in a circuit operation. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.
  • FIG. 10 is a conceptual view of an example of the stacked-layer structure.
  • the stacked-layer structure of the semiconductor device includes an oxide stack 404 between a base insulating layer 402 and a gate insulating layer 410. Further, the oxide stack 404 includes a first oxide layer 404a, an oxide semiconductor layer 404b, and a second oxide layer 404c.
  • Each of the first oxide layer 404a and the second oxide layer 404c is an oxide layer containing one or more kinds of metal elements which form the oxide semiconductor layer 404b.
  • the oxide semiconductor layer 404b includes a layer represented by an In-M-Zn oxide, which contains at least indium, zinc, and M (M is a metal element such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf)-
  • M is a metal element such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf
  • the oxide semiconductor layer 404b preferably contains indium because the carrier mobility of a transistor is increased.
  • the first oxide layer 404a under the oxide semiconductor layer 404b includes an oxide layer which is represented by an In-M-Zn oxide (M is a metal element such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) and in which the atomic ratio of M to In is higher than that in the oxide semiconductor layer 404b.
  • M is a metal element such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf
  • the amount of any of the above elements in the first oxide layer 404a in an atomic ratio is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more as much as that in the oxide semiconductor layer 404b in an atomic ratio.
  • Any of the above elements is more strongly bonded to oxygen than indium, and thus has a function of suppressing generation of an oxygen vacancy in the oxide layer. That is, an oxygen vacancy is more unlikely to be generated in the first oxide layer 404a than in the oxide semiconductor layer 404b.
  • the second oxide layer 404c over the oxide semiconductor layer 404b includes an oxide layer which is represented by an In-M-Zn oxide (M is a metal element such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) and in which the atomic ratio of M to In is higher than that in the oxide semiconductor layer 404b.
  • M is a metal element such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf
  • the amount of any of the above elements in the second oxide layer 404c in an atomic ratio is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more as much as that in the oxide semiconductor layer 404b in an atomic ratio.
  • the oxide semiconductor layer 404b, and the second oxide layer 404c is an In-M-Zn oxide containing at least indium, zinc, and M
  • M is a metal element such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf
  • the first oxide layer 404a has an atomic ratio of In to M and Zn which is ⁇ : ⁇ :Z]
  • the oxide semiconductor layer 404b has an atomic ratio of In to M and Zn which is xi'-yi-zi
  • the second oxide layer 404c has an atomic ratio of In to M and Zn which is x3-.y .z3, each of y ⁇ lx ⁇ and 3/.X3 is preferably larger than ⁇ / ⁇ .
  • Each of y ⁇ lx ⁇ and 3 ⁇ 4/.x:3 is 1.5 times or more as large as 2 / 2 , preferably 2 times or more, further preferably 3 times or more as large as 3 ⁇ 4/JC2-
  • a transistor can have stable electrical characteristics.
  • ⁇ is preferably equal to 2 or less than
  • the first oxide layer 404a is an In-M-Zn oxide
  • the proportion of In be less than 50 atomic% and the proportion of M be greater than or equal to 50 atomic%
  • the oxide semiconductor layer 404b is an In-M-Zn oxide
  • the proportion of In be greater than or equal to 25 atomic% and the proportion of M be less than 75 atomic%, and it is more preferable that, in the atomic ratio between In and M, the proportion of In be greater than or equal to 34 atomic% -and the -proportion-of- -be less than -66- atomic%;
  • the second oxide layer 404c is an In-M-Zn oxide
  • the constituent elements of the first oxide layer 404a and the second oxide layer 404c may be different from each other, or their constituent elements may be the same at the same atomic ratios or different atomic ratios.
  • the oxide semiconductor layer 404b for example, an oxide semiconductor containing indium, zinc, and gallium can be used.
  • the thickness of the first oxide layer 404a is greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm.
  • the thickness of the oxide semiconductor layer 404b is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 50 nm.
  • each of the first oxide layer 404a and the second oxide layer 404c contain one or more kinds of metal elements forming the oxide semiconductor layer 404b and be formed using an oxide semiconductor whose bottom of the conduction band is closer to a vacuum level than that of the oxide semiconductor layer 404b by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, l eV or less, 0.5 eV or less, or 0.4 eV or less in an energy between the vacuum level and the bottom of the conduction band.
  • a band structure of the oxide stack 404 is described.
  • the stack is referred to as an oxide stack, and the layers forming the stack are referred to as a first oxide layer, an oxide semiconductor layer, and a second oxide layer.
  • the thickness of each of the first oxide layer, the oxide semiconductor layer, and the second oxide layer was 10 nm.
  • the energy gap was measured with use of a spectroscopic ellipsometer (UT-300 manufactured by HORJBA Jobin Yvon). Further, the energy gap in the vicinity of an interface between the first oxide layer and the oxide semiconductor layer was 3 eV, and the energy gap in the vicinity of an interface between the second oxide layer and the oxide semiconductor layer was 3 eV.
  • FIG. 6A the energy difference between a vacuum level and a top of a valence band of each layer was measured while the oxide stack was etched from the second oxide layer side, and was plotted.
  • the energy difference between the vacuum level and the top of the valence band was measured using an ultraviolet photoelectron spectroscopy (UPS) device (VersaProbe manufactured by UL VAC-PHI, Inc.).
  • UPS ultraviolet photoelectron spectroscopy
  • FIG. 7A shows the case where silicon oxide films are provided in contact with the first oxide layer and the second oxide layer.
  • Ev represents energy of the vacuum level
  • Ecll and EcI2 represent energy at the bottom of the conduction band of the silicon oxide film
  • EcS l represents energy at the bottom of the conduction band of the first oxide layer
  • EcS2 represents energy at the bottom of the conduction band of the oxide semiconductor layer
  • EcS3 represents energy at the bottom of the conduction band of the second oxide layer.
  • the energies of the bottoms of the conduction bands of the first oxide layer, the oxide semiconductor layer, and the second oxide layer are changed continuously. This can be understood also from the fact that the compositions of the first oxide layer, the oxide semiconductor layer, and the second oxide layer are close to each other and oxygen is easily diffused through the interface between the first oxide layer and the oxide semiconductor layer and through the interface between the oxide semiconductor layer and the second oxide layer.
  • the first oxide layer and the second oxide layer are oxide layers having the same energy gap
  • the first oxide layer and the second oxide layer may be oxide layers having different energy gaps.
  • part of the band structure in the case where EcS l is higher than EcS3 is shown in FIG. 7B.
  • EcS3 may be higher than EcSl .
  • the oxide semiconductor layer of the oxide stack serves as a well and a channel of the transistor including the oxide stack is formed in the oxide semiconductor layer.
  • the oxide stack can also be referred to as a U-shaped well.
  • a channel formed to have such a structure can also be referred to as a buried channel.
  • each of the first oxide layer 404a and the second oxide layer 404c is an oxide layer containing one or more kinds of metal elements forming the oxide semiconductor layer 404b
  • the oxide stack 404 can also be referred to as an oxide stack in which layers containing the same main components are stacked.
  • the oxide stack in which layers containing the same main components are stacked is formed to have not only a simple stacked-layer structure of the layers but also a continuous energy band (here, in particular, a well structure having a U shape in which energies of the bottoms of the conduction bands are changed continuously between the layers).
  • a defect level or an impurity for an oxide semiconductor for example, a defect level such as a trapping center or a recombination center, or an impurity forming a barrier which inhibits the flow of carriers is mixed at an interface between the layers, the continuity of the energy band is lost, and thus carriers are trapped or disappear by recombination at the interface.
  • a multi-chamber deposition apparatus including a load lock chamber.
  • Each chamber in the sputtering apparatus is preferably subjected to high vacuum evacuation (to a vacuum of about 1 x 10 "4 Pa to 5 x 10 "7 Pa) with use of a suction vacuum evacuation pump such as a cryopump in order to remove water or the like which is an impurity for an oxide semiconductor as much as possible.
  • a turbo-molecular pump is preferably used in combination with a cold trap so that a gas does not flow backward from an evacuation system to a chamber.
  • a chamber In order to obtain a highly purified intrinsic oxide semiconductor, a chamber needs to be subjected to high vacuum evacuation, and in addition, a sputtering gas needs to be highly purified.
  • a highly purified gas having a dew point of -40 °C or lower, preferably -80 °C or lower, more preferably -100 °C or lower is used as an oxygen gas or an argon gas used as a sputtering gas, moisture or the like can be prevented from entering an oxide semiconductor as much as possible.
  • the first oxide layer 404a and the second oxide layer 404c which are provided over and under the oxide semiconductor layer 404b each serve as a barrier layer and can prevent a trap level formed at an interface between the oxide stack 404 and each of the insulating layers which are in contact with the oxide stack 404 (the base insulating layer 402 and the gate insulating layer 410) from adversely affecting the oxide semiconductor layer 404b which serves as a main carrier path for the transistor.
  • oxygen vacancies contained in the oxide semiconductor layer appear as localized states in deep energy area in the energy gap of the oxide semiconductor. A carrier is trapped in such localized states, so that reliability of the transistor is lowered. For this reason, oxygen vacancies contained in the oxide semiconductor layer need to be reduced.
  • the oxide layers in which oxygen vacancies are less likely to be generated than in the oxide semiconductor layer 404b are provided over and under and in contact with the oxide semiconductor layer 404b in the oxide stack 404, whereby oxygen vacancies in the oxide semiconductor layer 404b can be reduced.
  • the absorption coefficient due to the localized levels which is obtained by measurement by a constant photocurrent method (CPM) is set lower than 1 ⁇ 10 ⁇ cm, preferably lower than 1 x 10 -4 /cm.
  • CPM constant photocurrent method
  • an impurity element e.g., silicon
  • an interface state is formed at an interface between the oxide semiconductor layer 404b and the insulating layer by the mixed impurity element, decrease in electrical characteristics of the transistor, such as a change in a threshold voltage of the transistor, is caused.
  • the first oxide layer 404a contains one or more kinds of metal elements forming the oxide semiconductor layer 404b in the oxide stack 404, an interface state is less likely to be formed at an interface between the first oxide layer 404a and the oxide semiconductor layer 404b.
  • providing the first oxide layer 404a makes it possible to reduce fluctuation in the electrical characteristics of the transistor, such as threshold voltage.
  • the second oxide layer 404c contains one or more kinds of metal elements forming the oxide semiconductor layer 404b in the oxide stack 404, scattering of carriers is less likely to occur at an interface between the second oxide layer 404c and the oxide semiconductor layer 404b, and thus the field-effect mobility of the transistor can be increased.
  • first oxide layer 404a and the second oxide layer 404c each also serve as a barrier layer which suppresses formation of an impurity level due to the entry of the constituent elements of the insulating layers which are in contact with the oxide stack 404 (the base insulating layer 402 and the gate insulating layer 410) into the oxide semiconductor layer 404b.
  • the silicon in the insulating layers or carbon which might be contained in the insulating layers enters the first oxide layer 404a or the second oxide layer 404c at a depth of several nanometers from the interface in some cases.
  • An impurity such as silicon, carbon, or the like entering the oxide semiconductor layer forms impurity levels.
  • the impurity levels serve as a donor and generate an electron, so that the oxide semiconductor layer may become n-type.
  • the impurity such as silicon or carbon does not reach the oxide semiconductor layer 404b, so that the influence of impurity levels is suppressed.
  • the concentration of silicon in the oxide semiconductor layer is lower than or equal to 3 x 10 l 8 /cm 3 , preferably lower than or equal to 3 x 10 , 7 /cm 3 .
  • the concentration of carbon in the oxide semiconductor layer is lower than or equal to 3 x 10 18 /cm 3 , preferably lower than or equal to 3 x 10 17 /cm 3 . It is particularly preferable to sandwich or surround the oxide semiconductor layer 404b serving as a carrier path by the first oxide layer 404a and the second oxide layer 404c in order to prevent entry of much silicon or carbon, which is a Group 14 element, to the oxide semiconductor layer 404b. That is, the concentration of silicon and carbon contained in the oxide semiconductor layer 404b is preferably lower than that in the first oxide layer 404a and the second oxide layer 404c.
  • the impurity concentration of the oxide semiconductor layer can be measured by secondary ion mass spectrometry (SIMS).
  • the oxide semiconductor layer If hydrogen or moisture is contained in the oxide semiconductor layer, it can work as a donor and form an n-type region; therefore, in order to achieve a well-shaped structure, it is useful to provide a protective insulating layer (e.g. a silicon nitride layer) for preventing entry of hydrogen or moisture from the outside, above the oxide stack 404.
  • a protective insulating layer e.g. a silicon nitride layer
  • the oxide semiconductor layer can be distanced away from the trap levels owing to existence of the first oxide layer and the second oxide layer.
  • an electron in the oxide semiconductor layer might reach the trap level by passing over the energy difference.
  • the energy difference between EcS l and EcS2 and the energy difference between EcS3 and EcS2 are each preferably greater than or equal to 0.1 eV, more preferably greater than or equal to 0.15 eV because the amount of change of the threshold voltage of the transistor is reduced and the transistor has stable electrical characteristics.
  • Each of the oxide layers included in the multi-layer structure is formed using a sputtering target which contains at least indium (In) and with which a film can be formed by a sputtering method, preferably a DC sputtering method.
  • a sputtering target which contains at least indium (In) and with which a film can be formed by a sputtering method, preferably a DC sputtering method.
  • the sputtering target contains indium, the conductivity thereof is increased; therefore, film formation by a DC sputtering method is facilitated.
  • a material which is represented by an In- -Zn oxide is a metal element such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf
  • M Ga is preferably used.
  • a material with a high proportion of Ga specifically the material represented as InGa ⁇ Zn ⁇ Oz with X exceeding 10, is not suitable because powder may be generated in the deposition and deposition by a sputtering method may become difficult.
  • the indium and gallium contents in those oxide layers 404a and 404c and the oxide semiconductor layer 404b can be compared with each other by time-of-flight secondary ion mass spectrometry (also referred to as TOF-SIMS) or X-ray photoelectron spectrometry (also referred to as XPS).
  • time-of-flight secondary ion mass spectrometry also referred to as TOF-SIMS
  • XPS X-ray photoelectron spectrometry
  • the first oxide layer 404a contains a constituent element (e.g. silicon) of the base insulating layer 402 as an impurity, it might have an amorphous structure.
  • the oxide semiconductor layer 404b in which a channel is formed preferably has a crystal part.
  • the oxide stack can be referred to as a hetero structure having different crystal structures.
  • the second oxide layer 404c may have an amorphous structure or include a crystal part. Formation of the second oxide layer 404c over the oxide semiconductor layer 404b having a crystal part allows the second oxide layer 404c to have a crystal structure. In this case, a boundary between the oxide semiconductor layer 404b and the second oxide layer 404c cannot be clearly identified by observation of the cross section with a transmission electron microscope (TEM) in some cases. Note that the second oxide layer 404c has lower crystallinity than the oxide semiconductor layer 404b. Hence, it can be said that the boundary can be determined by the degree of crystallinity.
  • TEM transmission electron microscope
  • At least the oxide semiconductor layer 404b in the oxide stack 404 is preferably a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • a CAAC-OS film refers to an oxide semiconductor layer which includes a crystal part whose c-axis is aligned in a direction substantially perpendicular to the surface of the oxide semiconductor film.
  • a structure of an oxide semiconductor layer is described below.
  • An oxide semiconductor layer is classified roughly into a single-crystal oxide semiconductor layer and a non-single-crystal oxide semiconductor layer.
  • the non-single-crystal oxide semiconductor layer includes any of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, a CAAC-OS film, and the like.
  • the amorphous oxide semiconductor layer has disordered atomic arrangement and no crystalline component.
  • a typical example thereof is an oxide semiconductor layer in which no crystal part exists even in a microscopic region, and the whole of the film is amorphous.
  • the microcrystalline oxide semiconductor layer includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example.
  • the microcrystalline oxide semiconductor layer has a higher degree of atomic order than the amorphous oxide semiconductor layer.
  • the density of defect states of the microcrystalline oxide semiconductor layer is lower than that of the amorphous oxide semiconductor layer.
  • the CAAC-OS film is one of oxide semiconductor layers including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits inside a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor layer.
  • the CAAC-OS film is described in detail below.
  • metal atoms are arranged in a layered manner in the crystal parts.
  • Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film.
  • metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts.
  • plane TEM image there is no regularity of arrangement of metal atoms between different crystal parts.
  • a CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus.
  • XRD X-ray diffraction
  • each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.
  • the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment.
  • the c-axis of the crystal is aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film.
  • the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film.
  • the degree of crystalhnity in the CAAC-OS film is not necessarily uniform.
  • the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases.
  • the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions.
  • a peak of 2 ⁇ 9 may also be observed at around 36°, in addition to the peak of 2 ⁇ at around 31 °.
  • the peak of 2 ⁇ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak of 2 ⁇ appear at around 31 ° and a peak of 2(9 do not appear at around 36°.
  • the transistor With the use of the CAAC-OS film in a transistor, change in electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has high reliability.
  • an oxide semiconductor layer may be a -stacked " film including two or more films of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, and a CAAC-OS film, for example.
  • first oxide layer 404a and the second oxide layer 404c which are included in the oxide stack 404 might have the same structure as the above oxide semiconductor layer.
  • the first oxide layer 404a have an amorphous structure and that a CAAC-OS film be deposited from a surface of the amorphous structure to be used as the oxide semiconductor layer 404b.
  • the CAAC-OS film is formed by a sputtering method with a polycrystalline oxide semiconductor sputtering target.
  • a crystal region included in the sputtering target may be separated from the target along an a-b plane; in other words, a sputtered particle having a plane parallel to an a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) may flake off from the sputtering target.
  • the flat-plate-like sputtered particle reaches a substrate while maintaining their crystal state, whereby the CAAC-OS film can be formed.
  • the flat-plate-like sputtered particle has, for example, an equivalent circle diameter of a plane parallel to the a-b plane of greater than or equal to 3 nm and less than or equal to 10 nm, and a thickness (length in the direction perpendicular to the a-b plane) of greater than or equal to 0.7 nm and less than 1 nm.
  • the plane parallel to the a-b plane may be a regular triangle or a regular hexagon.
  • the term "equivalent circle diameter of a plane” refers to the diameter of a perfect circle having the same area as the plane.
  • the following conditions are preferably used.
  • the substrate temperature during the deposition is higher than or equal to 100 °C and lower than or equal to 740 °C, preferably higher than or equal to 200 °C and lower than or equal to 500 °C.
  • the sputtered particle is charged positively, whereby sputtered particles are attached to the substrate while repelling each other; thus, the sputtered particles do not overlap with each other randomly, and a CAAC-OS film with a uniform thickness can be deposited.
  • the crystal state can be prevented from being broken by the impurities.
  • the concentration of impurities e.g., hydrogen, water, carbon dioxide, and nitrogen
  • the concentration of impurities in a deposition gas may be reduced.
  • a deposition gas whose dew point is -80 °C or lower, preferably -100 °C or lower is used.
  • the proportion of oxygen in the deposition gas be increased and the power be optimized in order to reduce plasma damage at the deposition.
  • the proportion of oxygen in the deposition gas is 30 vol% or higher, preferably 100 vol%.
  • heat treatment may be performed.
  • the temperature of the heat treatment is higher than or equal to 100 °C and lower than or equal to 740 °C, preferably higher than or equal to 200 °C and lower than or equal to 500 °C. Further, the heat treatment is performed for 1 minute to 24 hours, preferably 6 minutes to 4 hours.
  • the heat treatment may be performed in an inert atmosphere or an oxidation atmosphere. It is preferable to perform heat treatment in an inert atmosphere and then to perform heat treatment in an oxidation atmosphere.
  • the heat treatment in an inert atmosphere can reduce the concentration of impurities in the CAAC-OS film in a short time ; At the same time, the heat treatment in an inert atmosphere may generate oxygen vacancies in the CAAC-OS film. In this case, the heat treatment in an oxidation atmosphere can reduce the oxygen vacancies.
  • the heat treatment can further increase the crystallinity of the CAAC-OS film.
  • the heat treatment may be performed under a reduced pressure, such as 1000 Pa or lower, 100 Pa or lower, 10 Pa or lower, or 1 Pa or lower. The heat treatment under the reduced pressure can reduce the concentration of impurities in the CAAC-OS film in a shorter time.
  • an In-Ga-Zn-O compound target is described below.
  • the polycrystalline In-Ga-Zn-O compound target is made by mixing ⁇ powder, GaOr powder, and ZnOz powder at a predetermined molar ratio, applying pressure, and performing heat treatment at a temperature higher than or equal to 1000 °C and lower than or equal to 1500 °C.
  • x, y, and z are each a given positive number.
  • the predetermined molar ratio of ⁇ ' powder to GaOy powder and ZnOz powder is, for example, 2:2: 1 , 8:4:3, 3: 1 : 1 , 1 : 1 : 1 , 4:2:3, or 3: 1 :2.
  • the kinds of powder and the molar ratio for mixing powder may be determined as appropriate depending on the desired sputtering target.
  • the CAAC-OS film is formed by the following method.
  • a first oxide semiconductor film is formed to a thickness of greater than or equal to 1 nm and less than 10 nm.
  • the first oxide semiconductor film is formed by a sputtering method.
  • the substrate temperature during the deposition is higher than or equal to 100 °C and lower than or equal to 500 °C, preferably higher than or equal to 150 °C and lower than or equal to 450 °C, and the proportion of oxygen in the deposition gas is higher than or equal to 30 vol.%, preferably 100 vol.%.
  • heat treatment is performed so that the first oxide semiconductor film serves as a first CAAC-OS film with high crystallinity.
  • the temperature of the heat treatment is higher than or equal to 350 °C and lower than or equal to 740 °C, preferably higher than or equal to 450 °C and lower than or equal to 650 °C. Further, the heat treatment is performed for 1 minute to 24 hours, preferably 6 minutes to 4 hours.
  • the heat treatment may be performed in an inert atmosphere or an oxidation atmosphere. It is preferable to perform heat treatment in an inert atmosphere and then to perform heat treatment in an oxidation atmosphere.
  • the heat treatment in an inert atmosphere can reduce the concentration of impurities in the first oxide semiconductor film in a short time.
  • the heat treatment in an inert atmosphere may generate oxygen vacancies in the first oxide semiconductor film.
  • the heat treatment in an oxidation atmosphere can reduce the oxygen vacancies.
  • the heat treatment may be performed under a reduced pressure, such as 1000 Pa or lower, 100 Pa or lower, 10 Pa or lower, or 1 Pa or lower. The heat treatment under the reduced pressure can reduce the concentration of impurities in the first oxide semiconductor film in a shorter time.
  • the first oxide semiconductor film with a thickness of greater than or equal to 1 nm and less than 10 nm can be easily crystallized by heat treatment compared to the case where the first oxide semiconductor film has a thickness of greater than or equal to 10 nm.
  • a second oxide semiconductor film that has the same composition as the first oxide semiconductor film is formed to a thickness of greater than or equal to 10 nm and less than or equal to 50 nm.
  • the second oxide semiconductor film is formed by a sputtering method.
  • the substrate temperature during the deposition is higher than or equal to 100 °C and lower than or equal to 500 °C, preferably higher than or equal to 150 °C and lower than or equal to 450 °C, and the proportion of oxygen in the deposition gas is higher than or equal to 30 vol.%, preferably 100 vol.%.
  • heat treatment is performed so that solid phase growth of the second oxide semiconductor film from the first CAAC-OS film occurs, whereby the second oxide semiconductor film is turned into a second CAAC-OS film having high crystallinity.
  • the temperature of the heat treatment is higher than or equal to 350 °C and lower than or equal to 740 °C, preferably higher than or equal to 450 °C and lower than or equal to 650 °C. Further, the heat treatment is performed for 1 minute to 24 hours, preferably 6 minutes to 4 hours.
  • the heat treatment may be performed in an inert atmosphere or an oxidation atmosphere. It is preferable to perform heat treatment in an inert atmosphere and then to perform heat treatment in an oxidation atmosphere.
  • the heat treatment in an inert atmosphere can reduce the concentration of impurities in the second oxide semiconductor film in a short time.
  • the heat treatment in an inert atmosphere may generate oxygen vacancies in the second oxide semiconductor film.
  • the heat treatment in an oxidation atmosphere can reduce the oxygen vacancies.
  • the heat treatment may be performed under a reduced pressure, such as 1000 Pa or lower, 100 Pa or lower, 10 Pa or lower, or 1 Pa or lower. The heat treatment under a reduced pressure can reduce the concentration of impurities in the second oxide semiconductor film in a shorter time.
  • the CAAC-OS film with a total thickness of 10 nm or more can be formed.
  • the CAAC-OS film can be favorably used as the oxide semiconductor layer in the oxide stack.
  • FIGS. 1A to I D one embodiment of a semiconductor device including the stacked structure described in Embodiment 1 will be described with reference to FIGS. 1A to I D, FIGS. 2 A to 2C, FIGS. 3 A to 3D, FIGS. 9A to 9C, and FIG. 19.
  • a top gate transistor including an oxide semiconductor layer will be described as an example of the sem iconductor device.
  • the transistor 310 illustrated in FIGS. 1A to ID includes the base insulating layer 402 formed over a substrate 400; the island-shaped oxide stack 404 formed over the base insulating layer 402; a first source electrode layer 406a and a first drain electrode layer 406b each of which is in contact with a top surface of the island-shaped oxide stack 404 and a side face thereof in a channel length direction; a second source electrode layer 408a and a second drain electrode layer 408b which are provided over the first source electrode layer 406a and the first drain electrode layer 406b, respectively, are in contact with the top surface of the oxide stack 404, and formed using a metal nitride film; a gate insulating layer 410 which is provided over the second source electrode layer 408a and the second drain electrode layer 408b and in contact with the top surface of the oxide stack 404 between the second source electrode layer 408a and the second drain electrode layer 408b; a gate electrode layer 412 which overlaps with the oxide stack 404 with the gate insulating
  • the substrate 400 is not limited to a simple supporting substrate, and may be a substrate where a device such as a transistor is formed.
  • a device such as a transistor
  • at least one of the gate electrode layer 412, the first source electrode layer 406a, the first drain electrode layer 406b, the second source electrode layer 408a, and the second drain electrode layer 408b which are included in the transistor 310 may be electrically- connected to the above device.
  • the base insulating layer 402 has a function of supplying oxygen to the oxide stack 404 as well as a function of preventing diffusion of an impurity from the substrate 400; thus, an insulating layer containing oxygen is used as the base insulating layer 402.
  • the base insulating layer 402 has also a function as an interlayer insulating film.
  • the base insulating layer 402 is preferably subjected to planarization treatment such as chemical mechanical polishing (CMP) treatment so as to have a flat surface.
  • CMP chemical mechanical polishing
  • the base insulating layer 402 containing oxygen is provided below the stack structure (the oxide stack 404) including the oxide semiconductor layer. With such a structure, oxygen in the base insulating layer 402 can be supplied to a channel formation region.
  • the base insulating layer 402 preferably has a region containing oxygen in excess of the stoichiometric composition. When the base insulating layer 402 contains oxygen in excess of the stoichiometric composition, supply of oxygen to the channel formation region can be promoted.
  • excess oxygen means oxygen which can be transferred in an oxide semiconductor layer, silicon oxide, or silicon oxynitride, oxygen which exists in excess of the intrinsic stoichiometric composition, or oxygen having a function of filling Vo (oxygen vacancies) generated due to lack of oxygen.
  • Oxygen is also supplied to the oxide stack 404 from the gate insulating layer 410 provided over and in contact with the oxide stack 404.
  • the gate insulating layer 410 is in contact with the base insulating layer 402 outside the island-shaped oxide stack 404. Accordingly, oxygen in the base insulating layer 402 can be supplied to the oxide stack 404 from the region where the _gate_ insulating layer 410 and the base insulating layer 402 are in contact with each other, with use of the gate insulating layer 410 as a path.
  • the gate insulating layer 410 is a layer which serves as a path for supplying oxygen in the base insulating layer 402 to the oxide stack 404.
  • the gate insulating layer 410 can be formed using an insulating layer containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Further, the gate insulating layer 410 may be a stacked layer of any of the above materials.
  • oxygen vacancies which might be included in the oxide stack 404 can be reduced.
  • an insulating layer having a lower oxygen-transmitting property (higher oxygen barrier property) than the gate insulating layer 410 is provided.
  • the protective insulating layer 414 which is provided over and in contact with the gate insulating layer 410 and the gate electrode layer 412 and has a barrier property against oxygen is provided, desorption of oxygen from the gate insulating layer 410 can be suppressed.
  • the gate insulating layer 410 is an insulating layer serving as a path for supplying oxygen to the channel formation region, when desorption of oxygen from the gate insulating layer 410 is suppressed, extraction of oxygen from the oxide stack 404 which is caused by oxygen vacancies in the gate insulating layer 410 can be suppressed, so that oxygen vacancies in the channel formation region can be suppressed.
  • a protective insulating layer a silicon nitride film or a silicon nitride oxide film can be provided, for example.
  • the concentration of hydrogen in the protective insulating layer 414 is preferably reduced. Specifically, the concentration of hydrogen in the protective insulating layer 414 is preferably lower than 5 x l O 19 cm -3 , further preferably lower than 5 x l 0 , 8 cm -3 .
  • the oxide stack 404 includes the oxide semiconductor layer 404b in which at least a channel is formed, the first oxide layer 404a which is provided between the oxide semiconductor layer 404b and the base insulating layer 402, and the second oxide layer 404c which is provided between the oxide semiconductor layer 404b and the gate insulating layer 410.
  • Each of the first oxide layer 404a and the second oxide layer 404c is an oxide layer containing one or more kinds of metal elements forming the oxide semiconductor layer 404b.
  • the details of the oxide stack 404 refer to Embodiment 1.
  • the oxide layers in which oxygen vacancies are less likely to be generated than in the oxide semiconductor layer 404b are provided over and under and in contact with the oxide semiconductor layer 404b where a channel is formed, whereby generation of oxygen vacancies in the channel of the transistor can be suppressed.
  • the concentration of silicon in the oxide semiconductor layer which is measured by SIMS, is set to be lower than 1 ⁇ l O 19 atoms/cm 3 * preferably lower than 5 x l O 18 atoms/cm 3 , further preferably lower than 3 x 10 18 atoms/cm 3 , still further preferably lower than 1 x 10 atoms/cm .
  • the concentration of hydrogen in the oxide semiconductor layer is set to be lower than or equal to 2 x l O 20 atoms/cm 3 , preferably lower than or equal to 5 x l O 19 atoms/cm ⁇ further preferably lower than or equal to 1 ⁇ lO 19 atoms/cm 3 , still further preferably lower than or equal to 5 ⁇ 10 18 atoms/cm J .
  • the concentration of nitrogen in the oxide semiconductor layer is set to be lower than 5 x lO 19 atoms/cm 3 , preferably lower than or equal to 5 ⁇ l O 18 atoms/cm J , further preferably lower than or equal to I x 10 18 atoms/cm J , still further preferably lower than or equal to 5 ⁇ l O 1 7 atoms/cm 3 .
  • the oxide semiconductor layer includes crystals
  • high concentration of silicon or carbon might reduce the crystallinity of the oxide semiconductor layer.
  • the crystallinity of the oxide semiconductor layer can be prevented from decreasing when the concentration of silicon is lower than 1 x l O 19 atoms/cm 3 , preferably lower than 5 x 10 18 atoms/cm 3 , further preferably lower than 1 x 10 18 atoms/cm 3
  • the concentration of carbon is lower than 1 x 10 19 atoms/cm 3 , preferably lower than 5 x 10 18 atoms/cm 3 , further preferably lower than 1 x 10 18 atoms/cm 3 .
  • a transistor in which a highly purified oxide semiconductor film is used for a channel formation region as described above has extremely low off-state current.
  • the drain current at the time when the transistor including a highly purified oxide semiconductor film is in an off-state at room temperature (approximately 25 °C)
  • An off state of a transistor refers to a state where a gate voltage is much lower than a threshold voltage in an n-channel transistor. Specifically, the transistor is in an off state when the gate voltage is lower than the threshold voltage by 1 V or more, 2 V or more, or 3 V or more.
  • the transistor 310 includes the first source electrode layer 406a and the first drain electrode layer 406b each of which is in contact with the side face of the oxide stack 404 in the channel length direction, and the second source electrode layer 408a and the second drain electrode layer 408b which are provided over the first source electrode layer 406a and the first drain electrode layer 406b and have regions extending beyond the first source electrode layer 406a and the first drain electrode layer 406b in the channel length direction.
  • a conductive material which is easily bonded to oxygen can be used.
  • Al, Cr, Cu, Ta, Ti, Mo, or W can be used.
  • W with a high melting point is preferably used, which allows subsequent process temperatures to be relatively high.
  • the conductive material which is easily bonded to oxygen includes, in its category, a material to which oxygen is easily diffused.
  • oxygen in the oxide stack 404 is taken into the conductive material.
  • oxygen vacancies are generated in a region of the oxide stack 404 which is in the vicinity of an interface between the oxide stack 404 and each of the first source electrode layer 406a and the first drain electrode layer 406b, so that an n-type region 405 is formed (see FIG. I D).
  • the n-type region 405 can serve as a source or a drain of the transistor 310.
  • a constituent element of the first source electrode layer 406a and the first drain electrode layer 406b may enter the region 405. Further, parts of the first source electrode layer 406a and the first drain electrode layer 406b, which are in contact with the regions 405, might have a region having high oxygen concentration. A constituent element of the oxide stack 404 may enter the parts of the first source electrode layer 406a and the first drain electrode layer 406b, which are in contact with the regions 405.
  • a portion which can be called a mixed region or a mixed layer of the oxide stack 404 and each of the first source electrode layer 406a and the first drain electrode layer 406b is formed in some cases.
  • an interface between the n-type region 405 and a region which is not made to have n-type conductivity is schematically indicated by a dotted line. The same applies to other drawings referred to below.
  • the n-type region which is formed by the generation of the oxygen vacancies sometimes extends in the channel of the transistor. in that case, electrical characteristics of the transistor change; for example, the threshold voltage is shifted or on and off of the transistor cannot be controlled with the gate voltage (i.e., the transistor is on). Accordingly, when a transistor with an extremely short channel length is formed, it is preferable that the conductive material which is not easily bonded to oxygen be used for the source electrode and the drain electrode.
  • the second source electrode layer 408a and the second drain electrode layer 408b which have regions extending beyond the first source electrode layer 406a and the first drain electrode layer 406b in the channel length direction and determine a channel length are stacked over the first source electrode layer 406a and the first drain electrode layer 406b, and formed using a conductive material which is not easily bonded to oxygen.
  • a conductive material for example, tantalum nitride, titanium nitride, or the like is preferably used.
  • the conductive material which is not easily bonded to oxygen includes, in its category, a material to which oxygen is not easily diffused.
  • the channel length refers to a distance L2 between the second source electrode layer 408a and the second drain electrode layer 408b.
  • a channel means a part of the oxide semiconductor layer 404b which is between the second source electrode layer 408a and the second drain electrode layer 408b.
  • a channel formation region means parts of the first oxide layer 404a, the oxide semiconductor layer 404b, and the second oxide layer 404c which are between the second source electrode layer 408a and the second drain electrode layer 408b.
  • the contact resistance with the oxide stack 404 becomes too high; thus, it is preferable that as illustrated in FIG. IB, the first source electrode layer 406a and the first drain electrode layer 406b be formed over the oxide stack 404 and the second source electrode layer 408a and the second drain electrode layer 408b be formed over and in contact with the first source electrode layer 406a and the first drain electrode layer 406b.
  • the oxide stack 404 have a large contact area with the first source electrode layer 406a or the first drain electrode layer 406b, and the oxide stack 404 have a small contact area with the second source electrode layer 408a or the second drain electrode layer 408b.
  • the contact resistance between the oxide stack 404 and each of the first source electrode layer 406a and the first drain electrode layer 406b is reduced by the n-type region 405 due to generation of oxygen vacancies.
  • the contact resistance between the oxide stack 404 and each of the second source electrode layer 408a and the second drain electrode layer 408b is higher than the contact resistance between the oxide stack 404 and each of the first source electrode layer 406a and the first drain electrode layer 406b.
  • the transistor can have favorable electrical characteristics.
  • a conductive film formed using Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or the like can be used.
  • the structure of the transistor of one embodiment of the present invention can suppress an increase in oxygen vacancies in the oxide semiconductor layer. Accordingly, a semiconductor device which has favorable electrical characteristics and high long-term reliability can be provided.
  • FIGS. 2A to 2C illustrate a structural example of a transistor 320.
  • FIG. 2A is a plan view of the transistor 320
  • FIG. 2B is a cross-sectional view taken along dashed-dotted line X2-Y2 in FIG. 2A
  • FIG. 2C is a cross-sectional view taken along dashed-dotted line V2-W2 in FIG. 2A.
  • some components of the transistor 320 e.g., the protective insulating layer 414 and the like
  • the transistor 320 illustrated in FIGS. 2A to 2C includes the base insulating layer 402 formed over the substrate 400; the island-shaped oxide stack 404 formed over the base insulating layer; the first source electrode layer 406a and the first drain electrode layer 406b each of which is in contact with a top surface of the island-shaped oxide stack and a side face thereof in a channel length direction; the second source electrode layer 408a and the second drain electrode layer 408b which are provided so as to cover the first source electrode layer 406a and the first drain electrode layer 406b, respectively, are in contact with the top surface of the oxide stack 404, and formed using a metal nitride film; the gate insulating layer 410 which is provided over the second source electrode layer 408a and the second drain electrode layer 408b and in contact with the top surface of the oxide stack 404 between the second source electrode layer 408a and the second drain electrode layer 408b; the gate electrode layer 412 which overlaps with the oxide stack 404 with the gate insulating layer 410 provided therebetween;
  • One of the differences between the transistor 310 and the transistor 320 is the length L of the gate electrode layer 412 in a channel length direction.
  • the transistor 320 a structure in which the first source electrode layer 406a and the first drain electrode layer 406b do not overlap with the gate electrode layer 412 is employed in order to reduce parasitic capacitance between the gate and the drain and parasitic capacitance between the gate and the source.
  • the width of the gate electrode layer 412 is L0 and L I ⁇ L0 ⁇ L2 (L0 is greater than or equal to L2 and less than or equal to LI)
  • the parasitic capacitance between the gate and the drain and the parasitic capacitance between the gate and the source can be reduced as much as possible, so that the frequency characteristics of the transistor can be improved.
  • (L I - L2)/2 is preferably less than 20 % of L2.
  • the area occupied by the transistor 320 is preferably 1 ⁇ 2 to 25 ⁇ 2 .
  • L0 be 40 nm and L2 be 30 nm.
  • the area of a top surface of the island-shaped oxide stack 404 can be less than or equal to 1 ⁇ .
  • L0 > LI > L2 (LI is longer than or equal to L2 and shorter than or equal to L0) may be satisfied as illustrated in FIG. IB.
  • L0 > LI > L2 LI is longer than or equal to L2 and shorter than or equal to L0
  • the gate electrode layer 412 has a stacked- layer structure of a first gate electrode layer 412a in contact with the gate insulating layer 410 and a second gate electrode layer 412b.
  • first gate electrode layer 412a is formed using a material similar to that of the second source electrode layer 408a and the second drain electrode layer 408b, extraction of oxygen from the gate insulating layer 410 by the gate electrode layer 412 can be prevented.
  • Another difference between the transistor 310 and the transistor 320 is a structure of the second source electrode layer 408a and the second drain electrode layer 408b.
  • W l the width of the first source electrode layer 406a (or the first drain electrode layer 406b) in a channel width direction
  • Wl the width of the second source electrode layer 408a (or the second drain electrode layer 408b) in a channel width direction
  • Wl W2 ⁇ W2 (W2 is larger than Wl) in the transistor 320
  • the transistor 320 has a structure in which the second source electrode layer 408a (or the second drain electrode layer 408b) covers the first source electrode layer 406a (or the first drain electrode layer 406b).
  • Such a structure can prevent the gate insulating layer 410 from being in contact with the first source electrode layer 406a and the first drain electrode layer 406b formed using a conductive material which is easily bonded to oxygen. Accordingly, oxygen can be prevented from being extracted from the gate insulating layer 410.
  • the gate insulating layer 410 is a layer which serves as a path for supplying oxygen to the oxide stack 404, extraction of oxygen from the gate insulating layer 410 by the first source electrode layer 406a and the first drain electrode layer 406b is prevented, whereby oxygen can be supplied to the oxide stack 404 effectively. Accordingly, oxygen vacancies can be prevented from being generated in the oxide stack 404, and thus reliability, of the transistor 320 can be improved.
  • transistor 320 has the same structure as the transistor 310; therefore, the description of the transistor 310 can be referred to.
  • FIGS. 3A and 3B illustrate modification examples of the transistor 310 and the transistor 320. End portions of the first source electrode layer 406a and the first drain electrode layer 406b in a transistor 330 illustrated in FIG. 3A are different from those of the first source electrode layer 406a and the first drain electrode layer 406b in the transistor 310. End portions of the first source electrode layer 406a and the first drain electrode layer 406b in a transistor 340 illustrated in FIG. 3B are different from those of the first source electrode layer 406a and the first drain electrode layer 406b in the transistor 320.
  • the structures of the transistors 330 and 340 except those of the end portions of the first source electrode layer 406a and the first drain electrode layer 406b are similar to the structures of the transistors 310 and 320, respectively; therefore, the above description can be referred to.
  • FIGS. 3C and 3D are enlarged views each illustrating the first source electrode layer 406a in the transistors 330 and 340. It is preferable that in each of the transistors 330 and 340, the end portions of the first source electrode layer 406a and the first drain electrode layer 406b have a staircase-like shape including a plurality of steps, an end surface of a lower step be formed at an angle ⁇ 1 using the top surface of the oxide stack 404 as a reference, and an end surface of an upper step be formed at an angle ⁇ 2 using a top surface of the lower step as a reference.
  • the first source electrode layer 406a and the first drain electrode layer 406b be formed so as to have a curved surface having a curvature radius Rl between the top surface and the end surface of the lower step, a curved surface having a curvature radius R3 between a top surface and the end surface of the upper step, and a curved surface having a curvature radius R2 between the top surface of the lower step and the end surface of the upper step.
  • twxLSteps are provided Jn- each of the end portions of the first source electrode layer 406a and the first drain electrode layer 406b; however, the number of steps may be three or more. It is preferable that the number of steps be increased as the thickness of each of the first source electrode layer 406a and the first drain electrode layer 406b is larger. Note that the end portions of the first source electrode layer 406a and the first drain electrode layer 406b is not necessarily symmetric to each other.
  • each of the first source electrode layer 406a and the first drain electrode layer 406b may have a shape having only the angle ⁇ 1 and the curvature radius Rl .
  • the angles ⁇ 1 and ⁇ 2 are greater than or equal to 20° and less than or equal to 80°, preferably greater than or equal to 25° and less than or equal to 70°, further preferably greater than or equal to 30° and less than or equal to 60°.
  • the curvature radii Rl , R2, and R3 are greater than or equal to 10 % and less than or equal to 100 % of the thickness, preferably greater than or equal to 20 % and less than or equal to 75 % of the thickness, further preferably greater than or equal to 30 % and less than or equal to 60 % of the thickness.
  • the curvature radius R2 is preferably larger than either or both of the curvature radii Rl and R3.
  • each of the first source electrode layer 406a and the first drain electrode layer 406b has a shape including a plurality of steps as described above, coverage with the films formed over the first source electrode layer 406a and the first drain electrode layer 406b, specifically, coverage with the second source electrode layer 408a, the second drain electrode layer 408b, the gate insulating layer 410, and the like is improved, so that the transistor can have more favorable electrical characteristics and higher long-term reliability.
  • an end surface of the second source electrode layer 408a or the second drain electrode layer 408b is formed at an angle ⁇ 3 using the top surface of the oxide stack 404 as a reference.
  • the angle ⁇ 3 is greater than or equal to 30° and less than or equal to 80°, preferably greater than or equal to 35° and less than or equal to 75°. With such an angle, coverage with the gate insulating layer 410 and the like is improved, so that the transistor can have more favorable electrical characteristics and higher long-term reliability.
  • FIGS. 9A to 9C illustrates a structural example of a transistor 350.
  • the transistor 350 is a modification example of the transistor 320 in FIGS. 2A to 2C.
  • FIG. 9A is a plan view of the transistor 350
  • FIG. 9B is a cross-sectional view taken along line X3-Y3 in FIG. 9A
  • FIG. 9C is a cross-sectional view taken along line V3-W3 in FIG. 9A.
  • some components of the transistor 350 e.g., the protective insulating layer 414 and the like
  • a difference between the transistor 320 and the transistor 350 is a stacking order of the oxide stack 404 and the source electrode layer and the drain electrode layer. That is, in the transistor 350, the first source electrode layer 406a and the first drain electrode layer 406b are provided so as to cover side faces of an island-shaped first oxide layer 407a in a channel length direction, and side faces in the channel length direction and part of a top surface of an island-shaped oxide semiconductor layer 407b, and an island-shaped second oxide layer 407c is provided over and in contact with the first source electrode layer 406a and the first drain electrode layer 406b. Further, the second source electrode layer 408a and the second drain electrode layer 408b are provided over the second oxide layer 407c.
  • the n-type region 405 is formed due to extraction of oxygen by the first source electrode layer 406a or the first drain electrode layer 406b.
  • an oxide stack 407 including the first oxide layer 407a, the oxide semiconductor layer 407b, and the second oxide layer 407c is formed between the base insulating layer 402 and the gate insulating layer 410.
  • a region of the second oxide layer 407c which does not overlap with the second source electrode layer 408a and the second drain electrode layer 408b has a small thickness in some cases, by being partly etched at the time of processing into the second source electrode layer 408a and the second drain electrode layer 408b.
  • the transistor 350 in a cross section taken along the channel width direction, can have a structure in which side faces of the island-shaped first oxide layer 407a and the island-shaped oxide semiconductor layer 407b are covered with the second oxide layer 407c.
  • the influence of a parasitic channel which may be generated in an end portion of the oxide stack 407 in the channel width direction can be reduced. Therefore, reliability of the transistor can be improved.
  • the first source electrode layer 406a and the second source electrode layer 408a are electrically connected to each other in such a manner that a contact hole reaching the first source electrode layer 406a is formed in an interlayer insulating layer 424 provided over the protective insulating layer 414, and an electrode layer 422a is formed in the contact hole.
  • the first drain electrode layer 406b and the second drain electrode layer 408b are electrically connected to each other in such a manner that a contact hole reaching the first drain electrode layer 406b is formed in the interlayer insulating layer 424, and an electrode layer 422b is formed in the contact hole.
  • each of the first source electrode layer 406a and the first drain electrode layer 406b (the area of a top surface thereof) is made to be larger than the size of the contact hole provided in the interlayer insulating layer 424 (the area of a plane surface of the contact hole).
  • the size of the electrode layer is preferably reduced.
  • an organic insulating layer or an inorganic insulating layer can be used as appropriate.
  • an organic resin film which can be readily formed to have high planarity is preferably used.
  • a material similar to that of the first source electrode layer 406a and the first drain electrode layer 406b is preferably used.
  • oxygen can continue to be supplied to the channel formation region from the base insulating layer or through the gate insulating layer which is in contact with the base insulating layer outside the island-shaped oxide stack.
  • the structure of the transistor can suppress an increase in oxygen vacancies in the oxide semiconductor layer and reduce the impurity concentration, so that the oxide semiconductor layer can be highly purified to be a highly purified intrinsic oxide semiconductor layer.
  • the transistor including the oxide stack 404 has normally-off characteristics with a positive threshold voltage. Accordingly, a semiconductor device having favorable electrical characteristics and high long-term reliability can be provided.
  • the transistor 310 may have the gate electrode layer of the transistor 320, which has the stacked-layer structure.
  • Embodiment 1 an example of a method for fabricating the transistor described in Embodiment 1 will be described.
  • a case of fabricating the transistor 340 illustrated in FIG. 3B will be described as an example with reference to FIGS. 4A to 4C and FIGS. 5A to 5D.
  • the base insulating layer 402 is formed over the substrate 400 having an insulating surface (see FIG. 4A).
  • the base insulating layer 402 is formed to a thickness greater than or equal to 1 nm and less than or equal to 100 nm, and an insulating film containing oxygen, such as an aluminum oxide film, a magnesium oxide film, a silicon oxide film, a silicon oxynitride film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film , a hafnium oxide film, or a tantalum oxide film, which is formed by a plasma CVD method or a sputtering method can be used for the base insulating layer 402.
  • an insulating film containing oxygen such as an aluminum oxide film, a magnesium oxide film, a silicon oxide film, a silicon oxynitride film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum
  • the base insulating layer 402 may be formed in an oxygen atmosphere, for example.
  • the base insulating layer 402 may contain excess oxygen in such a manner that oxygen is introduced into the base insulating layer 402 which has been formed. Both the methods may be combined.
  • oxygen 302 (at least including any of oxygen radicals, oxygen atoms, or oxygen ions) is introduced into the base insulating layer 402 which has been formed to form an oxygen-excess region.
  • a method for introducing oxygen an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like may be used.
  • a gas containing oxygen can be used for oxygen introducing treatment.
  • oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used.
  • a rare gas may be contained in the gas containing oxygen in the oxygen introducing treatment.
  • the first oxide layer 404a, the oxide semiconductor layer 404b, and the second oxide layer 404c are formed over the base insulating layer 402 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method and selectively etched, so that the oxide stack 404 is formed (see FIG. 4B). Note that heating may be performed before etching.
  • the material described in Embodiment 1 can be used.
  • the first oxide layer 404a is preferably formed using an In-Ga-Zn oxide whose atomic ratio of In to Ga and Zn is 1 :3:2, an In-Ga-Zn oxide whose atomic ratio of In to Ga and Zn which is 1 :6:4, an In-Ga-Zn oxide whose atomic ratio of In to Ga and Zn is 1 :9:6, or an oxide having a composition is in the neighborhood of any of the above atomic ratios.
  • the oxide semiconductor layer 404b is preferably formed using an In-Ga-Zn oxide having an atomic ratio of In to Ga and Zn which is 1 : 1 : 1 , an In-Ga-Zn oxide having an atomic ratio of In to Ga and Zn which is 3: 1 :2, or an oxide having a composition which is in the neighborhood of any of the above atomic ratios.
  • the second oxide layer 404c is preferably formed using an In-Ga-Zn oxide having an atomic ratio of In to Ga and Zn which is 1 :3:2 or an oxide having a composition which is in the neighborhood of the above atomic ratio.
  • the composition of each of the oxide layers is not limited to the above atomic ratios.
  • the indium content in the oxide semiconductor layer 404b is preferably higher than those in the first oxide layer 404a and the second oxide layer 404c.
  • the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Therefore, an oxide having a composition in which the proportion of In is higher than that of Ga has higher mobility than an oxide having a composition in which the proportion of In is equal to or lower than that of Ga.
  • gallium needs large formation energy of an oxygen vacancy and thus is not likely to generate an oxygen vacancy as compared to indium. Therefore, an oxide having a high gallium content has stable characteristics.
  • the transistor With use of an oxide having a high indium content for the oxide semiconductor layer 404b, a transistor having high mobility can be achieved. Further, when an oxide having a high gallium content (here, the first oxide layer 404a and the second oxide layer 404c) is used, the transistor can have higher reliability.
  • an oxide semiconductor that can be used for the first oxide layer 404a, the oxide semiconductor layer 404b, and the second oxide layer 404c preferably contains at least indium (In) or zinc (Zn).
  • the oxide semiconductor preferably contains both In and Zn.
  • the oxide semiconductor layer 404b contain indium because the carrier mobility of the transistor can be increased, and the oxide semiconductor layer 404b contain zinc because a CAAC-OS film is formed easily.
  • the oxide semiconductor layer preferably contains a stabilizer in addition to indium and zinc.
  • gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), and the like can be given.
  • lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) can be given.
  • a material of the first oxide layer 404a and the second oxide layer 404c is selected so that the first oxide layer 404a and the second oxide layer 404c have higher electron affinities than that of the oxide semiconductor layer 404b.
  • the oxide stack is preferably formed by a sputtering method.
  • a sputtering method an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used.
  • a DC sputtering method is preferably used because dust generated in the deposition can be reduced and the film thickness can be uniform.
  • oxygen may be introduced into the first oxide layer 404a at timing which is after formation of the first oxide layer 404a and before formation of the oxide semiconductor layer 404b.
  • the first oxide layer 404a contains excess oxygen, so that the excess oxygen can be supplied to the oxide semiconductor layer 404b by heat treatment in a later film formation step.
  • oxygen vacancies in the oxide semiconductor layer 404b can be suppressed more by the oxygen introduction treatment performed on the first oxide layer 404a.
  • the first oxide layer 404a becomes amorphous by the oxygen introduction treatment in some cases.
  • at least the oxide semiconductor layer 404b is preferably a CAAC-OS film. Accordingly, the oxygen introduction treatment is preferably performed at timing which is after formation of the first oxide layer 404a and before formation of the oxide semiconductor layer 404b.
  • first heat treatment is preferably performed.
  • the first heat treatment may be performed at a temperature higher than or equal to 250 °C and lower than or equal to 650 °C, preferably higher than or equal to 300 °C and lower than or equal to 500 °C, in an inert gas atmosphere, an atmosphere containing an oxidizing gas at 10 ppm or more, or a reduced pressure state.
  • the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more in order to compensate desorbed oxygen.
  • the crystallinity of the oxide semiconductor layer 404b can be increased, and moreover, an impurity such as hydrogen or water can be removed from at least one of the base insulating layer 402, the first oxide layer 404a, the oxide semiconductor layer 404b, and the second oxide layer 404c.
  • the step of the first heat treatment may be performed before etching for formation of the oxide stack 404.
  • a first conductive film to be the first source electrode layer 406a and the first drain electrode layer 406b is formed over the oxide stack 404.
  • Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy material containing any of these as a main component can be used.
  • a 100-nm-thick tungsten film is formed by a sputtering method or the like.
  • the first conductive film is etched so as to be divided over the oxide stack
  • the end portions of the first source electrode layer 406a and the first drain electrode layer 406b are preferably formed so as to have a staircase-like shape as illustrated in the drawing.
  • the end portions can be formed in such a manner that a step of making a resist mask recede by ashing and an etching step are alternately performed plural times.
  • a second conductive film to be the second source electrode layer 408a and the second drain electrode layer 408b is formed over the oxide stack 404, the first source electrode layer 406a, and the first drain electrode layer 406b.
  • a metal nitride film of tantalum nitride, titanium nitride, or the like, or an alloy material containing any of these as its main component can be used.
  • a 20-nm-thick tantalum nitride film is formed by a sputtering method or the like.
  • the second conductive film is etched so as to be divided over the oxide stack 404, so that the second source electrode layer 408a and the second drain electrode layer 408b are formed (see FIG. 5A).
  • part of the oxide stack 404 (specifically, part of the second oxide layer 404c) may be etched. Note that although not illustrated, by the etching treatment for forming the second source electrode layer 408a and the second drain electrode layer 408b, a region of the base insulating layer 402 which is exposed from the second source electrode layer 408a and the second drain electrode layer 408b is etched and has a smaller thickness in some cases.
  • the gate insulating layer 410 is formed over the oxide stack 404, the second source electrode layer 408a, and the second drain electrode layer 408b (see FIG. 5B).
  • the gate insulating layer 410 can be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 410 may be a stacked layer of any of the above materials.
  • the gate insulating layer 410 can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable that the gate insulating layer 410 be formed by a CVD method, further preferably a plasma CVD method, because favorable coverage can be obtained.
  • second heat treatment is preferably performed.
  • an impurity such as water or hydrogen contained in the gate insulating layer 410 can be desorbed (dehydration or dehydrogenation can be performed).
  • the temperature of the second heat treatment is preferably higher than or equal to 300 °C and lower than or equal to 400 °C.
  • the second heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more in order to compensate desorbed oxygen.
  • an impurity such as hydrogen or water can be removed from the gate insulating layer 410.
  • further impurities such as hydrogen and water are removed from the oxide stack 404 in some cases.
  • oxygen can be supplied to the gate insulating layer 410.
  • the second heat treatment be successively performed in a deposition chamber after the gate insulating layer 410 is formed.
  • the heating at the time of forming the gate insulating layer 410 can serve as the second heat treatment.
  • the second heat treatment is performed in a state where the first source electrode layer 406a and the first drain electrode layer 406b are in contact with the oxide stack 404
  • oxygen in the oxide stack 404 is taken into the first source electrode layer 406a and the first drain electrode layer 406b which are easily bonded to oxygen. Accordingly, oxygen vacancies are generated in a region of the oxide stack 404 which is in the vicinity of an interface between the oxide stack 404 and each of the first source electrode layer 406a and the first drain electrode layer 406b, so that the n-type region 405 is formed.
  • the n-type region 405 is not formed depending on a temperature of the second heat treatment.
  • a conductive film to be the gate electrode layer 412 is formed over the gate insulating layer 410.
  • the conductive film can be formed by a sputtering method, or the like.
  • the conductive film is etched so as to remain to overlap with the channel formation region, so that the gate electrode layer 412 is formed (see FIG. 5C).
  • the gate electrode layer 412 has a stacked-layer structure including the first gate electrode layer 412a formed using a material similar to that of the second conductive film and the second gate electrode layer 412b formed using a material similar to that of the first conductive film.
  • the protective insulating layer 414 is formed over the gate insulating layer 410 and the gate electrode layer 412 (see FIG. 5D).
  • an insulating layer having a lower oxygen-transmitting property (higher oxygen barrier property) than the gate insulating layer 410 is provided.
  • a silicon nitride film or a silicon nitride oxide film can be provided, for example.
  • the protective insulating layer 414 be formed by a sputtering method because the concentration of hydrogen in the protective insulating layer 414 is preferably reduced.
  • the concentration of hydrogen in the protective insulating layer 414 is preferably lower than 5 x 10 19 cm -3 , more preferably lower than 5 x 10 18 cm ⁇ 3 .
  • Third heat treatment is preferably performed after the protective insulating layer 414 is formed.
  • the temperature of the third heat treatment is preferably higher than or equal to 350 °C and lower than or equal to 450 °C.
  • oxygen might be transferred from the oxide stack 404 to the first source electrode layer 406a and the first drain electrode layer 406b which are bonded to oxygen easily. Accordingly, in some cases, more oxygen vacancies are generated in the n-type region 405. Alternatively, in the case where the region which is in the vicinity of the interface does not become an n-type region by the second heat treatment, the region can become the n-type region 405 by the third heat treatment.
  • the transistor 340 in this embodiment can be fabricated.
  • FIG. 20A illustrates an example of a circuit diagram of a NOR circuit, which is a logic circuit, as an example of the semiconductor device of one embodiment of the present invention.
  • FIG. 20B illustrates a circuit diagram of a NAND circuit.
  • p-channel transistors 801 and 802 are transistors in each of which a channel formation region is formed using a semiconductor material (e.g., silicon) other than an oxide semiconductor, and n-channel transistors 803 and 804 each include an oxide stack including an oxide semiconductor and each have a structure similar to any of the structures of the transistors described in Embodiment 2.
  • a semiconductor material e.g., silicon
  • n-channel transistors 803 and 804 each include an oxide stack including an oxide semiconductor and each have a structure similar to any of the structures of the transistors described in Embodiment 2.
  • a transistor including a semiconductor material such as silicon can easily operate at high speed.
  • a transistor including an oxide semiconductor enables charge to be held for a long time owing to its characteristics.
  • the n-channel transistors 803 and 804 be stacked over the p-channel transistors 801 and 802.
  • the transistors 801 and 802 can be formed using a single crystal silicon substrate, and the transistors 803 and 804 can be formed over the transistors 801 and 802 with an insulating layer provided therebetween.
  • the transistors 803 and 804 have a structure having a back gate electrode, and by control ling the potential of the back gate electrode, for example, by setting the potential to GND, the threshold voltages of the transistors 803 and 804 are increased, so that the transistors can be normally off.
  • p-channel transistors 81 1 and 814 are transistors in each of which a channel formation region is formed using a semiconductor material (e.g., silicon) other than an oxide semiconductor, and n-channel transistors 812 and 813 each include an oxide stack containing an oxide semiconductor and each have a structure similar to any of the structures of the transistors described in Embodiment 2.
  • a semiconductor material e.g., silicon
  • the transistors 812 and 813 have a structure having a back gate electrode, and by controlling the potential of the back gate electrode, for example, by setting the potential to GND, the threshold voltages of the transistors 812 and 813 are increased, so that the transistors can be normally off.
  • the n-channel transistors 812 and 813 be stacked over the p-channel transistors 81 1 and 814.
  • a semiconductor device which is miniaturized, is highly integrated, and has stable and excellent electrical characteristics by stacking semiconductor elements including different semiconductor materials and a method for fabricating the semiconductor device can be provided.
  • Examples of a NOR circuit and a NAND circuit using the transistor in Embodiment 2 are described as an example in this embodiment; however, there is no particular limitation to the circuits and an AND circuit, an OR circuit, or the like can be formed.
  • FIG. 21 A is a circuit diagram illustrating the semiconductor device of this embodiment.
  • a transistor including a semiconductor material (e.g., silicon) other than an oxide semiconductor can be applied to a transistor 260 illustrated in FIG. 21A and thus the transistor 260 can easily operate at high speed. Further, charge can be held in a transistor 262 to which a structure similar to that of any of the transistors each including an oxide semiconductor layer described in Embodiment 2 can be applied for a long time owing to its characteristics.
  • a semiconductor material e.g., silicon
  • transistors are n-channel transistors here, p-channel transistors can also be used as the transistors used for the semiconductor device described in this embodiment.
  • a first wiring (a 1 st Line) is electrically connected to a source electrode layer of the transistor 260.
  • a second wiring (a 2nd Line) is electrically connected to a drain electrode layer of the transistor 260.
  • a third wiring (3rd Line) is electrically connected to one of a source electrode layer and a drain electrode layer of the transistor 262, and a fourth wiring (4th Line) is electrically connected to a gate electrode layer of the transistor 262.
  • a gate electrode layer of the transistor 260 and the other of the source electrode layer and the drain electrode layer of the transistor 262 are electrically connected to one electrode of the capacitor 264.
  • a fifth wiring (5th Line) and the other electrode of the capacitor 264 are electrically connected to each other.
  • the semiconductor device in FIG. 21 A utilizes a characteristic in which the potential of the gate electrode layer of the transistor 260 can be held, and thus enables data writing, storing, and reading of data as follows.
  • the potential of the fourth wiring is set to a potential at which the transistor 262 is turned on, so that the transistor 262 is turned on. Accordingly, the potential of the third wiring is applied to the gate electrode layer of the transistor 260 and the capacitor 264. That is, a predetermined charge is supplied to the gate electrode layer of the transistor 260 (writing).
  • a low-level charge and a high-level charge one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied.
  • the potential of the fourth wiring is set to a potential at which the transistor 262 is turned off, so that the transistor 262 is turned off.
  • the charge supplied to the gate electrode layer of the transistor 260 is held (holding). That is, the data is held in a floating gate (FG).
  • the off-state current of the transistor 262 is extremely low, the charge of the gate electrode layer of the transistor 260 is held for a long time.
  • the potential of the second wiring varies depending on the amount of charge held in the gate electrode layer of the transistor 260. This is because in general, when the transistor 260 is an n-channel transistor, an apparent threshold voltage K,h_H in the case where the high-level charge is given to the gate electrode layer of the transistor 260 is lower than an apparent threshold voltage F th L in the case where the low-level charge is given to the gate electrode layer of the transistor 260.
  • an apparent threshold voltage refers to the potential of the fifth wiring which is needed to turn on the transistor 260.
  • the potential of the fifth wiring is set to a potential Vo which is between V t h_ H and V t h_L, whereby charge supplied to the gate electrode layer of the transistor 260 can be determined.
  • Vo the potential of the fifth wiring
  • the transistor 260 is turned on.
  • V 0 the potential of the fifth wiring
  • the transistor 260 remains off. Therefore, the data stored in the floating-gate ⁇ FG) ean be-read-by determining the potential of the " second-wiring.
  • the fifth wiring in the case where data is not read may be supplied with a potential at which the transistor 260 is turned off regardless of the state of the gate electrode layer, that is, a potential lower than V t h H-
  • the fifth wiring may be supplied with a potential at which the transistor 260 is turned on regardless of the state of the gate electrode layer, that is, a potential higher than V t h_L- [0232]
  • FIG. 21B illustrates another example of one embodiment of a structure of a memory device.
  • FIG. 21 B illustrates an example of a circuit configuration of a semiconductor device
  • FIG. 21C is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 21 B is described, and then, the semiconductor device illustrated in FIG. 21C is described.
  • a bit line BL is electrically connected to the source electrode or the drain electrode of the transistor 262
  • a word line WL is electrically connected to the gate electrode layer of the transistor 262
  • the source electrode or the drain electrode of the transistor 262 is electrically connected to a first terminal of a capacitor 254.
  • the transistor 262 including an oxide semiconductor has extremely low off-state current. For that reason, the potential of the first terminal of the capacitor 254 (or a charge accumulated in the capacitor 254) can be held for an extremely long time by turning off the transistor 262.
  • the potential of the word line WL is set to a potential at which the transistor 262 is turned on, so that the transistor 262 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 254 (writing). After that, the potential of the word line WL is set to a potential at which the transistor 262 is turned off, so that the transistor 262 is turned off. Thus, the potential of the first terminal of the capacitor 254 is held (holding).
  • the off-state current of the transistor 262 is extremely low, the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor) can be held for a long time.
  • bit line BL which is in a floating state and the capacitor 254 are electrically connected to each other, and the charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL is changed.
  • the amount of change in potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254).
  • the potential of the bit line BL after charge redistribution is
  • CBX VBO+C V I (CB+Q, where V is the potential of the first terminal of the capacitor 254, C is the capacitance of the capacitor 254, C& is the capacitance of the bit line BL (hereinafter also referred to as bit line capacitance), and VBO is the potential of the bit line BL before the charge redistribution.
  • the semiconductor device illustrated in FIG. 2 IB can hold charge that is accumulated in the capacitor 254 for a long time because the off-state current of the transistor 262 is extremely low. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long period even when power is not supplied.
  • the semiconductor device illustrated in FIG. 21 C includes a memory cell array
  • memory cell arrays 251a and 251b including the plurality of memory cells 250 illustrated in FIG. 21 B as memory circuits in the upper portion, and a peripheral circuit 253 in the lower portion, which is necessary for operating the memory cell array 251 (the memory cell arrays 251 a and 251 b). Note that the peripheral circuit 253 is electrically connected to the memory cell array 251.
  • the peripheral circuit 253 can be provided under the memory cell array 251 (the memory cell arrays 251a and 251b).
  • the size of the semiconductor device can be reduced.
  • a semiconductor material of a transistor provided in the peripheral circuit 253 be different from that of the transistor 262.
  • silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used.
  • an organic semiconductor material or the like may be used.
  • a transistor including such a semiconductor material can operate at sufficiently high speed.
  • the transistor enables a variety of circuits (e.g., a logic circuit and a driver circuit) which need to operate at high speed to be favorably obtained.
  • FIG. 21C illustrates, as an example, the semiconductor device in which two memory cell arrays 25 1 (the memory cell arrays 25 1 a and 251 b) are stacked; however, the number of memory cell arrays to be stacked is not limited thereto. Three or more memory cell arrays may be stacked.
  • transistor 262 When a transistor including an oxide semiconductor in a channel formation region is used as the transistor 262, stored data can be retained for a long period. In other words, power consumption can be sufficiently reduced because a semiconductor device in which refresh operation is unnecessary or the frequency of refresh operation is extremely low can be provided.
  • the semiconductor device described in this embodiment is the semiconductor device described in Embodiment 1 which includes an oxide stack and in which an oxide semiconductor layer where a channel is formed is apart from a surface of the oxide stack.
  • FIG. 22 is a block diagram of an electronic device.
  • An electronic device illustrated in FIG. 22 includes an RF circuit 901 , an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 91 1, a memory circuit 912, a display 913, a touch sensor 919, an audio circuit 917, a keyboard 918, and the like.
  • the display 913 includes a display portion 914, a source driver 915, and a gate driver 916.
  • the application processor 906 includes a CPU 907, a DSP 908, and an interface 909 (IF 909).
  • the memory circuit 912 includes an SRAM or a DRAM; by employing the semiconductor device described in any of the above embodiments for the memory circuit 912, it is possible to provide an electronic device in which writing and reading of data can be performed at high speed, data can be held for a long period, power consumption is sufficiently reduced, and the reliability is high.
  • FIG. 23 illustrates an example in which any of the semiconductor devices described in the above embodiments is used for a memory circuit 950 in a display.
  • the memory circuit 950 illustrated in FIG. 23 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. Further, in the memory circuit, a signal line from image data (input image data), a display controller 956 which reads and controls data held in the memories 952 and 953(stored image data), and a display 957 which displays data by a signal from the display controller 956 are connected.
  • image data input image data
  • a display controller 956 which reads and controls data held in the memories 952 and 953(stored image data)
  • a display 957 which displays data by a signal from the display controller 956 are connected.
  • image data (input image data A) is formed by an application processor (not shown).
  • the input image data A is held in the memory 952 though the switch 954.
  • the image data (stored image data A) held in the memory 952 is transmitted and displayed to the display 957 through the switch 955 and the display controller 956.
  • the stored image data A is read from the memory 952 through the switch 955 by the display controller 956 normally at a frequency of approximately 30 Hz to 60 Hz.
  • new image data (input image data B) is formed by the application processor.
  • the input image data B is held in the memory 953 through the switch 954.
  • the stored image data A is read periodically from the memory 952 through the switch 955 even during that time.
  • the stored image data B starts to be read, transmitted to the display 957 through the switch 955 and the display controller 956, and displayed on the display 957. This reading operation is continued until another new image data is held in the memory 952.
  • the memory 952 and the memory 953 are not limited to separate memories, and a single memory may be divided and used.
  • the semiconductor device described in any of the above embodiments for the memory 952 and the memory 953 data can be written and read at high speed and held for a long period, and power consumption can be sufficiently reduced. Further, a semiconductor device which is hardly affected by entry of water, moisture, and the like from the outside and which has high reliability can be provided.
  • FIG. 24 is a block diagram of an e-book reader.
  • FIG. 24 includes a battery
  • a power supply circuit 1002 a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.
  • the memory circuit 1007 has a function of temporarily holding the contents of a book. For example, when a user uses a highlight function, the memory circuit 1007 stores and holds data of a portion specified by the user. Note that the highlight function is used to make a difference between a specific portion and the other portions while reading an e-book, by marking the specific portion, e.g., by changing the display color, underlining, making characters bold, changing the font of characters, or the like. In order to store the data for a short time, the data may be stored in the memory circuit 1007. In order to store the data for a short time, the data may be stored in the memory circuit 1007.
  • the data stored in the memory circuit 1007 may be copied to the flash memory 1004. Also in such a case, by employing the semiconductor device described in any of the above embodiments, data can be written and read at high speed and held for a long period, and power consumption can be sufficiently reduced. Further, a semiconductor device which is hardly affected by entry of water, moisture, and the like from the outside and which has high reliability can be provided.
  • FIGS. 25A and 25B illustrate a specific example of an electronic device.
  • FIGS. 25A and 25B illustrate a foldable tablet terminal.
  • FIG. 25A illustrates the tablet terminal in the state of being unfolded.
  • the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631 b, a display-mode switching button 9034, a power switch 9035, a power-saving-mode switching button 9036, a fastener 9033, and an operation switch 9038.
  • any of the semiconductor devices described in the above embodiments can be used for the display portion 9631 a and the display portion 9631 b, so that the tablet terminal can have high reliability.
  • the memory device described in the above embodiment may be applied to any of the semiconductor devices of this embodiment.
  • Part of the display portion 9631a can be a touch panel region 9632a, and data can be input by touching operation keys 9638 that are displayed.
  • a structure in which a half region in the display portion 9631 a has only a display function and the other half region also has a touch panel function is shown as an example, the display portion 9631a is not limited to the structure.
  • the display portion 9631 a can display keyboard buttons in the whole region to be a touch panel, and the display portion 9631b can be used as a display screen.
  • part of the display portion 9631b can be a touch panel region 9632b.
  • keyboard buttons can be displayed on the display portion 9631b.
  • Touch input can be performed concurrently on the touch panel regions 9632a and 9632b.
  • the switch 9034 for switching display modes can switch display orientation (e.g., between landscape mode and portrait mode) and select a display mode (switch between monochrome display and color display), for example.
  • the switch 9036 for switching to power-saving mode the luminance of display can be optimized in accordance with the amount of external light at the time when the tablet terminal is in use, which is detected with an optical sensor incorporated in the tablet terminal.
  • the tablet terminal may include another detection device such as a sensor for detecting orientation (e.g., a gyroscope or an acceleration sensor) in addition to the optical sensor.
  • FIG. 25A shows an example in which the display portion 9631a and the display portion 9631 b have the same display area; however, one embodiment of the present invention is not limited and one of the display portions may be different from the other display portion in size and display quality. For example, one of them may be a display panel that can display higher-definition images than the other.
  • the tablet terminal is closed in FIG. 25B.
  • the tablet terminal includes the housing 9630, a solar cell 9633, a charge and discharge control circuit 9634, a battery 9635, and a DCDC converter 9636.
  • FIG. 25B illustrates an example in which the charge and discharge control circuit 9634 includes the battery 9635 and the DC-DC converter 9636.
  • the housing 9630 can be closed when the tablet terminal is not in use.
  • the display portions 9631 a and 9631 b can be protected, thereby providing a tablet terminal with high endurance and high reliability for long-term use.
  • the tablet terminal illustrated in FIGS. 25A and 25B can have a function of displaying a variety of kinds of data (e.g., a still image, a moving image, and a text image), a function of displaying a calendar, a date, the time, or the like on the display portion, a touch-input function of operating or editing the data displayed on the display portion by touch input, a function of controlling processing by a variety of kinds of software (programs), and the like.
  • a function of displaying a variety of kinds of data e.g., a still image, a moving image, and a text image
  • a function of displaying a calendar, a date, the time, or the like on the display portion e.g., a calendar, a date, the time, or the like
  • a touch-input function of operating or editing the data displayed on the display portion by touch input
  • a function of controlling processing by a variety of kinds of software (programs) e.g., a
  • a conductive film was formed over an oxide semiconductor film and transfer of elements which exist between the stacked films was examined by SIMS, and results thereof will be described.
  • FIGS. 1 1 A and 1 IB each show analysis results of profiles of an oxygen isotope ( l 8 0) in a depth direction by SIMS before and after heat treatment in samples which were each fabricated with a stack of an IGZO film and a tungsten film by a sputtering method.
  • the IGZO film was formed by a DC sputtering method with a sputtering target containing In, Ga, and Zn at an atomic ratio of 1 : 1 : 1 or 1 :3:2 and a deposition gas containing Ar and 0 2 ( l 8 0) at a flow rate ratio of 2: 1.
  • the tungsten film was formed by a DC sputtering method with a tungsten sputtering target and a 100 percent Ar gas used as a deposition gas. Note that heat treatment was performed at 300 °C, 350 °C, 400 °C, and 450 °C each for one hour, and five samples including a sample which was not subjected to heat treatment were compared with one another.
  • the IGZO film formed with the sputtering target containing In, Ga, and Zn at an atomic ratio of 1 : 1 : 1 is crystalline, and the IGZO film formed with the sputtering target containing In, Ga, and Zn at an atomic ratio of 1 :3:2 is amorphous.
  • the fabrication process of the transistor involves some heat treatment steps, oxygen vacancies are generated in a region of the oxide semiconductor layer, which is in contact with the source electrode or the drain electrode, and the region becomes an n-type.
  • the n-type region can serve as a source or a drain of the transistor.
  • FIGS. 12A and 12B each show the analysis results by SIMS in samples which were each fabricated using a tantalum nitride film instead of the tungsten film.
  • the tantalum nitride film was formed by a reactive sputtering method (a DC sputtering method) with a tantalum sputtering target and a deposition gas containing Ar and N 2 at a flow rate ratio of 5 : 1 . Note that heat treatment was performed under four conditions similar to the above, and five samples including a sample which was not subjected to heat treatment were compared with one another.
  • FIG. 12A shows the analysis results by SIMS in samples which were each fabricated with a stack of the IGZO film whose atomic ratio of In to Ga and Zn was 1 :1 : 1 and the tantalum nitride film.
  • oxygen transferred to the tantalum nitride film oxygen taken thereinto was not observed and its behavior was different from that of the sample with the tungsten film in FIG. 1 1 A.
  • FIG. 12B shows the analysis results by SIMS in samples which were each formed with a stack of the IGZO film whose atomic ratio of In to Ga and Zn was 1 :3:2 and the tantalum nitride film.
  • the tantalum nitride film is a film that is not easily bonded to oxygen or a film which does not take oxygen therein easily.
  • FIGS. 13A and 13B each show the analysis results by SIMS in samples which were each fabricated using a titanium nitride film instead of the tungsten film.
  • the titanium nitride film was formed by a reactive sputtering method (a DC sputtering method) with a titanium sputtering target and a 100 percent N 2 gas used as a deposition gas. Note that heat treatment was performed under four conditions similar to the above, and five samples including a sample which was not subjected to heat treatment were compared with one another.
  • FIG. 13A shows the analysis results by SIMS in samples which were each fabricated with a stack of the IGZO film whose atomic ratio of In to Ga and Zn was 1 : 1 : 1 and the titanium nitride film. In either sample, oxygen transferred to the titanium nitride film (oxygen taken thereinto) was not observed and its behavior was different from that of the sample with the tungsten film in FIG. 1 1 A.
  • FIG. 13B shows the analysis results by SIMS in samples which were each fabricated with a stack of the IGZO film whose atomic ratio of In to Ga and Zn was 1 :3:2 and the titanium nitride film.
  • the titanium nitride film is a film that is not easily bonded to oxygen or a film which does not take oxygen therein easily.
  • FIGS. 14A and 14B each show analysis results of profiles of nitrogen in a depth direction by SIMS before and after heat treatment in samples which were each fabricated with a tantalum nitride film or a titanium nitride film formed over an IGZO film by a sputtering method.
  • the IGZO film was formed by a DC sputtering method with a sputtering target containing In, Ga, and Zn at an atomic ratio of 1 :1 : 1 and a deposition gas containing Ar and 0 2 at a flow rate ratio of 2: 1.
  • the tantalum nitride film and the titanium nitride film were formed by the above method. Note that heat treatment was performed at 400 °C for one hour, and two samples including a sample which was not subjected to heat treatment were compared with each other. [0280]
  • FIGS. 15A and 15B show SIMS analysis results of profiles of tantalum and titanium, respectively, in a depth direction in samples similar to those shown in FIGS. 14A and 14B as examples. As shown in FIGS. 1 5A and 15B, transfer of tantalum or titanium to the IGZO film was not observed. Accordingly, each of titanium and tantalum which might serve as an impurity affecting the electrical characteristics of the transistor is not widely transferred to the IGZO film from the tantalum nitride film or the titanium nitride film.
  • a film of a conductive nitride such as tantalum nitride or titanium nitride is a film that is not easily bonded to oxygen or a film which does not take oxygen therein easily, and nitrogen and a metal element in such a conductive nitride are not easily transferred to the oxide semiconductor film.
  • FIG. 16 shows measurement results of sheet resistance values of samples each fabricated as follows with respect to a depth to which an IGZO film was etched: the IGZO film was formed by a sputtering method, a tungsten film or a titanium nitride film was stacked over the IGZO film by a sputtering method, and then the tungsten film or the titanium nitride film was removed. For comparison, a sample in which a conductive film was not formed over the IGZO film was also fabricated.
  • the IGZO film was formed by a DC sputtering method with a sputtering target containing In, Ga, and Zn at an atomic ratio of 1 : 1 : 1 and a deposition gas containing Ar and 0 2 ( l 8 0) at a flow rate ratio of 2: 1.
  • the tungsten film was formed by a DC sputtering method with a tungsten sputtering target and a 100 percent Ar gas used as a deposition gas.
  • the titanium nitride film was formed by a reactive sputtering method (a DC sputtering method) with a titanium sputtering target and a 100 percent N 2 gas used as a deposition gas.
  • the tungsten film and the titanium nitride film were etched using hydrogen peroxide water.
  • the IGZO film was etched using a mixed solution of hydrogen peroxide water and ammonia. The remaining thickness of the IGZO film after the etching was measured using spectroscopic ellipsometry before and after the etching in order to obtain the depth to which the IGZO film was etched.
  • FIG. 17A shows measurement results of sheet resistance values of samples each fabricated as follows with respect to a depth to which an IGZO film was etched: the IGZO film was formed by a sputtering method, a tungsten film or a titanium nitride film was stacked over the IGZO film by a sputtering method, heat treatment was performed, and then the tungsten film or the titanium nitride film was removed. For comparison, a sample in which a conductive film was not formed over the IGZO film was also fabricated.
  • the formation of the IGZO film, and the tungsten film or the titanium nitride film and the removal of the tungsten film or the titanium nitride film were performed in manners similar to those of the above.
  • the heat treatment was performed at 400 °C under a N 2 atmosphere for one hour.
  • the resistance of the IGZO film was reduced.
  • the resistance of the IGZO film was most reduced in the region close to the surface thereof and up to the greatest depth. This suggests that the tungsten film takes oxygen of the IGZO film thereinto most easily.
  • the behavior of the sample in which the titanium nitride film was formed over the IGZO film was similar to that of the sample in which a conductive film was not formed over the IGZO film.
  • FIG. 17B shows measurement results of sheet resistance values of samples each fabricated as follows with respect to a depth to which an IGZO film was etched: a silicon oxide film was formed by a sputtering method, the IGZO film was formed over the silicon oxide film by a sputtering method, a tungsten film or a titanium nitride film was stacked over the IGZO film by a sputtering method, heat treatment was performed, and then the tungsten film or the titanium nitride film was removed. For comparison, a sample in which a conductive film was not formed over the IGZO film was also fabricated.
  • the silicon oxide film was formed by a reactive sputtering method (a DC sputtering method) with a silicon sputtering target and a 100 percent 0 2 gas used as a deposition gas. Note that the formation of the IGZO film, and the tungsten film or the titanium nitride film and the removal of the tungsten film or the titanium nitride film were performed in manners similar to those of the above.
  • the heat treatment was performed at 400 °C under a N 2 atmosphere for one hour.
  • a silicon oxynitride film was formed by a plasma CVD method over a silicon wafer which was subjected to thermal oxidation treatment in an atmosphere containing HC1.
  • a surface of the silicon oxynitride film was subjected to planarization treatment by a CMP method.
  • an 1GZO film was formed over the silicon oxynitride film, and an oxygen ion (0 + ) was added to the IGZO film by an ion implantation method.
  • the IGZO film was formed by a DC sputtering method, using a sputtering target containing In, Ga, and Zn at an atomic ratio of 1 :3:2 and a deposition gas containing Ar and 0 2 at a flow rate ratio of 2: 1.
  • the oxygen ion was added under the following conditions: the acceleration voltage was 5 kV and the dose was 1 .0 x 10 ions/cm . Further, a sample to which an oxygen ion was not added was also prepared as a comparative sample.
  • FIG. 18A shows a result obtained by measurement of the amount of a released gas having a mass number of 32 from the sample to which an oxygen ion was not added by TDS analysis. A peak indicating release of the gas having a mass number of 32 was not observed in the range from approximately 50 °C to approximately 550 °C.
  • FIG. 1 8B shows a result obtained by measurement of the amount of a released gas having a mass number of 32 from the sample to which an oxygen ion was added by TDS analysis. A prominent peak indicating release of the gas was observed in the range from approximately 400 °C to approximately 500 °C.
  • the film densities of the oxide semiconductor films which are a sample to which an oxygen ion was not added and a sample to which an oxygen ion was added were measured by X-ray reflectometry (XR ).
  • a silicon oxynitride film was formed by a plasma CVD method over a silicon wafer which was subjected to thermal oxidation treatment in an atmosphere containing HC1, and an oxygen ion (0 + ) was added to the silicon oxynitride film by an ion implantation method, and then a surface of the silicon oxynitride film was subjected to pianarization treatment by a CMP method. After that, an IGZO film was formed over the silicon oxynitride film, and an oxygen ion (0 + ) was added to the IGZO film by an ion implantation method.
  • formation of the IGZO film and addition of an oxygen ion to the IGZO film were performed under conditions similar to those above. An oxygen ion was added to the silicon oxynitride film under the following conditions: the acceleration voltage was 60
  • the film density of the sample to which an oxygen ion was not added was 5.8 g/cm
  • the film density of the sample to which an oxygen ion was added was 5.6 g/cm 3 . Accordingly, it was found that the film density of an oxide semiconductor film was reduced by addition of an oxygen ion. This shows that by addition of an oxygen ion, an oxide semiconductor film can have more disordered atomic arrangement, that is, the oxide semiconductor film can be modified into a prominently amorphous film.
  • the crystallinity of the oxide semiconductor film which is an upper layer is lowered in some cases. Even in such a case, an oxygen ion is added to the oxide semiconductor film which is the lower layer so that it becomes amorphous before formation of the oxide semiconductor film which is the upper layer, whereby the oxide semiconductor film which is the upper layer can have improved crystallinity.

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US20140103337A1 (en) 2014-04-17
TW201431073A (zh) 2014-08-01
US9287117B2 (en) 2016-03-15
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CN104704638B (zh) 2017-11-17
CN104704638A (zh) 2015-06-10

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