WO2013084451A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2013084451A1
WO2013084451A1 PCT/JP2012/007661 JP2012007661W WO2013084451A1 WO 2013084451 A1 WO2013084451 A1 WO 2013084451A1 JP 2012007661 W JP2012007661 W JP 2012007661W WO 2013084451 A1 WO2013084451 A1 WO 2013084451A1
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WIPO (PCT)
Prior art keywords
impurity diffusion
diffusion region
region
conductivity type
contact
Prior art date
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Ceased
Application number
PCT/JP2012/007661
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English (en)
French (fr)
Japanese (ja)
Inventor
奥山　正樹
久克 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
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Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to US14/358,982 priority Critical patent/US9312329B2/en
Priority to CN201280060455.1A priority patent/CN103988305A/zh
Publication of WO2013084451A1 publication Critical patent/WO2013084451A1/ja
Anticipated expiration legal-status Critical
Priority to US15/049,839 priority patent/US9859359B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H10D18/60—Gate-turn-off devices 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a structure for protecting a circuit from a surge current caused by static electricity or the like.
  • semiconductor devices have been formed by forming various elements.
  • One of them is a semiconductor device in which a digital circuit and an analog circuit are mixed.
  • the voltage level of the signal handled with respect to the voltage level that is the boundary between the high level and the low level called the threshold value is close to both ends of the voltage change range, so there is a possibility that the signal value may be mistaken.
  • the handling of the voltage level that is low and deviates from the threshold value has an advantage that it is not severe compared to the analog signal.
  • the signal level is determined by the voltage level of the signal at the switching timing of the operation clock signal serving as a reference.
  • the disturbance of the voltage level at times other than the switching timing of the operation clock signal is In many cases, it does not affect the processing result of the digital circuit.
  • the analog circuit part it is important to accurately detect the voltage level of the signal to be handled and to perform transmission and processing, and the disturbance of the signal voltage greatly affects the processing result.
  • the disturbance of the signal voltage occurs due to various noise effects.
  • Noise or the like given from the outside of the semiconductor device may be able to reduce the influence on the internal elements by increasing the so-called shielding property of the semiconductor device itself.
  • some noise is generated inside the semiconductor element.
  • a digital element generates noise in switching from a high level to a low level and switching from a low level to a high level. Even if such switching noise does not lead to a malfunction in the digital circuit, it greatly affects the processing of the analog circuit.
  • a structure called a triple well in which a digital element and an analog element are separated in a semiconductor device may be employed.
  • the triple well structure has a problem that the internal element is destroyed due to a surge current caused by ESD (electrostatic discharge) or the like.
  • ESD electrostatic discharge
  • Patent Document 1 As a countermeasure against the surge current, for example, there is a method described in Patent Document 1.
  • the present invention has been made to solve at least one of the above-described problems or problems, and can be realized as the following application examples or embodiments.
  • the semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first impurity diffusion region, a first conductivity type second impurity diffusion region, and a second conductivity type third impurity.
  • the first impurity diffusion region is provided in the semiconductor substrate, and the second impurity
  • the diffusion region is provided in the first impurity diffusion region
  • the third impurity diffusion region is provided in the second impurity diffusion region
  • the first portion of the fourth impurity diffusion region is the second impurity diffusion region.
  • the second impurity diffusion region is provided apart from the third impurity diffusion region, and the second portion of the fourth impurity diffusion region is the surface side of the semiconductor substrate of the third portion of the first impurity diffusion region.
  • the first portion and the second portion are continuous,
  • the first contact is provided in contact with the second portion, the first contact and the third portion overlap in plan view, and the first power source is connected to the third impurity diffusion region. It is characterized by. In this specification, “separation” means that an appropriate distance is maintained without contact.
  • the second portion of the fourth impurity diffusion region is provided on the surface side of the semiconductor substrate of the third portion of the first impurity diffusion region,
  • the first part and the second part are continuous, and the first contour
  • the first contact and the third portion overlap in plan view, and the first power source is connected to the third impurity diffusion region.
  • a first conductivity type impurity diffusion region is formed below a second conductivity type impurity diffusion region to which a contact is connected.
  • a second conductivity type impurity diffusion region is formed under the first conductivity type impurity diffusion region. That is, the layers under the contact are in the order of the second conductivity type layer, the first conductivity type layer, the second conductivity type layer, and the first conductivity type layer (substrate) as viewed from the contact side. To do. In this case, when a surge current enters the contact, breakdown is likely to occur at an interface between the second conductivity type layer to which the contact is connected and the first conductivity type layer immediately below the layer having a different conductivity type.
  • the second conductivity type first impurity diffusion region below the second conductivity type fourth impurity diffusion region to which the first contact is connected is the same conductivity type. Therefore, the breakage at the boundary between the fourth impurity diffusion region and the first impurity diffusion region is less likely to occur.
  • the first impurity diffusion region is, for example, a layer having a function of element isolation between an analog element and a digital element, and the area of the first impurity diffusion region in a plan view of the semiconductor device is It is considered that the influence of the surge current at the boundary between the first impurity diffusion region and the semiconductor substrate is smaller than the influence at the boundary of the fourth impurity diffusion region.
  • a first power supply is connected to the third impurity diffusion region of the second conductivity type.
  • the first power source may be GND, for example.
  • GND gate controlled diode
  • the gap between the fourth impurity diffusion region and the third impurity diffusion region is provided.
  • the barrier can be controlled appropriately.
  • the predetermined region of the first impurity diffusion region that can sandwich the second impurity diffusion region between the first contact and the third portion is a first region. It is preferable that they are connected by wiring.
  • the first contact and the predetermined region of the first impurity diffusion region that can sandwich the second impurity diffusion region between the third portion are connected by the first wiring.
  • the occurrence of a potential difference in the first impurity diffusion region can be reduced by applying the voltage due to the surge voltage to the first impurity diffusion region widely across the second impurity diffusion region in which an element is mainly formed.
  • the flow of surge current other than the route to the first power supply can be suppressed, and breakdown due to surge current can be reduced.
  • the semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first impurity diffusion region provided in the semiconductor substrate, and a first impurity diffusion region provided in the first impurity diffusion region.
  • a first conductivity type second impurity diffusion region; a second conductivity type third impurity diffusion region provided in the second impurity diffusion region; a second conductivity type fourth impurity diffusion region; and the second impurity A fifth impurity diffusion region of a second conductivity type provided in the diffusion region, a first contact, and a first power source, wherein the second impurity diffusion region is the first impurity diffusion in a plan view.
  • the third impurity diffusion region and the fifth impurity diffusion region are surrounded by the first region of the region and so as to surround the second region of the first impurity diffusion region. Are arranged so that the area of The four impurity diffusion regions are disposed between the third impurity diffusion region and the fifth impurity diffusion region in plan view, and the fourth impurity diffusion region includes a first portion, a second portion, and a third portion. The second portion is disposed in the second region, and the first portion is disposed on the third impurity diffusion region side of the second impurity diffusion region and spaced apart from the third impurity diffusion region.
  • the third portion is disposed on the fifth impurity diffusion region side of the second impurity diffusion region and spaced apart from the fifth impurity diffusion region, and the first portion, the second portion, and the third portion The portion is continuous, the first contact is provided in contact with the second portion, and the first power source is connected to the third impurity diffusion region and the fifth impurity diffusion region. To do.
  • a semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first impurity diffusion region provided in the semiconductor substrate, and the first impurity diffusion region.
  • the third impurity diffusion region and the fifth impurity diffusion region are planarly disposed so as to be surrounded by the first region of the first impurity diffusion region and the second region of the first impurity diffusion region.
  • the second region is located in between The fourth impurity diffusion region is disposed between the third impurity diffusion region and the fifth impurity diffusion region in plan view, and the fourth impurity diffusion region includes the first portion, The second portion is disposed in the second region, and the first portion is diffused on the third impurity diffusion region side of the second impurity diffusion region.
  • the third portion is disposed apart from the fifth impurity diffusion region on the side of the fifth impurity diffusion region of the second impurity diffusion region, the first portion, and the second portion
  • the first portion is provided so as to contact the second portion, and the first power source is connected to the third impurity diffusion region and the fifth impurity diffusion region.
  • the second portion of the second conductivity type fourth impurity diffusion region to which the first contact is connected is formed in the second region of the second conductivity type first impurity diffusion region, and the first contact is connected Since the region and the region below it have the same conductivity type, breakdown at the boundary between the fourth impurity diffusion region and the first impurity diffusion region is unlikely to occur. Further, by providing GCD or the like between the first portion and the third impurity diffusion region and between the third portion and the fifth impurity diffusion region, the fourth impurity diffusion region and the third impurity diffusion region are The barrier between them can be controlled appropriately.
  • the same potential is supplied to different portions of the first impurity diffusion region.
  • the potential difference can be reduced in the diffusion region, the flow of surge current other than the route to the first power supply can be suppressed, and breakdown due to surge current can be reduced.
  • FIG. 3 is a schematic cross-sectional view of a semiconductor device.
  • FIG. FIG. 3 is a schematic diagram of a plan view and a cross section of the semiconductor device according to the first embodiment.
  • FIG. 6 is a schematic diagram of a plan view and a cross section of a semiconductor device in Example 2. The figure which shows the manufacturing process of a semiconductor device. The figure which shows the manufacturing process of the conventional semiconductor device.
  • FIG. 3 is a schematic plan view of a semiconductor device. Sectional drawing of the conventional semiconductor device.
  • FIG. 7A shows a cross-sectional view of a predetermined portion of a semiconductor device 900 having a conventional triple well structure.
  • a second conductivity type first impurity diffusion region 920 is formed in a first conductivity type semiconductor substrate 910, and the first conductivity type second impurity diffusion region is so formed as to float in the first impurity diffusion region 920.
  • a contact 953 is formed in the fourth impurity diffusion region 950, and the first wiring 901 is connected to the contact 953.
  • the first wiring 901 is a wiring connected to the pad 909 connected to the external terminal.
  • a contact 948 and a contact 949 are formed on the surfaces of the third impurity diffusion region 940 and the third impurity diffusion region 941, a second wiring 902 is connected to the contact 948, and a third wiring 903 is connected to the contact 949. Is formed.
  • the second wiring 902 and the third wiring 903 are connected to a first power source (not shown).
  • a first gate 960 is provided between the third impurity diffusion region 940 and the fourth impurity diffusion region 950, and a second gate 961 is provided between the third impurity diffusion region 941 and the fourth impurity diffusion region 950. Is provided.
  • the first impurity diffusion region 920 becomes an N-type well and the second impurity diffusion region 930 becomes a P-type well. That is, the semiconductor substrate 910, the first impurity diffusion region 920, and the second impurity diffusion region 930 form a triple well structure.
  • the first power supply may be GND.
  • the bipolar BP composed of the impurity diffusion region 940 and the fourth impurity diffusion region 950 (BP in FIG. 7- (a) and FIG. 7- (b)) is turned on, and a surge current is applied to the first power supply via the bipolar BP. It is possible to flow.
  • FIG. 1 is a cross-sectional view of a predetermined portion of a semiconductor device 100 to which the present invention is applied.
  • the semiconductor device 100 includes a first conductivity type semiconductor substrate 10, a second conductivity type first impurity diffusion region 20, a first conductivity type second impurity diffusion region 30, and a second conductivity type third impurity diffusion region 40.
  • the third conductivity diffusion region 41 of the second conductivity type and the fourth impurity diffusion region 50 of the second conductivity type are formed.
  • a first gate 60 is provided between the third impurity diffusion region 40 and the fourth impurity diffusion region 50, and a second gate is provided between the third impurity diffusion region 41 and the fourth impurity diffusion region 50. 61 is provided.
  • the structure of the semiconductor substrate 10, the first impurity diffusion region 20, and the second impurity diffusion region 30 forms a triple well structure.
  • the first conductivity type is P-type and the second conductivity type is N-type.
  • the first impurity diffusion region 20 is an N-type well, and the second impurity diffusion region 30 is a P-type well.
  • a contact 53 is formed on the surface of the fourth impurity diffusion region 50, and the first wiring 101 is connected to the contact 53.
  • the first wiring 101 is a wiring connected to the pad 109 connected to the external terminal.
  • the first impurity diffusion region 20 is disposed in a region immediately below the fourth impurity diffusion region 50 where the contact 53 is provided.
  • a contact 48 and a contact 49 are formed on the surfaces of the third impurity diffusion region 40 and the third impurity diffusion region 41, the second wiring 102 is connected to the contact 48, and the third wiring 103 is connected to the contact 49. Is formed.
  • the second wiring 102 and the third wiring 103 are connected to a first power source (not shown).
  • the bipolar BP constituted by the impurity diffusion region 40 and the fourth impurity diffusion region 50 is turned on, and a surge current can be passed to the first power supply via the bipolar BP.
  • a predetermined time elapses before the bipolar BP is turned on, but the first impurity having the same conductivity type as that of the fourth impurity diffusion region 50 is located immediately below the fourth impurity diffusion region 50 where the contact 53 is provided. Since it is the diffusion region 20, it is possible to prevent destruction near the boundary between the fourth impurity diffusion region 50 and the first impurity diffusion region 20.
  • the first power supply may be GND.
  • FIG. 2 shows a plan view of a part of the semiconductor device 200 and a cross-sectional view taken along line AB of the plan view. The broken line shows the correspondence between the plan view and the sectional view for convenience.
  • the same components as those of the semiconductor device 100 are denoted by the same reference numerals, and the description thereof may be omitted.
  • a region having a higher impurity concentration exists on the surface side of the semiconductor substrate in each region.
  • Tap region 80 in semiconductor substrate 10 tap region 21 in first impurity diffusion region 20, tap region 32 in second impurity diffusion region 30, tap region 42 in third impurity diffusion region 40, tap region in third impurity diffusion region 41 43 and the tap region 51 in the fourth impurity diffusion region 50 correspond to this.
  • the tap area 21 and the tap area 51 are connected via the first wiring 101.
  • the element isolation regions 90 are connected so as to sandwich the respective tap regions.
  • the second impurity diffusion region 30 is formed so as to float on the first impurity diffusion region 20, and when viewed in plan, the region immediately below the contact 53 is a partial region of the first impurity diffusion region 20,
  • the fourth impurity diffusion region 50 has a structure that covers the partial region.
  • the first wiring 101 is connected to a pad 109 and to a part of a pair of CMOSs.
  • the first signal wiring 104 connected to the first gate 60 and the second gate 61 is connected to a circuit (not shown).
  • the tap area 32, the tap area 42, and the tap area 43 are connected to GND.
  • the first impurity diffusion region 20 Since the first wiring 101 is connected to the tap region 21 and the tap region 51, the first impurity diffusion region 20 is kept at the same potential even when a surge voltage is applied to the pad 109. With this structure, it is possible to prevent breakdown due to surge current near the boundary between the fourth impurity diffusion region 50 and the first impurity diffusion region 20.
  • the surge voltage is a positive voltage
  • silicide 52 is formed on the surfaces of the tap region 21, the tap region 32, the tap region 42, the tap region 43, the tap region 51, and the tap region 80. By forming the silicide 52, the resistance value in the current path can be reduced.
  • FIG. 3 shows a plan view of a part of the semiconductor device 300 and a cross-sectional view taken along line AB of the plan view. The broken line shows the correspondence between the plan view and the sectional view for convenience. Also in the description of this embodiment, the same components as those of the semiconductor device 100 or the semiconductor device 200 are denoted by the same reference numerals, and the description thereof may be omitted.
  • the first gate 60 is connected to the second wiring 102.
  • the second gate 61 is connected to the third wiring 103. Since the first gate 60 and the second gate 61 are connected to GND, the barrier between the fourth impurity diffusion region 50 and the third impurity diffusion region 40 is appropriately maintained.
  • the semiconductor device 300 is an element only for ESD, and the first wiring 101 is connected to other input / output elements. Other structures are the same as those of the semiconductor device 200. With this structure, it is possible to prevent breakdown due to surge current near the boundary between the fourth impurity diffusion region 50 and the first impurity diffusion region 20.
  • the surge voltage When the surge voltage is a positive voltage, after the parasitic diode between the fourth impurity diffusion region 50 and the second impurity diffusion region 30 becomes an avalanche break, the second impurity diffusion region 30, the third impurity diffusion region 40, and the second impurity diffusion region A surge current flows to GND via the three impurity diffusion regions 41.
  • the surge voltage is a negative voltage, a current flows in the forward direction in the parasitic diode between the fourth impurity diffusion region 50 and the second impurity diffusion region 30, and the fourth impurity diffusion is performed from the tap region 32.
  • a surge current flows through the region 50.
  • FIGS. 4 and 5 are cross-sectional views at the same position as shown in FIG. 2 or FIG.
  • a plurality of element isolation regions 90 are formed on the surface of the first surface of the first conductivity type semiconductor substrate 10 (FIG. 4A).
  • the plurality of element isolation regions 90 include a first element isolation region 91 and a second element isolation region 92.
  • processing such as ion implantation is performed on the region surrounded by the first element isolation region 91 to form the first impurity diffusion region 20 (FIG. 4B).
  • a resist 93 is formed leaving a region surrounded by the second element isolation region 92, and ion implantation is performed to form the second impurity diffusion region 30 (FIG. 5- (a)).
  • the process is repeated, and the third impurity diffusion region 40, the fourth impurity diffusion region 50, the first gate 60, the second gate 61, and the like are formed in the second impurity diffusion region 30. Further, a tap region having a higher concentration is formed in a region not covered with the element isolation region 90 (FIG. 5- (b)).
  • a plurality of element isolation regions 90 are formed on the surface of the first surface of the first conductivity type semiconductor substrate 10 (FIG. 4A).
  • a resist 94 is formed while leaving a partial region of the surface of the first impurity diffusion region 20 in a region surrounded by the second element isolation region 92, and ion implantation is performed to perform the second impurity diffusion region. 30 is formed (FIG. 4- (c)).
  • a region other than a partial region on the surface of the first impurity diffusion region 20 is a region where the contact 53 is formed in a later step.
  • the process is repeated, and the third impurity diffusion region 40, the fourth impurity diffusion region 50, the first gate 60, the second gate 61, and the like are formed in the second impurity diffusion region 30. Further, a tap region having a higher concentration is formed in a region not covered with the element isolation region 90 (FIG. 4- (d)).
  • FIG. 6 shows a plan view of the semiconductor device 200 or the semiconductor device 300 after the step of FIG. 4- (d).
  • the first impurity diffusion region 20, the second impurity diffusion region 30, the third impurity diffusion region 40, the third impurity diffusion region 41, and the fourth impurity diffusion region 50 on the surface of the semiconductor device 200 or the semiconductor device 300.
  • the arrangement is indicated by a broken line.
  • the second impurity diffusion region 30 is not formed under the portion of the fourth impurity diffusion region 50 where the contact 53 is formed, and the first impurity diffusion region 20 is formed.
  • the difference between the method for manufacturing a semiconductor device according to the present invention and the method for manufacturing a conventional semiconductor device is only the difference in the shape of the resist 93 and the resist 94 to be formed. Therefore, it is possible to manufacture the semiconductor device according to the present invention without making a major change in manufacturing equipment.
  • the first conductivity type is P type and the second conductivity type is N type.
  • the first conductivity type may be N type and the second conductivity type may be P type.
  • DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 20 ... 1st impurity diffusion region, 21 ... Tap region, 30 ... 2nd impurity diffusion region, 32 ... Tap region, 40 ... 3rd impurity diffusion region, 41 ... 3rd impurity diffusion region, 42 ... Tap Region 43... Tap region 48. Contact 49. Contact 50. Fourth impurity diffusion region 51. Tap region 52. Silicide 53 53 Contact 60 First gate 61 61 Second gate 80. Tap region, 90 ... element isolation region, 91 ... first element isolation region, 92 ... second element isolation region, 93 ... resist, 94 ... resist, 100 ... semiconductor device, 101 ... first wiring, 102 ...

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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2012/007661 2011-12-09 2012-11-29 半導体装置 Ceased WO2013084451A1 (ja)

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US14/358,982 US9312329B2 (en) 2011-12-09 2012-11-29 Semiconductor device
CN201280060455.1A CN103988305A (zh) 2011-12-09 2012-11-29 半导体装置
US15/049,839 US9859359B2 (en) 2011-12-09 2016-02-22 Semiconductor device

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JP2011-269891 2011-12-09
JP2011269891A JP5849670B2 (ja) 2011-12-09 2011-12-09 半導体装置

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US15/049,839 Division US9859359B2 (en) 2011-12-09 2016-02-22 Semiconductor device

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JP6894715B2 (ja) * 2017-01-31 2021-06-30 ラピスセミコンダクタ株式会社 半導体装置
JP2019029399A (ja) * 2017-07-26 2019-02-21 パナソニックＩｐマネジメント株式会社 撮像装置
US12495617B2 (en) * 2023-02-17 2025-12-09 Vanguard International Semiconductor Corporation Semiconductor structure and electrostatic discharge protection device

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TWI497683B (zh) 2015-08-21
US20140312462A1 (en) 2014-10-23
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US20160204095A1 (en) 2016-07-14

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