WO2012017796A9 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2012017796A9 WO2012017796A9 PCT/JP2011/066063 JP2011066063W WO2012017796A9 WO 2012017796 A9 WO2012017796 A9 WO 2012017796A9 JP 2011066063 W JP2011066063 W JP 2011066063W WO 2012017796 A9 WO2012017796 A9 WO 2012017796A9
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Definitions
- an epitaxial layer of silicon carbide having an n conductivity type is formed on the main surface of substrate 1 made of silicon carbide.
- the epitaxial layer becomes the breakdown voltage holding layer 2.
- Epitaxial growth for forming the breakdown voltage holding layer 2 is a CVD using, for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) as a source gas and using, for example, hydrogen gas (H 2 ) as a carrier gas. It can be implemented by law.
- the node of the n-type impurity of the breakdown voltage holding layer 2 can be, for example, 5 ⁇ 10 15 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less.
- a gate insulating film 8 is formed so as to extend from the inside of the trench 6 to the upper surfaces of the n-type source contact layer 4 and the p-type contact region 5.
- the material and forming method of the gate insulating film 8 are the same as the material and forming method of the gate insulating film 8 in FIG. In this way, the structure shown in FIG. 21 is obtained.
- the silicon carbide layer has a plurality of mesa structures in which the side surface 20 constitutes a side surface on the main surface opposite to the surface facing the substrates 1 and 31, as shown in FIGS. May be included.
- the surface portion of the silicon carbide layer located between the plurality of mesa structures and continuing to the side face 20 (the bottom of the groove 6 located between the side faces of the plurality of mesa structures) is substantially a ⁇ 000-1 ⁇ plane. Also good.
- the upper surface continuous with the side surface 20 may be substantially a ⁇ 000-1 ⁇ plane.
- the semiconductor device may further include an electric field relaxation region 7 formed between a plurality of mesa structures.
- the electric field relaxation region 7 exists when the drain electrode 14 is formed on the back side of the substrates 1 and 31 (the back side opposite to the main surface where silicon carbide is formed on the substrates 1 and 31).
- the breakdown voltage between the electrode (for example, the gate electrode 9) and the drain electrode 14 between the mesa structures can be increased.
- the side surface 20 formed in the silicon carbide layer is substantially any of the ⁇ 03-3-8 ⁇ plane, the ⁇ 01-1-4 ⁇ plane, and the ⁇ 100 ⁇ plane.
- These side surfaces 20 which are so-called semipolar surfaces can be used as active regions (for example, channel regions) of the semiconductor device.
- these side surfaces 20 are stable crystal planes, when the side surfaces 20 are used as active regions such as channel regions, than when other crystal surfaces (for example, (0001) planes) are used as channel regions, The leakage current can be sufficiently reduced and a high breakdown voltage can be obtained.
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Abstract
Description
図1および図2を参照して、本発明による半導体装置の実施の形態1を説明する。
そして、このレジスト膜をマスクとして用いて、エッチングにより層間絶縁膜10およびゲート絶縁膜8を部分的にエッチングにより除去する。この結果、層間絶縁膜10およびゲート絶縁膜8には開口部11(図11参照)が形成される。この開口部11の底部においては、p型のコンタクト領域5およびn型ソースコンタクト層4の一部が露出した状態となる。その後、当該開口部11の内部を充填するとともに、上述したレジスト膜の上部表面上を覆うようにソース電極12(図11参照)となるべき導電体膜を形成する。その後、薬液などを用いてレジスト膜を除去することにより、レジスト膜上に形成されていた導電体膜の部分を同時に除去する(リフトオフ)。この結果、開口部11の内部に充填された導電体膜によりソース電極12を形成できる。このソース電極12はp型のコンタクト領域5およびn型ソースコンタクト層4とオーミック接触したオーミック電極である。
図15を参照して、本発明による半導体装置の実施の形態2を説明する。
次に、ゲート電極9の上部表面、およびp型のコンタクト領域35上において露出しているゲート絶縁膜8の上部表面上を覆うように層間絶縁膜10(図23参照)を形成する。層間絶縁膜10としては、絶縁性を有する材料であれば任意の材料を用いることができる。そして、図11に示した工程と同様に、層間絶縁膜10およびゲート絶縁膜8には開口部11(図23参照)が形成される。当該開口部11の形成方法は、図11における開口部の形成方法と同様である。この開口部11の底部においては、p型のコンタクト領域35およびn型ソースコンタクト層34の一部が露出した状態となる。
また、基板31の裏面側(n型エピタキシャル層32が形成された主表面と反対側の表面側)に、ドレイン電極14(図23参照)を形成する。ドレイン電極14としては、基板31とオーミック接触が可能な材料であれば任意の材料を用いることができる。このようにして、図23に示す構造を得る。
図25を参照して、本発明による半導体装置の参考例を説明する。
図26に示した半導体装置は、基本的には図25に示した半導体装置と同様の構造を備えるが、ガードリング45(図25参照)に代えてJTE(Junction Termination Extension)領域46が形成されている点が異なる。JTE領域46は、導電型がp型の領域である。このようなJTE領域46も、図25に示したガードリング45と同様にイオン注入および活性化アニールを実施することにより形成することができる。そして、図25に示した半導体装置の製造方法と同様に、図26に示した半導体装置の製造方法においても、JTE領域46を形成するためのイオン注入後の活性化アニール処理においては、少なくとも側面20を覆うようなキャップ層を形成することなく活性化アニール処理を実施する。このようにしても、側面20は安定な結晶面(たとえば{03-3-8}面)によって構成されているため、当該活性アニールによっても側面20の表面が荒れるといった問題は発生しない。また、上記図25および図26に示したガードリング45および/またはJET構造は、先に説明した本発明による半導体装置の実施の形態1または実施の形態2に適用することもできる。
上記半導体装置の製造方法において、端面を形成する工程では、メサ構造の側面20と、複数のメサ構造の間に位置し、側面20と連なる炭化珪素層の表面部分(溝6の底壁)とを自己形成的に形成してもよい。具体的には、上記熱エッチングやSiC再構成層22の形成といった手法を用いて、上記メサ構造の側面20として{03-3-8}面を表出させるとともに、上記溝6の底壁にて所定の結晶面(たとえば(0001)面または(000-1)面)を表出させてもよい。この場合、側面20とともに溝6の底壁においても所定の結晶面(たとえば(0001)面または(000-1)面)を安定して形成することができる。
Claims (14)
- 主表面を有する基板(1、31)と、
前記基板(1、31)の前記主表面上に形成され、前記主表面に対して傾斜した端面(20)を含む炭化珪素層(2~5、32~35)とを備え、
前記端面(20)は実質的に{03-3-8}面を含み、
前記端面(20)はチャネル領域を含む、半導体装置。 - 前記炭化珪素層(2~5、32~35)は、前記基板(1、31)と対向する面と反対側に位置する主表面において、前記端面(20)が側面を構成する複数のメサ構造を含み、
複数の前記メサ構造の間に位置し、前記側面と連なる前記炭化珪素層(2~5、32~35)の表面部分が実質的に{000-1}面となっている、請求項1に記載の半導体装置。 - 複数の前記メサ構造において前記側面と連なる上部表面の平面形状が六角形であり、
複数の前記メサ構造は、少なくとも3つのメサ構造を含み、
複数の前記メサ構造は、平面視したときの中心を結んだ線分により正三角形が形成されるように配置されている、請求項2に記載の半導体装置。 - 前記メサ構造の前記上部表面が実質的に{000-1}面となっている、請求項3に記載の半導体装置。
- 前記メサ構造の上部表面上に形成されたソース電極(12)と、
複数の前記メサ構造の間に形成されたゲート電極(9)とを備える、請求項2に記載の半導体装置。 - 複数の前記メサ構造の間に形成された電界緩和領域(7)を備える、請求項2に記載の半導体装置。
- 主表面上に炭化珪素層(2~5、32~35)が形成された基板(1、31)を準備する工程と、
前記炭化珪素層(2~5、32~35)において、前記基板(1、31)の主表面に対して傾斜した端面(20)を形成する工程と、
前記端面(20)上に絶縁膜(8)を形成する工程と、
前記絶縁膜(8)上にゲート電極(9)を形成する工程とを備え、
前記端面(20)を形成する工程では、前記端面(20)が実質的に{03-3-8}面を含むように形成される、半導体装置の製造方法。 - 前記端面(20)を形成する工程では、前記炭化珪素層(2~5、32~35)において、前記基板(1、31)と対向する面と反対側に位置する主表面に、前記端面(20)が側面を構成する複数のメサ構造が形成される、請求項7に記載の半導体装置の製造方法。
- [規則91に基づく訂正 20.02.2012]
前記端面(20)を形成する工程では、上部表面の平面形状が六角形である前記メサ構造が形成される、請求項8に記載の半導体装置の製造方法。 - 前記端面(20)を形成する工程は、
前記炭化珪素層(2~5、32~35)の主表面上に、平面形状が六角形状である複数のマスク層(17)を形成する工程と、
前記マスク層(17)をマスクとして用いて、前記上部表面の平面形状が六角形の前記メサ構造を形成する工程とを含む、請求項9に記載の半導体装置の製造方法。 - 前記端面(20)を形成する工程は、
前記炭化珪素層(2~5、32~35)の主表面上に、互いに間隔を隔てて、平面形状が六角形状である複数のマスク層(17)を形成する工程と、
前記マスク層(17)をマスクとして用いて、複数の前記マスク層(17)の間において露出する前記炭化珪素層(2~5、32~35)を部分的に除去することにより、前記炭化珪素層(2~5、32~35)の主表面に凹部(16)を形成する工程と、
前記凹部(16)の側壁を部分的に除去することにより、上部表面の平面形状が六角形の前記メサ構造を形成する工程とを含む、請求項9に記載の半導体装置の製造方法。 - 前記端面(20)を形成する工程では、前記メサ構造の前記側面を自己形成的に形成する、請求項8に記載の半導体装置の製造方法。
- 前記端面(20)を形成する工程では、前記メサ構造の前記側面と、複数の前記メサ構造の間に位置し、前記側面と連なる前記炭化珪素層(2~5、32~35)の表面部分とを自己形成的に形成する、請求項8に記載の半導体装置の製造方法。
- 前記炭化珪素層(2~5、32~35)に導電性不純物を注入する工程と、
前記注入された導電性不純物を活性化するための熱処理を行なう工程とを備え、
前記熱処理を行なう工程では、前記炭化珪素層(2~5、32~35)の表面は熱処理を行なうための雰囲気ガスに露出した状態になっている、請求項7に記載の半導体装置の製造方法。
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-
2010
- 2010-08-03 JP JP2010174663A patent/JP5707770B2/ja active Active
-
2011
- 2011-07-14 CA CA2783310A patent/CA2783310A1/en not_active Abandoned
- 2011-07-14 WO PCT/JP2011/066063 patent/WO2012017796A1/ja active Application Filing
- 2011-07-14 KR KR1020127011631A patent/KR20130098847A/ko not_active Application Discontinuation
- 2011-07-14 EP EP11814426.0A patent/EP2602822B1/en active Active
- 2011-07-14 US US13/512,456 patent/US20120228640A1/en not_active Abandoned
- 2011-07-14 CN CN201180004823.6A patent/CN102652362B/zh active Active
- 2011-08-01 TW TW100127239A patent/TW201214707A/zh unknown
-
2017
- 2017-01-05 US US15/399,387 patent/US20170117381A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
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JP2012038770A (ja) | 2012-02-23 |
EP2602822A1 (en) | 2013-06-12 |
EP2602822A4 (en) | 2014-01-01 |
WO2012017796A1 (ja) | 2012-02-09 |
CA2783310A1 (en) | 2012-02-09 |
JP5707770B2 (ja) | 2015-04-30 |
EP2602822B1 (en) | 2022-01-19 |
CN102652362B (zh) | 2015-07-08 |
KR20130098847A (ko) | 2013-09-05 |
TW201214707A (en) | 2012-04-01 |
US20170117381A1 (en) | 2017-04-27 |
US20120228640A1 (en) | 2012-09-13 |
CN102652362A (zh) | 2012-08-29 |
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