JP5707770B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5707770B2 JP5707770B2 JP2010174663A JP2010174663A JP5707770B2 JP 5707770 B2 JP5707770 B2 JP 5707770B2 JP 2010174663 A JP2010174663 A JP 2010174663A JP 2010174663 A JP2010174663 A JP 2010174663A JP 5707770 B2 JP5707770 B2 JP 5707770B2
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Description
図1および図2を参照して、本発明による半導体装置の実施の形態1を説明する。
図14を参照して、本発明による半導体装置の実施の形態2を説明する。
図23を参照して、本発明による半導体装置の参考例を説明する。
図24に示した半導体装置は、基本的には図23に示した半導体装置と同様の構造を備えるが、ガードリング45(図23参照)に代えてJTE(Junction Termination Extension)領域46が形成されている点が異なる。JTE領域46は、導電型がp型の領域である。このようなJTE領域46も、図23に示したガードリング45と同様にイオン注入および活性化アニールを実施することにより形成することができる。そして、図23に示した半導体装置の製造方法と同様に、図24に示した半導体装置の製造方法においても、JTE領域46を形成するためのイオン注入後の活性化アニール処理においては、少なくとも側面20を覆うようなキャップ層を形成することなく活性化アニール処理を実施する。このようにしても、側面20は安定な結晶面(たとえば{03−3−8}面)によって構成されているため、当該活性アニールによっても側面20の表面が荒れるといった問題は発生しない。また、上記図23および図24に示したガードリング45および/またはJET構造は、先に説明した本発明による半導体装置の実施の形態1または実施の形態2に適用することもできる。
Claims (14)
- 主表面を有する基板と、
前記基板の前記主表面上に形成され、前記主表面に対して傾斜した端面を含み、第1導電型の第1層と第2導電型の第2層とを含む積層構造を有する炭化珪素層と、
前記端面上において前記第1層および前記第2層に直接接するように設けられた絶縁膜とを備え、
前記端面は{03−3−8}面を含み、
前記端面はチャネル領域を含み、
前記炭化珪素層は前記端面が側面を構成するメサ構造を含み、前記メサ構造の前記側面は、前記メサ構造の全周にわたって前記主表面に対して斜めに傾斜している、半導体装置。 - 前記炭化珪素層は、前記基板と対向する面と反対側に位置する主表面において、前記端面が側面を構成する複数のメサ構造を含み、
複数の前記メサ構造の間に位置し、前記側面と連なる前記炭化珪素層の表面部分が{000−1}面となっている、請求項1に記載の半導体装置。 - 複数の前記メサ構造において前記側面と連なる上部表面の平面形状が六角形であり、
複数の前記メサ構造は、少なくとも3つのメサ構造を含み、
複数の前記メサ構造は、平面視したときの中心を結んだ線分により正三角形が形成されるように配置されている、請求項2に記載の半導体装置。 - 前記メサ構造の前記上部表面が{000−1}面となっている、請求項3に記載の半導体装置。
- 前記メサ構造の上部表面上に形成されたソース電極と、
複数の前記メサ構造の間に形成されたゲート電極とを備える、請求項2〜請求項4のいずれか1項に記載の半導体装置。 - 複数の前記メサ構造の間に形成された電界緩和領域を備える、請求項2〜請求項5のいずれか1項に記載の半導体装置。
- 第1導電型の第1層と第2導電型の第2層とを含む積層構造を有する炭化珪素層が主表面上に形成された基板を準備する工程と、
前記炭化珪素層において、前記基板の主表面に対して傾斜した端面を熱エッチングにより形成する工程と、
前記端面上において前記第1層および前記第2層に直接接するように絶縁膜を形成する工程と、
前記絶縁膜上にゲート電極を形成する工程とを備え、
前記端面を形成する工程では、前記端面が{03−3−8}面を含むように形成される、半導体装置の製造方法。 - 前記端面を形成する工程では、前記炭化珪素層において、前記基板と対向する面と反対側に位置する主表面に、前記端面が側面を構成する複数のメサ構造が形成される、請求項7に記載の半導体装置の製造方法。
- 前記端面を形成する工程では、上部表面の平面形状が六角形である前記メサ構造が形成される、請求項8に記載の半導体装置の製造方法。
- 前記端面を形成する工程は、
前記炭化珪素層の主表面上に、平面形状が六角形状である複数のマスク層を形成する工程と、
前記マスク層をマスクとして用いて、前記上部表面の平面形状が六角形の前記メサ構造を形成する工程とを含む、請求項9に記載の半導体装置の製造方法。 - 前記端面を形成する工程は、
前記炭化珪素層の主表面上に、互いに間隔を隔てて、平面形状が六角形状である複数の
マスク層を形成する工程と、
前記マスク層をマスクとして用いて、複数の前記マスク層の間において露出する前記炭化珪素層を部分的に除去することにより、前記炭化珪素層の主表面に凹部を形成する工程と、
前記凹部の側壁を部分的に除去することにより、上部表面の平面形状が六角形の前記メサ構造を形成する工程とを含む、請求項9に記載の半導体装置の製造方法。 - 前記端面を形成する工程では、前記メサ構造の前記側面を自己形成的に形成する、請求項8〜請求項11のいずれか1項に記載の半導体装置の製造方法。
- 前記端面を形成する工程では、前記メサ構造の前記側面と、複数の前記メサ構造の間に位置し、前記側面と連なる前記炭化珪素層の表面部分とを自己形成的に形成する、請求項8〜請求項11のいずれか1項に記載の半導体装置の製造方法。
- 前記炭化珪素層に導電性不純物を注入する工程と、
前記注入された導電性不純物を活性化するための熱処理を行なう工程とを備え、
前記熱処理を行なう工程では、前記炭化珪素層の表面は熱処理を行なうための雰囲気ガスに露出した状態になっている、請求項7〜請求項13のいずれか1項に記載の半導体装置の製造方法。
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CA2783310A CA2783310A1 (en) | 2010-08-03 | 2011-07-14 | Semiconductor device and method for manufacturing same |
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EP11814426.0A EP2602822B1 (en) | 2010-08-03 | 2011-07-14 | Semiconductor device and process for production thereof |
US13/512,456 US20120228640A1 (en) | 2010-08-03 | 2011-07-14 | Semiconductor device and method for manufacturing same |
KR1020127011631A KR20130098847A (ko) | 2010-08-03 | 2011-07-14 | 반도체 장치 및 그 제조 방법 |
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