WO2011122882A4 - 반도체 템플릿 기판, 반도체 템플릿 기판을 이용하는 발광 소자 및 이의 제조 방법 - Google Patents
반도체 템플릿 기판, 반도체 템플릿 기판을 이용하는 발광 소자 및 이의 제조 방법 Download PDFInfo
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- light emitting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
Definitions
- the present invention relates to a semiconductor template substrate, a light emitting device using the semiconductor template substrate, and a method of manufacturing the same, and more particularly to a semiconductor template substrate having reduced crystal defects and easy separation, .
- the conventional semiconductor light emitting device is formed of a horizontal element or a vertical element by using an insulating substrate such as sapphire.
- a conventional horizontal semiconductor light emitting device is shown in FIG. 6A and a conventional vertical semiconductor light emitting device is shown in FIG. 6B.
- the horizontal semiconductor light emitting device comprises a buffer layer 2, an n-type nitride semiconductor layer 3, an active layer 4 and a p-type nitride semiconductor layer 5 sequentially formed on a sapphire substrate 1.
- the p-type electrode 6 is formed on the upper surface of the p-type nitride semiconductor layer 5.
- the n-type electrode 7 removes a part of the p-type nitride semiconductor layer and the active layer by etching or the like, Is formed on the nitride semiconductor layer (3).
- the horizontal flat type light emitting device as shown in FIG. 6A the light emitting area is relatively small and the surface leakage current is increased to lower the light emitting performance of the device and the area through which the current passes is also relatively small, And the lifetime of the device is shortened due to heat generation.
- the p-type nitride semiconductor layer is formed in the substrate in the same manner as the horizontal type.
- the insulating substrate is separated from the light emitting device before the formation of the n-type electrode 7, And the n-type electrode 7 is formed on the lower surface of the layer.
- a laser lift-off method is generally used to separate the insulating substrate.
- the laser beam as the strong energy source is irradiated on the rear surface of the transparent sapphire substrate, laser beam absorption is strongly generated at the interface between the buffer layer and the sapphire substrate, and thus a temperature of 900 DEG C or more occurs instantaneously, And the sapphire substrate can be separated.
- An object of the present invention is to provide a semiconductor template substrate which does not damage a semiconductor substrate by a separation process.
- Another aspect of the present invention provides an excellent semiconductor light emitting device.
- Another aspect of the present invention provides a method of manufacturing an excellent semiconductor light emitting device.
- the present invention uses a separation layer in which the light emitting device is easily separated from the substrate in the step of forming the light emitting device.
- the light emitting device according to an embodiment of the present invention includes an inverse pyramid structure by the separation layer.
- a light emitting device includes a semiconductor layer, a light emitting layered structure, and an inverted pyramid structure.
- the luminescent stack structure is formed on the first surface of the semiconductor layer and the inverted pyramid structure is formed on the second surface of the semiconductor layer which is the opposite surface of the first surface and extends in the vertical direction on the second surface The cross sectional area decreases.
- One aspect of the present invention provides a method of manufacturing a light emitting device.
- a buffer layer is formed on the substrate.
- a plurality of pyramidal structures protruding on the buffer layer are formed.
- a semiconductor layer spaced apart from the buffer layer is formed through crystal growth from the top of the pyramid structure.
- the pyramid structure connects the buffer layer and the semiconductor layer.
- a light emitting stack structure is formed on the semiconductor layer. The semiconductor layer and the buffer layer are separated by cutting the pyramid structure or separating the surface contacting the pyramid structure with the buffer layer.
- One aspect of the present invention provides a method of manufacturing a light emitting device.
- a buffer layer is formed on the substrate.
- the buffer layer is divided into a plurality of individual light emitting element regions to form separated individual semiconductor layers on the individual light emitting element regions.
- the individual semiconductor layers formed in the individual light emitting element regions and the buffer layers corresponding to the individual light emitting element regions are connected by a plurality of projections.
- a light emitting stack structure is formed on the individual semiconductor layers.
- the semiconductor layer and the buffer layer are separated by cutting the pyramid structure or separating the surface contacting the pyramid structure with the buffer layer.
- One aspect of the present invention provides a method of manufacturing a light emitting device.
- a buffer layer is formed on the substrate.
- the buffer layer is divided into a plurality of light emitting device regions, and a plurality of pyramid structures are formed in the respective light emitting device regions.
- a semiconductor layer having a cleaved surface for separating the light emitting device regions is formed by growing the pyramid structure from the top of the pyramid structure.
- the semiconductor layer and the buffer layer are connected by the pyramid structure, and the semiconductor layer and the buffer layer are spaced apart from each other.
- a light emitting layered structure is formed on the semiconductor layer to form individual preliminary light emitting devices.
- the pyramid structure is cut to peel off the semiconductor layer and the buffer layer. And separates the individual preliminary light emitting devices about the cleaved surface.
- One aspect of the present invention provides a method of manufacturing a light emitting device.
- a buffer layer is formed on the substrate.
- the buffer layer is divided into a plurality of light emitting device regions, and a plurality of pyramid structures are formed in the respective light emitting device regions.
- the pyramid structure is grown from the top of the pyramid structure to form a semiconductor layer corresponding to each of the light emitting device regions and spaced apart from each other.
- the semiconductor layer and the buffer layer are connected by the pyramid structure, and the semiconductor layer and the buffer layer are spaced apart from each other.
- a light emitting stack structure is formed on each of the semiconductor layers to form individual light emitting devices.
- the pyramid structure is cut to form each light emitting device.
- the semiconductor substrate template includes a buffer layer formed on a substrate, a plurality of pyramid structures formed on the buffer layer, and a semiconductor layer spaced apart from the buffer layer and connected to the buffer layer by the plurality of pyramid structures to form a semiconductor layer on the buffer layer.
- the semiconductor substrate template includes a buffer layer formed on a substrate and divided into a plurality of preliminary luminescent regions, a plurality of protrusions protruding upward from individual preliminary luminescent regions of the plurality of preliminary luminescent regions, a plurality of protrusions formed on the protrusions and spaced apart from the buffer layer And an individual semiconductor layer formed on the individual preliminary luminescent region.
- the semiconductor substrate can be easily separated from the insulating substrate, the semiconductor substrate is not damaged, and a light emitting device having excellent performance can be manufactured.
- the concavo-convex pattern can be formed on the bottom surface of the semiconductor substrate without a separate additional process, the manufacturing process can be simplified.
- the semiconductor substrate may not be damaged.
- FIG. 1A and 1B illustrate a method of manufacturing a light emitting device according to an embodiment of the present invention
- FIGS. 2A and 2B are views for explaining a method of manufacturing a light emitting device according to another embodiment of the present invention.
- 3A to 3G are views for explaining a method of manufacturing a light emitting device according to another embodiment of the present invention.
- Fig. 4 is a view schematically showing a jig for electrode formation
- 5A to 5C are diagrams illustrating an intermediate product of a light emitting device manufactured according to an embodiment
- 6A and 6B are views schematically showing a conventional horizontal light emitting device and a vertical light emitting device.
- this embodiment is an embodiment of growing an n-type GaN crystal by using a sapphire substrate.
- the materials used for the substrate and the buffer layer, the semiconductor layer, and the light-emitting laminated structure are not limited by these embodiments.
- a buffer layer 20 is formed on an insulating substrate 10 and a mask layer 30 having a plurality of exposure patterns 39 is formed on the buffer layer 20 in step S110.
- the exposed pattern 39 is shown in FIG. 1A as a circle, the exposed pattern 39 may be a polygon such as a square, a triangle, a hexagon, and the like, and the arrangement thereof may vary.
- the substrate 10 may be selected from the group consisting of sapphire substrates or various materials such as silicon, GaAs, InP, and substrates including SiC.
- the buffer layer 20 may be formed by growing a GaN crystal.
- an n-type GaN crystal is grown by growing the crystal to a thickness of 2 to 5 ⁇ using an HVPE crystal growing apparatus.
- the buffer layer may comprise AlxGa (1-x) N ( 0 ⁇ x ⁇ 1) layer or an Al 2 O 3, AlN or ZnO.
- SiO 2 , Si 3 N 4 , Cr or Au, or a metal such as Ti or Ni may be used.
- an exposure pattern 39 is formed by a photolithography process to form a part of the buffer layer 20 .
- SiO 2 or Si 3 N 4 may be deposited to a thickness of 500 to 5000 ⁇ to form an exposure pattern, or a metal such as Cr or Au, Ti, or Ni may be deposited in an exposed pattern.
- the mask layer 30 can be formed using a lift-off method. A photoresist is coated on the buffer layer 20, and an exposure process is performed. Then, a developing process is performed to form a photoresist pattern. As a result, the buffer layer 20 having a desired pattern shape is exposed, and the remaining portions are covered with the photoresist pattern. A preliminary mask layer (not shown) is formed on the photoresist pattern formed on the buffer layer 20. Then, the photoresist pattern and the preliminary mask layer formed on the photoresist pattern are removed. Thus, a mask layer 30 having a desired pattern can be formed on the buffer layer 20. [
- the diameter of the exposed pattern 39 is approximately 0.5-5 ⁇ m, and the interval between adjacent exposed patterns 39 is 0.5-10 ⁇ m.
- step S120 crystals are grown from the buffer layer 20 exposed by the exposure pattern 39.
- the pyramidal structure 40 is formed from the inside of the exposed pattern 39 of the mask layer 30.
- the pyramid structure 40 means a shape in which the sectional area becomes narrower toward the upper part.
- the pyramid structure 40 may be a cone or hexagonal (polygonal) structure.
- the basic crystal structure of GaN is a wurtzite structure, when the exposed pattern 39 is grown to have a horn shape from the exposed buffer layer 20, a hexagonal horn structure can be formed.
- the diameter of the bottom surface of the pyramid structure 40 may be approximately the same as or slightly larger than that of the exposed pattern 39.
- the diameter of the exposed pattern 39 is 0.5 to 5 ⁇ ⁇ , ) Of about 0.5 to 7.5 mu m, which is about 1 to 1.5 times the diameter of the substrate.
- the bottom surface of the pyramid structure 40 is overgrowthed and becomes wider than the exposure pattern 39.
- the pyramid structure 40 is projected onto the mask layer 30. [
- the pyramid structure 40 may be formed in a hexagonal conical structure.
- an example of crystal growth conditions of HVPE is as follows. Ga metal is used as a raw material of Ga, ammonia (NH 3) is used as a raw material of N, and Te or Si is synthesized into a Ga solution to form n-type GaN.
- the substrate on which the exposed pattern 39 is formed is mounted in a reaction tube and GaN crystal is grown at 1000 to 1100 ° C to form a hexagonal cone structure of n-type GaN.
- the composition of the pyramid structure 40 may be AlxGa (1-x) N (0 ⁇ x ⁇ 1).
- the composition of the buffer layer 30 and the composition of the pyramid structure 40 may be the same or different by giving a change to the source used when the pyramid structure 40 is grown.
- the composition of the buffer layer 20 and the composition of the pyramid structure 40 are controlled by changes in the source. That is, the composition of the buffer layer 20 and the composition of the pyramid structure 40 may be the same or different.
- 5A is a SEM photograph of a pyramid structure 40 formed according to an embodiment of the present invention.
- a semiconductor layer 50 is formed in step S130.
- the semiconductor layer 50 may be formed using an HVPE crystal growing apparatus.
- the growth layer grown on the side of the pyramid structure 40 may be bonded to form the semiconductor layer 50. That is, in the mask layer 30, crystals hardly grow from the buffer layer 20, and the GaN crystal starts to grow on the inclined side of the exposed pyramid structure 40, and a crystal layer grown in the adjacent semiconductor layer 50 And the semiconductor layer 50 is formed.
- the height of the semiconductor layer 50 is preferably such that the pyramid structure 40 is thick enough to sustain the thickness of the semiconductor layer 50.
- the height of the semiconductor layer 50 may be 1 to 100 [mu] m.
- the composition of the pyramid structure 40 may be GaN or AlxGa (1-x) N (0 ⁇ x ⁇ 1).
- the source for growing the pyramid structure 40 and the source for growing the semiconductor layer 50 are made different from each other in the growth method, layers having different compositions can be obtained.
- a Ga source and ammonia are reacted to form the pyramid structure 40
- a Ga source, an Al source, and ammonia are reacted to form the semiconductor layer 50.
- the pyramid structure 40 is formed of GaN
- the semiconductor layer 50 is formed of AlGaN.
- the Al composition of the AlGaN layer can be controlled by adjusting the amount of Al.
- the composition of the pyramid structure 40 is only one example, and it is also possible for the user to change the source used for forming the pyramid structure 40 to form the pyramid structure 40 having another composition.
- the semiconductor layer 50 may be a planarized layer having a flat upper surface.
- crystals begin to grow from about a half of the height of the pyramid structure 40 to the sloped side of the pyramid structure 40, so that the crystals grown in the adjacent pyramid structure 40 fit together,
- the semiconductor layer 50 can be formed by maintaining growth until the region becomes flat.
- the lower surface of the semiconductor layer 50 may be formed to have a height of 1/3 of the pyramid structure 40.
- the spirit of the present invention is not limited by these heights.
- a vacant space portion surrounded by the semiconductor layer 50, the pyramid structure 40, and the mask layer 30 is formed.
- the separation layer 90 is formed between the lower surface of the semiconductor layer 50 and the mask layer 30.
- 5B is a side view SEM image of the pyramid structure 40 and the semiconductor layer 50 formed in accordance with the embodiment of the present invention, and the vacant space next to the pyramid structure 40 can be identified.
- a light emitting laminated structure 60 is formed on the semiconductor layer 50.
- an n-type AlGaN cladding layer, an AlGaN active layer, a p-type AlGaN cladding layer, a p-type GaN cap layer, or the like may be formed to form a light emitting laminate structure.
- the luminescent laminate structure 60 can be formed using the HVPE crystal growth method.
- a cladding layer containing n-type AlxGa (1-x) N (0 ⁇ x ⁇ 1), an active layer containing AlxGa (1-x) N (0 ⁇ x ⁇ -x) N (0 ⁇ x ⁇ 1) and a p-type GaN cap layer can be sequentially formed.
- the material used for each layer of the light-emitting laminated structure 60 and the stacking order can be appropriately changed depending on the desired light-emitting wavelength range, light output, or type of light-emitting element.
- the buffer layer 20, the semiconductor layer 50, and the light-emitting laminated structure 60 can be formed in a sequential manner since the buffer layer 20, the semiconductor layer 50 and the light-emitting laminated structure 60 can all be formed by the HVPE method. have.
- the buffer layer 20, the semiconductor layer 50, and the luminescent laminate structure 60 may be formed by an in-situ process.
- step S150 the substrate 10, the buffer layer 20, and the mask layer 30 are separated from the luminescent laminate structure 60. Irregular irregularities may be formed on the separated surface.
- the separation of the substrate 10 and the like can be performed by application of ultrasonic waves, physical vibration, or impact.
- the semiconductor layer 50 and the buffer layer 20 are connected only to the pyramid structure 40 when the substrate 10 on which the light emitting laminate structure 60 is formed is placed in a solution such as acetone or methanol or distilled water and subjected to ultrasonic wave,
- separation layer 90 the pyramid structure 40 is severed and separation occurs. Alternatively, the bottom portion of the pyramid is separated from the substrate. Alternatively, the pyramid structure 40 may be cut by applying a simple impact.
- an inverted pyramid structure is formed on the lower surface of the semiconductor layer 50.
- the inverted pyramid structure means a structure in which the cross sectional area increases as the distance from the bottom surface of the semiconductor layer 50 increases. That is, the inverted pyramid structure formed on the semiconductor layer 50 is a structure for facilitating the separation of the light emitting device and the substrate 10 for forming the light emitting device.
- the laser beam is irradiated to the pyramidal structure 40 of the separation layer 90 having a relatively weak bonding force to separate the laser beam from the laser beam. That is, thermal or mechanical damage due to the laser beam is applied only to a narrow region of the lower portion of the pyramid, so that the substrate 10 can be separated without damaging the luminescent laminate structure 60 at the time of substrate separation.
- strain may be applied to the substrate 10 and / or the buffer layer 20 to generate stress in the pyramid structure 40, thereby cutting the pyramid structure 40.
- the separation of the light emitting element from the substrate 10 is facilitated and complicated processes are omitted owing to the presence of the separation layer 90.
- the light emitting element is separated from the substrate 10, It is possible to manufacture a light emitting device having good quality.
- FIG. 5C is an SEM photograph of the bottom surface of the separated light-emitting laminated structure, in which pyramid patterns formed by cutting the pyramid structure 40 can be confirmed.
- a p-type electrode 71 is formed on the upper portion of the light-emitting laminated structure 60, and an n-type electrode 72 is formed on the lower surface 51 of the separated semiconductor layer 50, .
- the n-type electrode 72 may be formed on the reverse pyramid structure or may be formed on the lower surface 51 of the semiconductor layer 50.
- Each of the electrodes 71 and 72 may be completed after forming a separate intermediate layer according to the design.
- a reverse pyramid structure may be formed on the bottom surface 51 of the semiconductor layer 50 by cutting the pyramid structure 40.
- a protrusion pattern may be formed on the lower surface 51 of the semiconductor layer 50 without a separate pattern process.
- the p-type electrode 71 may be formed immediately before the separation step S150 after the formation of the light-emitting laminated structure 60 (S140).
- the substrate 10 formed up to the semiconductor layer 50 which is a structure before the step of separating the substrate 10 from the substrate 10, may be used as a semiconductor template substrate in step S140. It is also a matter of course that it is also possible to form various vertical semiconductor devices by separating the separation layer after forming various electronic device structures on the semiconductor template substrate.
- the second embodiment is similar to the first embodiment, but relates to a method of manufacturing a light emitting device by dividing a region of a separation layer to form regions having different bonding forces. Therefore, when forming the mask layer 30, the diameter and spacing of the exposure pattern are differently formed by dividing the first region 31 having a relatively large coupling force and the region 32 having a relatively small coupling force, as shown in FIG. 2A. That is, the diameter and spacing of the exposure pattern are smaller in the first region 31 having a relatively large coupling force, as compared with the second region 32 having a small coupling force.
- the diameter and spacing of the exposure pattern of the first region 31 may be 1 ⁇ ⁇
- the diameter and spacing of the exposure pattern of the second region 32 may be of the order of 3 ⁇ ⁇ .
- the pyramid structure 40 formed in the first region 31 is more inclined than the pyramid structure 40 in the second region 32, So that there is relatively little empty space.
- the separation layer 90 formed between the mask layer 30 and the semiconductor layer 50 is divided into a first separation portion 91 having a relatively small coupling force and a second separation portion 92 having a relatively large coupling force .
- the second separating unit having relatively low bonding force is separated by a physical force that may occur in the process after forming the semiconductor layer 50, So that the light emitting stacked structure is supported by the light emitting portion 91. Therefore, the case of the second embodiment is useful when the p-type electrode is formed first before the separation layer 90 is separated.
- FIGS. 3A to 3D a method of manufacturing a light emitting device according to another embodiment of the present invention will be described with reference to FIGS. 3A to 3D.
- the method of manufacturing the light emitting device described above is mainly described as a method of manufacturing one light emitting device, in the method of manufacturing the light emitting device of the present embodiment, a plurality of light emitting devices are formed on one substrate and are easily separated from the substrate And a method of manufacturing a light emitting device in which each light emitting device can be easily separated from each other. Detailed description of the manufacturing method similar to that of FIG. 1 will be omitted.
- a buffer layer 20 is formed on a substrate 10 as described with reference to FIG. 1, and a mask layer 30 as shown in FIG. 3A is formed on the buffer layer 20.
- the mask layer 30 has a plurality of light emitting chip areas A.
- each light emitting chip region A is shown as a quadrangle.
- the light emitting chip region A is not limited to a quadrangle, but may be formed according to various designs such as a circle or a hexagon.
- Each light emitting chip area A is spaced apart by a predetermined chip distance d.
- a plurality of exposure patterns 39 are formed in each of the light emitting chip regions of the mask layer 30.
- cleavage surface 55 may be formed to divide the semiconductor layer 50 into individual individual light-emitting laminated structures.
- the depth of the cleavage surface 55 can be adjusted to a desired depth by the chip spacing d, the conditions of the process, and the like.
- the depth of the cleaved surface 55 is adjusted by adjusting the ratio between the height h and the chip distance d.
- the chip spacing d may be adjusted to be less than 0.4 to 0.6 times the height h so that only a portion of the semiconductor chip 50 is connected as shown in Figure 3C, Structure can be formed.
- a light emitting laminated structure 60 is formed on the semiconductor layer 50 as shown in FIG. 3C.
- the light emitting laminate structure 60 is formed by the cleavage planes 51 of the semiconductor layer 50 so as to be divided into the respective light emitting chip regions.
- the light emitting devices are separated in the vertical and horizontal directions.
- the separation process may be performed in various orders.
- the substrate and the like may be firstly separated in the vertical direction by applying ultrasonic waves, vibration, shock, etc. around the separation layer 90, and then each of the light emitting devices may be separated in the horizontal direction .
- the separation in the horizontal direction can be performed by various methods such as physical impact, pressurization and the like.
- the film can be pasted on the elements and then pressed with a roller to separate each light emitting element.
- vertical separation and horizontal separation may be performed simultaneously by applying appropriate vibration or pressure.
- a p-type electrode (not shown) is formed on the upper part of the light emitting laminated structure 60, and an n-type electrode (not shown) is formed on the lower surface of the separated semiconductor layer 50 to complete a light emitting device .
- Each of the electrodes may be completed after forming a separate intermediate layer according to the design.
- the p-type electrode (not shown) may be formed at an appropriate time after the horizontal separation step, before or after the vertical separation step.
- an n-type electrode (not shown) may be formed before or after the horizontal separation step.
- the electrode forming jig 200 as shown in Fig. 4 can be used.
- the jig 200 is provided with a chip mounting portion 210 of a suitable size capable of accommodating a plurality of light emitting chips in a matrix form. The chips are sorted by the chip sorting device and inserted into the respective chip mounting portions 210 of the jig, and then the electrodes are formed.
- the semiconductor layers 50 may be formed separately from each other in the respective light emitting device units.
- the chip spacing d may be adjusted to be greater than 0.4 to 0.6 times the height h to form individually separated semiconductor layers 50 and individual light emitting device structures 60. That is, the light emitting device structure 60 may be formed on each semiconductor layer 50 as shown in FIG. 3F and separated as shown in FIG. 3G to obtain the individual light emitting device structure 60.
- a p-type electrode (not shown) is formed on the light emitting layered structure 60, and an n-type electrode (not shown) is formed on the lower surface of the separated semiconductor layer 50 to complete the light emitting device.
- the light emitting device of the present invention can reduce the crystal defect density and minimize the substrate dependency by forming the light emitting laminated structure after forming the semiconductor layer on the pyramid structure of the semiconductor layer.
- the present invention is not only required to use an expensive conductive metal substrate at the time of manufacturing a vertical light emitting device, but also is useful because a substrate can be easily separated without requiring a laser lift-off process, which is essential when using an insulating substrate . Therefore, the production process of the vertical type light emitting device is simplified, and the production cost can be greatly reduced.
- planarization nitride semiconductor layer is formed by forming the hexagonal horn structure of the light emitting chip region by adjusting the chip interval of the light emitting chip region and the height of the stacked light emitting structure, It is possible to simplify the production process.
- a planarizing nitride semiconductor layer can be provided with a concavo-convex pattern in which a hexagonal horn structure is partially cut off, thereby maximizing light emission efficiency without further processing.
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Abstract
Description
Claims (36)
- 반도체층상기 반도체층 제1 면 상에 형성된 발광 적층 구조물 및상기 제1 면의 반대면인 상기 반도체층의 제2 면에 형성되고, 상기 제2 면에서 수직인 방향으로 연장될수록 단면적이 감소하는 복수의 역피라미드 구조물을 포함하는 발광 소자.
- 제 1 항에 있어서,상기 역피라미드 구조물의 단면은 원형 또는 다각형을 포함하는 발광 소자.
- 제 2 항에 있어서,상기 역피라미드 구조물의 직경은 0.5-5 μm이고, 역피라미드 구조물의 간격은 0.5~10 μm인 발광 소자.
- 제 3 항에 있어서,상기 반도체층은 질화물을 포함하고, 상기 역피라미드 구조물의 횡단면은 상기 제2 면에 평행한 발광소자.
- 제 3 항에 있어서,상기 역피라미드 구조물과 상기 반도체층은 질화물을 포함하는 발광 소자
- 제 5 항에 있어서,상기 반도체층은 기판으로부터 분리된 반도체층이고, 상기 역피라미드 구조물은 상기 기판과 상기 반도체층의 분리를 용이하도록 하는 발광 소자.
- 제 1 항에 있어서,상기 역피라미드 구조물은 제1 경사를 갖는 제1 역피라미드 구조물 및 상기 제1 경사와 상이한 경사를 갖는 제2 역피라미드 구조물을 포함하는 발광 소자.
- 제 2 항에 있어서,상기 제1 역피라미드 구조물의 단면적은 상기 제2 역피라미드 구조물의 단면적보다 큰 발광 소자.
- 반도체층,상기 반도체층 제1 면 상에 형성된 발광 적층 구조물 및상기 제1 면의 반대면인 상기 반도체층의 제2 면에 형성된 높이가 상이한 복수의 요철을 포함하는 발광 소자.
- 제 1 항 내지 제 9 항의 발광 소자를 포함하는 조명.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층 상에 돌출된 복수의 피라미드 구조물을 형성하는 단계;상기 피라미드 구조물의 상부로부터 결정 성장을 통해 상기 버퍼층과 이격된 반도체층을 형성하되, 상기 피라미드 구조물은 상기 버퍼층과 상기 반도체층을 연결하고 있는, 단계;상기 반도체층 상에 발광 적층 구조물을 형성하는 단계 및상기 피라미드 구조물을 절단하거나 또는 상기 피라미드 구조물과 상기 버퍼층과 접촉하는 면을 분리하여 상기 반도체층과 상기 버퍼층을 분리하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 11 항에 있어서,상기 버퍼층 상에 돌출된 복수의 피라미드 구조물을 형성하는 단계는상기 버퍼층의 일부를 결정 성장시켜 복수의 피라미드 구조물을 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 12 항에 있어서,상기 버퍼층의 일부를 결정 성장시키는 단계는상기 버퍼층 상에 노출 패턴을 갖는 마스크층을 형성시키는 단계;상기 노출 패턴에 의해 노출되는 상기 버퍼층의 일부를 결정 성장시키는 단계를 포함하는 발광 소자의 제조 방법.
- 제 12 항에 있어서,상기 반도체층 및 상기 발광 적층 구조물은 질화물을 포함하는 물질을 이용하여 형성되고, 상기 반도체층을 형성하는 단계 및 상기 발광 적층 구조물을 형성하는 단계는 순차적으로 수행되는 발광 소자의 제조 방법.
- 제 12 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계는상기 피라미드 구조물의 일부를 상기 반도체층에 잔류시키는 단계를 포함하는 발광 소자의 제조 방법.
- 제 15 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계 이후에,상기 발광 적층 구조물의 제 1면에 제 1전극을 형성하고, 상기 피라미드 구조물의 일부가 잔류하는 상기 반도체층의 제2 면에 제 2전극을 형성하는 단계를 더 포함하는 발광 소자의 제조 방법.
- 제 14 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계 이전에,상기 발광 적층 구조물의 제 1면에 제 1전극을 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 15 항에 있어서,상기 피라미드 구조물을 절단하여 상기 반도체층과 상기 버퍼층을 분리하는 단계는 물리적 충격을 이용하는 발광 소자의 제조 방법.
- 제 15 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계는 상기 기판에 스트레인을 가하는 단계를 포함하는 발광 소자의 제조 방법.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층을 복수의 개별 발광 소자 영역으로 구분하여, 상기 개별적인 발광 소자 영역 상에 분리된 개별 반도체층을 형성하되, 상기 개별 발광 소자 영역에 형성된 개별 반도체층과 상기 개별 발광 소자 영역에 대응하는 버퍼층은 복수의 돌기에 의해 연결되어 있는 단계,상기 개별 반도체층 상에 발광 적층 구조물을 형성하는 단계 및상기 피라미드 구조물을 절단하거나 또는 상기 피라미드 구조물과 상기 버퍼층과 접촉하는 면을 분리하여 상기 반도체층과 상기 버퍼층을 분리하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 20 항에 있어서,상기 버퍼층을 복수의 개별 발광 소자 영역으로 구분하여, 상기 개별적인 발광 소자 영역 상에 분리된 개별 반도체층을 형성하는 단계는,상기 복수의 개별 발광 소자 영역에 해당하는 상기 버퍼층을 결정 성장시켜 상기 복수의 돌기를 형성하는 단계;상기 복수의 돌기 상부를 결정 성장시켜 상기 개별 반도체층을 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 21 항에 있어서,상기 돌기는 상기 버퍼층으로부터 상기 반도체층으로 갈수록 단면적이 좁아지는 피라미드 구조물이고,상기 돌기를 절단하여 상기 개별 반도체층을 상기 버퍼층으로부터 분리하는 단계는 물리적인 충격을 가하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 20 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계는상기 절단된 돌기의 일부를 상기 반도체층에 잔류시키는 단계를 포함하는 발광 소자의 제조 방법.
- 제 23 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계 이후에,상기 발광 적층 구조물의 제 1면에 제 1전극을 형성하고, 상기 돌기의 일부가 잔류하는 상기 반도체층의 제2 면에 제 2전극을 형성하는 단계를 더 포함하는 발광 소자의 제조 방법.
- 제 23 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계 이전에,상기 발광 적층 구조물의 제 1면에 제 1전극을 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층을 복수의 발광 소자 영역으로 구분하여, 상기 각각의 발광 소자 영역에 복수의 피라미드 구조물을 각각 형성하는 단계,상기 피라미드 구조물 상부로부터, 상기 피라미드 구조물을 성장시켜 상기 각각의 발광 소자 영역을 구분하는 벽개면을 갖는 반도체층을 형성하되, 상기 반도체층과 상기 버퍼층은 상기 피라미드 구조물에 의해 연결되어, 상기 반도체층과 상기 버퍼층은 이격되어 있는 단계상기 반도체층상에 발광 적층 구조물을 형성하여 개별적인 예비 발광 소자를 형성하는 단계상기 피라미드 구조물을 절단하여 상기 반도체층과 상기 버퍼층을 박리하는 단계;상기 벽개면을 중심으로 상기 개별적인 예비 발광 소자를 분리하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 26 항에 있어서,상기 피라미드 구조물을 절단하여 상기 반도체층 및 상기 버퍼층을 박리하는 단계는 상기 피라미드 구조물을 절단하여, 상기 반도체층의 일면에 상기 피라미드 구조물의 일부를 잔류시키는 단계를 포함하는 발광 소자의 제조 방법.
- 제 26 항에 있어서,상기 피라미드 구조물을 절단하여 상기 반도체층과 상기 버퍼층을 박리하는 단계와 상기 벽개면을 중심으로 상기 개별적인 예비 발광 소자를 분리하는 단계는 동시에 수행되는 발광 소자의 제조 방법.
- 제 26 항에 있어서,상기 피라미드 구조물의 간격을 조절하여 상기 벽개면의 깊이를 조절하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 26 항에 있어서,상기 복수의 발광 소자 영역 사이의 간격은 상기 발광 적층 구조물의 높이의 0.4배~0.6 배보다 작은 발광 소자의 제조 방법.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층을 복수의 발광 소자 영역으로 구분하여, 상기 각각의 발광 소자 영역에 복수의 피라미드 구조물을 각각 형성하는 단계,상기 피라미드 구조물 상부로부터, 상기 피라미드 구조물을 성장시켜 상기 각각의 발광 소자 영역에 해당하며 서로 이격되어 있는 반도체층을 형성하되, 상기 반도체층과 상기 버퍼층은 상기 피라미드 구조물에 의해 연결되어, 상기 반도체층과 상기 버퍼층은 이격되어 있는 단계,상기 각각의 반도체층 상에 발광 적층 구조물을 형성하여 개별적인 발광 소자를 형성하는 단계,상기 피라미드 구조물을 절단하여 각각의 발광 소자를 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 31 항에 있어서,상기 복수의 발광 소자 영역 사이의 간격은 상기 발광 적층 구조물의 높이의 0.4배~0.6 배보다 큰 발광 소자의 제조 방법.
- 기판 상에 형성된 버퍼층,상기 버퍼층 상에 형성된 복수의 피라미드 구조물,상기 버퍼층과 이격되고 상기 복수의 피라미드 구조물에 의해 상기 버퍼층과 연결되어 상기 버퍼층 상에 형성된 반도체층을 포함하는 반도체 기판 템플릿.
- 기판 상에 형성되고 복수의 예비 발광 영역으로 구분되는 버퍼층,상기 복수의 예비 발광 영역의 개별 예비 발광 영역으로부터 상부로 돌출된 복수의 돌기,상기 돌기 상에 형성되고 상기 버퍼층과 이격되며 상기 개별 예비 발광 영역 상에 형성된 개별 반도체층을 포함하는 반도체 기판 템플릿.
- 제 34 항에 있어서,상기 돌기는 상기 버퍼층으로부터 상부로 갈수록 단면적이 감소하는 피라미드 구조물을 포함하는 반도체 기판 템플릿.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층을 복수의 발광 소자 영역으로 구분하여, 상기 각각의 발광 소자 영역에 복수의 피라미드 구조물을 각각 형성하는 단계,상기 피라미드 구조물 상부로부터, 상기 피라미드 구조물을 성장시켜 상기 각각의 발광 소자 영역에 해당하는 각각의 반도체층을 형성하되, 상기 반도체층과 상기 버퍼층은 상기 피라미드 구조물에 의해 연결되어, 상기 반도체층과 상기 버퍼층은 이격되어 있는 단계,상기 각각의 반도체층 상에 발광 적층 구조물을 형성하되, 상기 각각의 발광 소자 영역 사이의 간격에 대한 상기 발광 적층 구조물의 높이의 비를 조절하여 개별적인 발광 소자를 형성하는 단계,상기 피라미드 구조물을 절단하여 각각의 발광 소자를 형성하는 단계를 포함하는 발광 소자의 제조 방법.
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EP11763054.1A EP2555256A4 (en) | 2010-03-31 | 2011-03-31 | SUBSTRATE FOR SEMICONDUCTOR MODEL, LIGHT EMITTING ELEMENT USING SUBSTRATE FOR SEMICONDUCTOR MODEL, AND PROCESS FOR PRODUCING SAME |
CN201180026689XA CN103038901A (zh) | 2010-03-31 | 2011-03-31 | 半导体模板衬底、使用半导体模板衬底的发光元件及其制造方法 |
US13/638,165 US8716042B2 (en) | 2010-03-31 | 2011-03-31 | Semiconductor template substrate, light-emitting device using a semiconductor template substrate, and manufacturing method therefor |
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KR1020100059632A KR101134130B1 (ko) | 2010-06-23 | 2010-06-23 | 질화물 반도체 발광 소자 제조 방법 |
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JP2014026999A (ja) * | 2012-07-24 | 2014-02-06 | Sophia School Corp | 半導体装置、テンプレート基板、半導体装置の製造方法 |
CN104638068B (zh) * | 2013-11-07 | 2018-08-24 | 上海蓝光科技有限公司 | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 |
JP2015201488A (ja) * | 2014-04-04 | 2015-11-12 | 旭化成イーマテリアルズ株式会社 | 積層体、及びこれを用いた発光素子の製造方法 |
JP6670683B2 (ja) * | 2016-06-07 | 2020-03-25 | 株式会社Screenラミナテック | キャリア基板と樹脂層からなるワークの分離方法および分離装置 |
US10484428B2 (en) * | 2016-06-09 | 2019-11-19 | LGS Innovations LLC | Methods and systems for securing VPN cloud servers |
CN106098875B (zh) * | 2016-08-16 | 2019-02-05 | 西安交通大学 | 一种无荧光粉的白光金字塔阵列氮化镓基半导体发光二极管及其制备方法 |
CN106169524B (zh) * | 2016-08-16 | 2019-02-05 | 西安交通大学 | 一种微纳金字塔氮化镓基发光二极管阵列及其制备方法 |
CN106206875B (zh) * | 2016-08-16 | 2018-08-10 | 西安交通大学 | 一种柔性金字塔阵列GaN基半导体发光二级管及其制作方法 |
CN108470804A (zh) * | 2018-03-27 | 2018-08-31 | 华灿光电(浙江)有限公司 | 一种发光二极管芯片的制作方法、衬底及发光二极管芯片 |
CN108878598B (zh) * | 2018-05-31 | 2020-03-27 | 华灿光电(浙江)有限公司 | 一种垂直结构发光二极管芯片的制作方法 |
CN109148653A (zh) * | 2018-08-30 | 2019-01-04 | 湘能华磊光电股份有限公司 | 6英寸图形化蓝宝石衬底及制备方法和led外延片 |
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CN110957407B (zh) * | 2019-12-13 | 2021-04-09 | 深圳第三代半导体研究院 | 衬底、led及其制造方法 |
FR3118305B1 (fr) * | 2020-12-22 | 2023-06-09 | Commissariat Energie Atomique | Procédé de réalisation d’une couche de nitrure |
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JP3571641B2 (ja) * | 1999-11-15 | 2004-09-29 | 松下電器産業株式会社 | 窒化物半導体素子 |
TW518767B (en) * | 2000-03-31 | 2003-01-21 | Toyoda Gosei Kk | Production method of III nitride compound semiconductor and III nitride compound semiconductor element |
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JP2004158546A (ja) * | 2002-11-05 | 2004-06-03 | Matsushita Electric Works Ltd | 半導体発光素子 |
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WO2010020077A1 (en) * | 2008-08-22 | 2010-02-25 | Lattice Power (Jiangxi) Corporation | Method for fabricating ingaain light-emitting device on a combined substrate |
JP5180050B2 (ja) * | 2008-12-17 | 2013-04-10 | スタンレー電気株式会社 | 半導体素子の製造方法 |
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US8716042B2 (en) | 2014-05-06 |
US20130020594A1 (en) | 2013-01-24 |
JP2013524502A (ja) | 2013-06-17 |
WO2011122882A3 (ko) | 2012-01-26 |
EP2555256A4 (en) | 2015-09-16 |
EP2555256A2 (en) | 2013-02-06 |
WO2011122882A2 (ko) | 2011-10-06 |
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