WO2011122882A2 - 반도체 템플릿 기판, 반도체 템플릿 기판을 이용하는 발광 소자 및 이의 제조 방법 - Google Patents
반도체 템플릿 기판, 반도체 템플릿 기판을 이용하는 발광 소자 및 이의 제조 방법 Download PDFInfo
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- light emitting
- semiconductor layer
- buffer layer
- emitting device
- pyramid structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 239000000758 substrate Substances 0.000 title claims description 75
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 230000007423 decrease Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 45
- 238000000926 separation method Methods 0.000 claims description 33
- 239000013078 crystal Substances 0.000 claims description 26
- 238000005520 cutting process Methods 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 238000005286 illumination Methods 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 229910052594 sapphire Inorganic materials 0.000 description 8
- 239000010980 sapphire Substances 0.000 description 8
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 238000005253 cladding Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 208000012868 Overgrowth Diseases 0.000 description 1
- -1 Si 3 N 4 Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012153 distilled water Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02642—Mask materials other than SiO2 or SiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
- H01L21/0265—Pendeoepitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
Definitions
- the present invention relates to a semiconductor template substrate, a light emitting device using the semiconductor template substrate, and a method of manufacturing the same. More specifically, a semiconductor template substrate having a reduced crystal defect and easy separation, a light emitting device using the semiconductor template substrate, and a method of manufacturing the same. It is about.
- Conventional semiconductor light emitting devices are formed as horizontal devices or vertical devices using an insulating substrate such as sapphire.
- a conventional horizontal semiconductor light emitting device is shown in FIG. 6A and a conventional vertical semiconductor light emitting device is shown in FIG. 6B.
- the horizontal semiconductor light emitting device includes a buffer layer 2, an n-type nitride semiconductor layer 3, an active layer 4, and a p-type nitride semiconductor layer 5 sequentially formed on the sapphire substrate 1.
- the p-type electrode 6 is formed on the upper surface of the p-type nitride semiconductor layer 5, and the n-type electrode 7 removes a portion of the p-type nitride semiconductor layer and the active layer by etching or the like to expose n. It is formed on the type nitride semiconductor layer 3.
- the horizontal light emitting device as shown in FIG.
- the light emitting area is relatively small and the surface leakage current is also increased to reduce the light emitting performance of the device, and the area through which the current passes is also relatively small to increase the resistance, thereby operating voltage of the device.
- forming a p-type nitride semiconductor layer on the substrate is the same as the horizontal type, and after separating the insulating substrate from the light emitting device before forming the n-type electrode 7, the n-type semiconductor
- the n-type electrode 7 is formed on the lower surface of the layer.
- a laser lift-off method is generally used. When the laser beam, which is a strong energy source, is irradiated on the back side of the transparent sapphire substrate, the laser beam absorption is strongly generated at the interface between the buffer layer and the sapphire substrate, and thus, a temperature of 900 ° C.
- One object of the present invention is to solve the above disadvantages, one aspect of the present invention provides a semiconductor template substrate that does not damage the semiconductor substrate by the separation process.
- Another aspect of the invention provides an excellent semiconductor light emitting device.
- Another aspect of the present invention provides a method of manufacturing an excellent semiconductor light emitting device.
- the present invention uses a separation layer in which the light emitting device is easily separated from the substrate in the step of forming the light emitting device as a means for solving the above problems.
- the light emitting device according to the embodiment of the present invention by the separation layer includes a reverse pyramid structure.
- the light emitting device includes a semiconductor layer, a light emitting stack structure, and an inverted pyramid structure.
- the light emitting stacked structure is formed on the first surface of the semiconductor layer
- the reverse pyramid structure is formed on the second surface of the semiconductor layer, which is opposite to the first surface, and extends in a direction perpendicular to the second surface.
- the cross sectional area decreases.
- One aspect of the present invention provides a method of manufacturing a light emitting device.
- a buffer layer is formed on the substrate.
- a plurality of pyramid structures protruding from the buffer layer are formed.
- a semiconductor layer spaced apart from the buffer layer is formed through crystal growth from an upper portion of the pyramid structure.
- the pyramid structure connects the buffer layer and the semiconductor layer.
- a light emitting stacked structure is formed on the semiconductor layer. The semiconductor layer and the buffer layer are separated by cutting the pyramid structure or separating a surface contacting the pyramid structure and the buffer layer.
- One aspect of the present invention provides a method of manufacturing a light emitting device.
- a buffer layer is formed on the substrate.
- the buffer layer is divided into a plurality of individual light emitting device regions to form separate semiconductor layers on the individual light emitting device regions.
- Individual semiconductor layers formed in the individual light emitting device regions and buffer layers corresponding to the individual light emitting device regions are connected by a plurality of protrusions.
- a light emitting stacked structure is formed on the individual semiconductor layer.
- the semiconductor layer and the buffer layer are separated by cutting the pyramid structure or separating a surface contacting the pyramid structure and the buffer layer.
- One aspect of the present invention provides a method of manufacturing a light emitting device.
- a buffer layer is formed on the substrate.
- the buffer layer is divided into a plurality of light emitting device regions, and a plurality of pyramid structures are formed in each of the light emitting device regions. From the upper part of the pyramid structure, the pyramid structure is grown to form a semiconductor layer having a cleaved surface separating the respective light emitting device regions.
- the semiconductor layer and the buffer layer are connected by the pyramid structure, and the semiconductor layer and the buffer layer are spaced apart from each other.
- a light emitting stack structure is formed on the semiconductor layer to form individual preliminary light emitting devices.
- the semiconductor layer and the buffer layer are separated by cutting the pyramid structure.
- the individual preliminary light emitting devices are separated around the cleaved surface.
- One aspect of the present invention provides a method of manufacturing a light emitting device.
- a buffer layer is formed on the substrate.
- the buffer layer is divided into a plurality of light emitting device regions, and a plurality of pyramid structures are formed in each of the light emitting device regions. From the upper portion of the pyramid structure, the pyramid structure is grown to form semiconductor layers corresponding to the respective light emitting device regions and spaced apart from each other.
- the semiconductor layer and the buffer layer are connected by the pyramid structure, and the semiconductor layer and the buffer layer are spaced apart from each other.
- a light emitting stack structure is formed on each of the semiconductor layers to form individual light emitting devices.
- the pyramid structures are cut to form respective light emitting devices.
- the semiconductor substrate template includes a buffer layer formed on the substrate, a plurality of pyramid structures formed on the buffer layer, a semiconductor layer spaced from the buffer layer and connected to the buffer layer by the plurality of pyramid structures and formed on the buffer layer.
- the semiconductor substrate template may include a buffer layer formed on the substrate and divided into a plurality of preliminary light emitting regions, a plurality of protrusions protruding upward from individual preliminary light emitting regions of the plurality of preliminary light emitting regions, and formed on the protrusions and spaced apart from the buffer layer. And an individual semiconductor layer formed on the respective preliminary light emitting regions.
- the semiconductor substrate can be easily separated from the insulated substrate, a light emitting device excellent in performance can be manufactured without damaging the semiconductor substrate.
- the uneven pattern may be formed on the lower surface of the semiconductor substrate, thereby simplifying the manufacturing process.
- the process of separating the individual light emitting devices from one semiconductor substrate may not damage the semiconductor substrate.
- FIG. 1A and 1B are views illustrating a light emitting device manufacturing method according to an embodiment of the present invention.
- FIGS. 2A and 2B are views for explaining a method of manufacturing a light emitting device according to another embodiment of the present invention.
- 3A to 3G are views for explaining a method of manufacturing a light emitting device according to another embodiment of the present invention.
- FIG. 4 is a view schematically showing an electrode forming jig
- 5A to 5C are diagrams illustrating an intermediate product of a light emitting device manufactured according to one embodiment
- 6A and 6B schematically illustrate a conventional horizontal light emitting device and a vertical light emitting device.
- this embodiment is for growing n-type GaN crystals using a sapphire substrate.
- the materials used for the substrate, the buffer layer, the semiconductor layer, and the light emitting stacked structure are not limited by this embodiment.
- step S110 the buffer layer 20 is formed on the insulating substrate 10, and the mask layer 30 having the plurality of exposure patterns 39 is formed on the buffer layer 20.
- the exposure pattern 39 is illustrated in a circle in FIG. 1A, the exposure pattern 39 may be a polygon such as a rectangle, a triangle, a hexagon, and the like, and the arrangement thereof may be various.
- the substrate 10 may be selected from the group consisting of various materials, such as a sapphire substrate or a substrate including silicon, GaAs, InP, and SiC.
- the buffer layer 20 may be formed by growing a GaN crystal.
- n-type GaN crystals are formed by growing to a thickness of 2 to 5 ⁇ using an HVPE crystal growth apparatus.
- the buffer layer may comprise an Al x Ga (1-x) N (0 ⁇ x ⁇ 1) layer or Al 2 O 3 , AlN or ZnO.
- a metal such as SiO 2 , Si 3 N 4 , Cr, Au, Ti, Ni, or the like may be used.
- SiO 2 or Si 3 N 4 on the buffer layer 20 to a thickness of about 500 ⁇ 5000 ⁇ by PECVD, an exposure pattern 39 is formed by a photolithography process to form part of the buffer layer 20. To be exposed.
- the mask layer 30 may be formed using a lift-off method.
- a photoresist is applied on the buffer layer 20 and an exposure process is performed. Then, a developing process is performed to form a photoresist pattern. Thereby, the buffer layer 20 of a desired pattern shape is exposed, and the other part is covered by the photoresist pattern.
- a preliminary mask layer (not shown) is formed on the photoresist pattern formed on the buffer layer 20. The photoresist pattern and the preliminary mask layer formed on the photoresist pattern are removed. Accordingly, a mask layer 30 having a desired pattern may be formed on the buffer layer 20.
- the diameter of the exposure pattern 39 is approximately 0.5-5 ⁇ m, and the interval between adjacent exposure patterns 39 is 0.5-10 ⁇ m.
- step S120 crystals are grown from the buffer layer 20 exposed by the exposure pattern 39.
- a pyramid structure 40 is formed from the inside of the exposure pattern 39 of the mask layer 30.
- the pyramid structure 40 means a shape in which the cross-sectional area becomes narrower toward the top.
- the pyramid structure 40 may be a cone or hexagonal pyramid (polygonal) structure.
- a hexagonal pyramid structure may be formed by growing to have a horn shape from the buffer layer 20 exposed by the exposure pattern 39.
- the diameter of the bottom surface of the pyramid structure 40 may be approximately the same or slightly larger than the exposure pattern 39, when the diameter of the exposure pattern 39 is 0.5 ⁇ 5 ⁇ m, the height of the pyramid structure 40 is the exposure pattern 39 It may be formed about 0.5 ⁇ 7.5 ⁇ m, about 1-1.5 times the diameter of the).
- the underside of the pyramid structure 40 is overgrowth and wider than the exposure pattern 39.
- the pyramid structure 40 protrudes above the mask layer 30.
- the pyramid structure 40 may be formed as a hexagonal pyramid structure.
- an example of crystal growth conditions of HVPE is as follows. Ga metal is used as the raw material of Ga and ammonia (NH 3) is used as the raw material of N, and Te or Si is synthesized in the Ga solution to form n-type GaN. A substrate on which the exposed pattern 39 is formed is mounted in a reaction tube, and GaN crystals are grown at 1000 to 1100 ° C. to form a hexagonal pyramid structure of n-type GaN.
- NH 3 ammonia
- Te or Si is synthesized in the Ga solution to form n-type GaN.
- a substrate on which the exposed pattern 39 is formed is mounted in a reaction tube, and GaN crystals are grown at 1000 to 1100 ° C. to form a hexagonal pyramid structure of n-type GaN.
- the composition of the pyramid structure 40 may be Al x Ga (1-x) N (0 ⁇ x ⁇ 1).
- the composition of the buffer layer 30 and the composition of the pyramid structure 40 may be formed in the same manner as the source used when growing the pyramid structure 40, or may be formed differently.
- the amount of Al put in the Ga solution used to form the buffer layer 20 may be from 0 g to 1 g of Ga. By adjusting several hundred mg, it is possible to obtain from GaN having composition x of 0 to AlN having composition x of 1.
- the amount of Al to be added to the Ga solution used to form the pyramid structure 40 may be adjusted from 0 g to several hundred mg to 1 g of Ga to obtain from GaN having composition x of 0 to AlN having composition x of 1.
- the composition of the buffer layer 20 and the composition of the pyramid structure 40 are adjusted by the change of the source. That is, the composition of the buffer layer 20 and the composition of the pyramid structure 40 may be formed in the same manner, or may be formed differently.
- 5A is a SEM photograph of the pyramid structure 40 formed in accordance with an embodiment of the present invention.
- the semiconductor layer 50 is formed.
- the semiconductor layer 50 may be formed using an HVPE crystal growth apparatus.
- the growth layer grown on the side of the pyramid structure 40 may be combined to form the semiconductor layer 50. That is, in the mask layer 30, it is difficult for crystals to grow from the buffer layer 20, and GaN crystals begin to grow on the inclined side surface of the exposed pyramid structure 40, and the crystal layers grown in the adjacent semiconductor layer 50 are formed.
- the semiconductor layers 50 are formed by adhering to each other.
- the height of the semiconductor layer 50 is preferably such that the pyramid structure 40 can support the thickness of the semiconductor layer 50.
- the height of the semiconductor layer 50 may be 1 ⁇ m to 100 ⁇ m.
- the composition of the pyramid structure 40 may be GaN or AlxGa (1-x) N (0 ⁇ x ⁇ 1).
- a layer having a different composition may be obtained.
- Ga source and ammonia are reacted to form the pyramid structure 40
- Ga source, Al source and ammonia are reacted to form the semiconductor layer 50.
- GaN is formed in the pyramid structure 40
- AlGaN is formed in the semiconductor layer 50.
- by adjusting the amount of Al it is possible to adjust the Al composition of the AlGaN layer.
- the composition of the pyramid structure 40 is only one example, and it is also possible to form a pyramid structure 40 having a different composition by changing a source used by the user to form the pyramid structure 40.
- the semiconductor layer 50 may be a flattening layer having a flat upper surface.
- crystals begin to grow from the approximately half of the height of the pyramid structure 40 to the inclined side of the pyramid structure 40 so that the crystals grown in the adjacent pyramid structure 40 adhere to each other and then move forward.
- the semiconductor layer 50 may be formed by maintaining growth until the region becomes flat.
- the lower surface of the semiconductor layer 50 may be formed to descend to a height of 1/3 of the pyramid structure 40.
- the idea of the present invention is not limited by this height.
- FIG. 5B is a side SEM image of the pyramid structure 40 and the semiconductor layer 50 formed according to the embodiment of the present invention, and it is possible to check the empty space next to the pyramid structure 40.
- the light emitting stacked structure 60 is formed on the semiconductor layer 50.
- an n-type AlGaN cladding layer, an AlGaN active layer, a p-type AlGaN cladding layer, a p-type GaN cap layer, or the like may be formed to form a light emitting stacked structure.
- the HVPE crystal growth method may be used to form the light emitting stacked structure 60.
- a cladding layer comprising n-type AlxGa (1-x) N (0 ⁇ x ⁇ 1), an active layer comprising AlxGa (1-x) N (0 ⁇ x ⁇ 1), p-type AlxGa (1) -x)
- a cladding layer and a p-type GaN cap layer including N (0 ⁇ x ⁇ 1) may be sequentially formed.
- the material used for each layer of the light emitting stack structure 60 and the stacking order may be appropriately changed depending on the desired light emitting wavelength range, light output, or type of light emitting device.
- the buffer layer 20, the semiconductor layer 50, and the light emitting stack 60 may all be formed by the HVPE method, the buffer layer 20, the semiconductor layer 50, and the light emitting stack 60 may be sequentially formed. have.
- the buffer layer 20, the semiconductor layer 50, and the light emitting stack 60 may be formed by an in-situ process.
- step S150 the substrate 10, the buffer layer 20, and the mask layer 30 are separated from the light emitting stack structure 60. Irregular irregularities may be formed on the separated surface. Separation of the substrate 10 may be performed by application of ultrasonic waves, physical vibration, or impact. For example, when the substrate 10 on which the light emitting stacked structure 60 is formed is placed in a solution such as acetone or methanol or distilled water and subjected to ultrasonic waves, the semiconductor layer 50 and the buffer layer 20 are connected only to the pyramid structure 40. In the separation layer 90, separation occurs while the pyramid structure 40 is cut. Or, the bottom portion of the pyramid is separated from the substrate and separation occurs. Alternatively, the pyramid structure 40 may be cut by applying a simple impact.
- the reverse pyramid structure means a structure in which the cross-sectional area increases as the distance from the lower surface of the semiconductor layer 50 increases. That is, the reverse pyramid structure formed in the semiconductor layer 50 is a structure that facilitates separation of the light emitting device and the substrate 10 for forming the light emitting device.
- the laser beam is irradiated to the pyramid structure 40 of the separation layer 90 which is relatively weak in binding force as compared with the conventional laser lift-off method.
- the substrate 10 can be separated without damaging the light emitting laminated structure 60 at the time of separating the substrate.
- the strain may be applied to the substrate 10 and / or the buffer layer 20 to generate stress in the pyramid structure 40, thereby cutting the pyramid structure 40.
- the separation layer 90 Due to the presence of the separation layer 90, the light emitting device is easily separated from the substrate 10, so that a complicated process is omitted, and the semiconductor layer 50 of the light emitting device is damaged when the light emitting device is separated from the substrate 10. It is possible to produce a light emitting device having a good quality without generating the.
- FIG. 5C is an SEM image of the lower surface of the separated light emitting stacked structure, and the uneven pattern formed while the pyramid structure 40 is cut can be confirmed.
- the p-type electrode 71 is formed on the light emitting stack 60, and the n-type electrode 72 is formed on the bottom surface 51 of the separated semiconductor layer 50 to emit light.
- the n-type electrode 72 may be formed on the reverse pyramid structure, or may be formed on the bottom surface 51 of the semiconductor layer 50.
- each of the electrodes 71 and 72 may be completed after forming a separate intermediate layer according to the design.
- an inverted pyramid structure may be formed on the lower surface 51 of the semiconductor layer 50 by cutting the pyramid structure 40.
- the projection pattern may be formed on the lower surface 51 of the semiconductor layer 50 without a separate pattern process.
- the p-type electrode 71 may be formed immediately before the separation step S150 after the formation (S140) of the light emitting stack structure 60.
- the substrate 10 formed up to the semiconductor layer 50 which is a structure before the separation process with the substrate 10, may be used as the semiconductor template substrate.
- the semiconductor template substrate may be used as the semiconductor template substrate.
- the second embodiment is similar to the first embodiment, but relates to a method of manufacturing a light emitting device by dividing the regions of the separation layer to form regions having different bonding forces. Therefore, when the mask layer 30 is formed, the diameter and the interval of the exposure pattern are differently formed by dividing the first region 31 having a relatively high bonding force and the region 32 having a small bonding force as shown in FIG. 2A. That is, the first region 31 having a relatively large bonding force has a smaller diameter and spacing of the exposure pattern than the second region 32 having a small bonding force.
- the diameter and the interval of the exposure pattern of the first region 31 may be 1 ⁇ m
- the diameter and the interval of the exposure pattern of the second region 32 may be about 3 ⁇ m.
- the pyramid structure 40 formed in the first region 31 has a higher inclination than the pyramid structure 40 of the second region 32 and has a hexagonal pyramid. The more sticky they are, the less empty space they have. Therefore, the separation layer 90 formed between the mask layer 30 and the semiconductor layer 50 is divided into a first separation portion 91 having a relatively small bonding force and a second separation portion 92 having a relatively large bonding force. You lose.
- the second embodiment is useful when the p-type electrode is first formed before the separation layer 90 is separated.
- FIGS. 3A to 3D a light emitting device manufacturing method according to still another embodiment of the present invention will be described with reference to FIGS. 3A to 3D.
- the light emitting device manufacturing method described above was mainly focused on a method of manufacturing a single light emitting device, but the light emitting device manufacturing method of the present embodiment not only forms a plurality of light emitting devices on a single substrate and easily separates the light emitting device from the substrate.
- Each light emitting device also relates to a light emitting device manufacturing method which can be easily separated from each other. Detailed description of the manufacturing method similar to that of FIG. 1 is omitted.
- each light emitting chip region A is illustrated as a quadrangle for convenience of description, but the light emitting chip region A is not limited to a quadrangle and may be formed according to various designs such as a circle or a hexagon.
- Each light emitting chip region A is spaced apart by a predetermined chip spacing d.
- a plurality of exposure patterns 39 are formed in each light emitting chip region of the mask layer 30.
- a plurality of pyramid structures 40 may be formed by selectively growing crystals from the buffer layer 20 using the HVPE method as shown in FIG. 3B.
- the semiconductor layer 50 is formed.
- a cleaved surface 55 may be formed to divide the semiconductor layer 50 into each individual light emitting stack structure. The depth of the cleaved surface 55 may be adjusted to a depth desired by the user through chip spacing d, process conditions, and the like.
- the depth of the cleaved surface 55 is adjusted by adjusting the ratio between the height h and the chip spacing d. May be For example, by adjusting the chip spacing d to be smaller than 0.4 to 0.6 times the height h, only a part of the semiconductor chip 50 is connected as shown in FIG. 3C, and the light emitting stacks 60 are separated from each other.
- the structure can be formed.
- the light emitting stacked structure 60 is formed on the semiconductor layer 50 as shown in FIG. 3C.
- the light emitting stack structure 60 is formed by dividing each light emitting chip region by the cleaved surface 51 of the semiconductor layer 50.
- each light emitting device is separated in the vertical and horizontal directions.
- the separation process may be performed in various orders.
- ultrasonic waves, vibrations, shocks, and the like may be applied to the separation layer 90 to first separate the substrate in the vertical direction, and then to separate the light emitting devices in the horizontal direction.
- Separation in the horizontal direction may be performed by various methods such as physical impact, pressure, etc.
- each of the light emitting devices may be separated by attaching a film over the devices and pressing them with a roller.
- the vertical separation and the horizontal separation may be performed simultaneously by applying an appropriate vibration or pressure.
- a p-type electrode (not shown) is formed on the light emitting stack 60, and an n-type electrode (not shown) is formed on the bottom surface of the separated semiconductor layer 50 to complete the light emitting device.
- Each electrode may be completed after forming a separate intermediate layer according to the design.
- the p-type electrode (not shown) may be formed at a suitable time before or after the vertical separation step and after the horizontal separation step.
- the n-type electrode (not shown) may be formed before or after the horizontal separation step.
- the electrode forming jig 200 shown in FIG. 4 may be used.
- the jig 200 includes a chip mounting portion 210 of a suitable size for accommodating a plurality of light emitting chips, respectively, in a matrix form. Chips are sorted by a chip selector and placed in each chip mounting part 210 of the jig to form electrodes.
- the semiconductor layer 50 is formed.
- the semiconductor layers 50 may be formed separately from each other in units of individual light emitting devices.
- the chip spacing d may be adjusted to be greater than 0.4 to 0.6 times the height h to form the semiconductor layers 50 and the individual light emitting device structures 60 that are separately separated. That is, the individual light emitting device structures 60 may be obtained by forming the light emitting device structures 60 on the respective semiconductor layers 50 as shown in FIG. 3F and separating them as shown in FIG. 3G.
- a p-type electrode (not shown) is formed on the light emitting stack 60
- an n-type electrode is formed on the bottom surface of the separated semiconductor layer 50 to complete the light emitting device.
- the light emitting layer structure is formed after the semiconductor layer is formed on the pyramid structure of the semiconductor layer, whereby the crystal defect density is reduced and the substrate dependency can be minimized.
- the present invention is useful because it is possible not only to use expensive conductive metal substrates in the manufacture of the vertical light emitting device, but also to easily separate the substrates without using the laser lift-off process, which is essential when using an insulating substrate. . Therefore, the production process of the vertical light emitting device can be simplified and the production cost can be greatly reduced.
- the planar nitride semiconductor layer is formed by forming the light emitting chip region hexagonal pyramid structure by adjusting the chip spacing of the light emitting chip region and the height of the stacked light emitting structure to form a flattened nitride semiconductor layer.
- the separation process can be facilitated to simplify the production process.
- the bottom surface of the planarized nitride semiconductor layer is formed with a concave-convex pattern in which a hexagonal pyramid structure is partially cut off, thereby providing a light emitting device capable of maximizing light emission efficiency without further processing.
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Abstract
Description
Claims (36)
- 반도체층상기 반도체층 제1 면 상에 형성된 발광 적층 구조물 및상기 제1 면의 반대면인 상기 반도체층의 제2 면에 형성되고, 상기 제2 면에서 수직인 방향으로 연장될수록 단면적이 감소하는 복수의 역피라미드 구조물을 포함하는 발광 소자.
- 제 1 항에 있어서,상기 역피라미드 구조물의 단면은 원형 또는 다각형을 포함하는 발광 소자.
- 제 2 항에 있어서,상기 역피라미드 구조물의 직경은 0.5-5 μm이고, 역피라미드 구조물의 간격은 0.5~10 μm인 발광 소자.
- 제 3 항에 있어서,상기 반도체층은 질화물을 포함하고, 상기 역피라미드 구조물의 횡단면은 상기 제2 면에 평행한 발광소자.
- 제 3 항에 있어서,상기 역피라미드 구조물과 상기 반도체층은 질화물을 포함하는 발광 소자
- 제 5 항에 있어서,상기 반도체층은 기판으로부터 분리된 반도체층이고, 상기 역피라미드 구조물은 상기 기판과 상기 반도체층의 분리를 용이하도록 하는 발광 소자.
- 제 1 항에 있어서,상기 역피라미드 구조물은 제1 경사를 갖는 제1 역피라미드 구조물 및 상기 제1 경사와 상이한 경사를 갖는 제2 역피라미드 구조물을 포함하는 발광 소자.
- 제 2 항에 있어서,상기 제1 역피라미드 구조물의 단면적은 상기 제2 역피라미드 구조물의 단면적보다 큰 발광 소자.
- 반도체층,상기 반도체층 제1 면 상에 형성된 발광 적층 구조물 및상기 제1 면의 반대면인 상기 반도체층의 제2 면에 형성된 높이가 상이한 복수의 요철을 포함하는 발광 소자.
- 제 1 항 내지 제 9 항의 발광 소자를 포함하는 조명.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층 상에 돌출된 복수의 피라미드 구조물을 형성하는 단계;상기 피라미드 구조물의 상부로부터 결정 성장을 통해 상기 버퍼층과 이격된 반도체층을 형성하되, 상기 피라미드 구조물은 상기 버퍼층과 상기 반도체층을 연결하고 있는, 단계;상기 반도체층 상에 발광 적층 구조물을 형성하는 단계 및상기 피라미드 구조물을 절단하거나 또는 상기 피라미드 구조물과 상기 버퍼층과 접촉하는 면을 분리하여 상기 반도체층과 상기 버퍼층을 분리하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 11 항에 있어서,상기 버퍼층 상에 돌출된 복수의 피라미드 구조물을 형성하는 단계는상기 버퍼층의 일부를 결정 성장시켜 복수의 피라미드 구조물을 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 12 항에 있어서,상기 버퍼층의 일부를 결정 성장시키는 단계는상기 버퍼층 상에 노출 패턴을 갖는 마스크층을 형성시키는 단계;상기 노출 패턴에 의해 노출되는 상기 버퍼층의 일부를 결정 성장시키는 단계를 포함하는 발광 소자의 제조 방법.
- 제 12 항에 있어서,상기 반도체층 및 상기 발광 적층 구조물은 질화물을 포함하는 물질을 이용하여 형성되고, 상기 반도체층을 형성하는 단계 및 상기 발광 적층 구조물을 형성하는 단계는 순차적으로 수행되는 발광 소자의 제조 방법.
- 제 12 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계는상기 피라미드 구조물의 일부를 상기 반도체층에 잔류시키는 단계를 포함하는 발광 소자의 제조 방법.
- 제 15 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계 이후에,상기 발광 적층 구조물의 제 1면에 제 1전극을 형성하고, 상기 피라미드 구조물의 일부가 잔류하는 상기 반도체층의 제2 면에 제 2전극을 형성하는 단계를 더 포함하는 발광 소자의 제조 방법.
- 제 14 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계 이전에,상기 발광 적층 구조물의 제 1면에 제 1전극을 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 15 항에 있어서,상기 피라미드 구조물을 절단하여 상기 반도체층과 상기 버퍼층을 분리하는 단계는 물리적 충격을 이용하는 발광 소자의 제조 방법.
- 제 15 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계는 상기 기판에 스트레인을 가하는 단계를 포함하는 발광 소자의 제조 방법.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층을 복수의 개별 발광 소자 영역으로 구분하여, 상기 개별적인 발광 소자 영역 상에 분리된 개별 반도체층을 형성하되, 상기 개별 발광 소자 영역에 형성된 개별 반도체층과 상기 개별 발광 소자 영역에 대응하는 버퍼층은 복수의 돌기에 의해 연결되어 있는 단계,상기 개별 반도체층 상에 발광 적층 구조물을 형성하는 단계 및상기 피라미드 구조물을 절단하거나 또는 상기 피라미드 구조물과 상기 버퍼층과 접촉하는 면을 분리하여 상기 반도체층과 상기 버퍼층을 분리하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 20 항에 있어서,상기 버퍼층을 복수의 개별 발광 소자 영역으로 구분하여, 상기 개별적인 발광 소자 영역 상에 분리된 개별 반도체층을 형성하는 단계는,상기 복수의 개별 발광 소자 영역에 해당하는 상기 버퍼층을 결정 성장시켜 상기 복수의 돌기를 형성하는 단계;상기 복수의 돌기 상부를 결정 성장시켜 상기 개별 반도체층을 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 21 항에 있어서,상기 돌기는 상기 버퍼층으로부터 상기 반도체층으로 갈수록 단면적이 좁아지는 피라미드 구조물이고,상기 돌기를 절단하여 상기 개별 반도체층을 상기 버퍼층으로부터 분리하는 단계는 물리적인 충격을 가하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 20 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계는상기 절단된 돌기의 일부를 상기 반도체층에 잔류시키는 단계를 포함하는 발광 소자의 제조 방법.
- 제 23 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계 이후에,상기 발광 적층 구조물의 제 1면에 제 1전극을 형성하고, 상기 돌기의 일부가 잔류하는 상기 반도체층의 제2 면에 제 2전극을 형성하는 단계를 더 포함하는 발광 소자의 제조 방법.
- 제 23 항에 있어서,상기 반도체층과 상기 버퍼층을 분리하는 단계 이전에,상기 발광 적층 구조물의 제 1면에 제 1전극을 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층을 복수의 발광 소자 영역으로 구분하여, 상기 각각의 발광 소자 영역에 복수의 피라미드 구조물을 각각 형성하는 단계,상기 피라미드 구조물 상부로부터, 상기 피라미드 구조물을 성장시켜 상기 각각의 발광 소자 영역을 구분하는 벽개면을 갖는 반도체층을 형성하되, 상기 반도체층과 상기 버퍼층은 상기 피라미드 구조물에 의해 연결되어, 상기 반도체층과 상기 버퍼층은 이격되어 있는 단계상기 반도체층상에 발광 적층 구조물을 형성하여 개별적인 예비 발광 소자를 형성하는 단계상기 피라미드 구조물을 절단하여 상기 반도체층과 상기 버퍼층을 박리하는 단계;상기 벽개면을 중심으로 상기 개별적인 예비 발광 소자를 분리하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 26 항에 있어서,상기 피라미드 구조물을 절단하여 상기 반도체층 및 상기 버퍼층을 박리하는 단계는 상기 피라미드 구조물을 절단하여, 상기 반도체층의 일면에 상기 피라미드 구조물의 일부를 잔류시키는 단계를 포함하는 발광 소자의 제조 방법.
- 제 26 항에 있어서,상기 피라미드 구조물을 절단하여 상기 반도체층과 상기 버퍼층을 박리하는 단계와 상기 벽개면을 중심으로 상기 개별적인 예비 발광 소자를 분리하는 단계는 동시에 수행되는 발광 소자의 제조 방법.
- 제 26 항에 있어서,상기 피라미드 구조물의 간격을 조절하여 상기 벽개면의 깊이를 조절하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 26 항에 있어서,상기 복수의 발광 소자 영역 사이의 간격은 상기 발광 적층 구조물의 높이의 0.4배~0.6 배보다 작은 발광 소자의 제조 방법.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층을 복수의 발광 소자 영역으로 구분하여, 상기 각각의 발광 소자 영역에 복수의 피라미드 구조물을 각각 형성하는 단계,상기 피라미드 구조물 상부로부터, 상기 피라미드 구조물을 성장시켜 상기 각각의 발광 소자 영역에 해당하며 서로 이격되어 있는 반도체층을 형성하되, 상기 반도체층과 상기 버퍼층은 상기 피라미드 구조물에 의해 연결되어, 상기 반도체층과 상기 버퍼층은 이격되어 있는 단계,상기 각각의 반도체층 상에 발광 적층 구조물을 형성하여 개별적인 발광 소자를 형성하는 단계,상기 피라미드 구조물을 절단하여 각각의 발광 소자를 형성하는 단계를 포함하는 발광 소자의 제조 방법.
- 제 31 항에 있어서,상기 복수의 발광 소자 영역 사이의 간격은 상기 발광 적층 구조물의 높이의 0.4배~0.6 배보다 큰 발광 소자의 제조 방법.
- 기판 상에 형성된 버퍼층,상기 버퍼층 상에 형성된 복수의 피라미드 구조물,상기 버퍼층과 이격되고 상기 복수의 피라미드 구조물에 의해 상기 버퍼층과 연결되어 상기 버퍼층 상에 형성된 반도체층을 포함하는 반도체 기판 템플릿.
- 기판 상에 형성되고 복수의 예비 발광 영역으로 구분되는 버퍼층,상기 복수의 예비 발광 영역의 개별 예비 발광 영역으로부터 상부로 돌출된 복수의 돌기,상기 돌기 상에 형성되고 상기 버퍼층과 이격되며 상기 개별 예비 발광 영역 상에 형성된 개별 반도체층을 포함하는 반도체 기판 템플릿.
- 제 34 항에 있어서,상기 돌기는 상기 버퍼층으로부터 상부로 갈수록 단면적이 감소하는 피라미드 구조물을 포함하는 반도체 기판 템플릿.
- 기판 상에 버퍼층을 형성하는 단계,상기 버퍼층을 복수의 발광 소자 영역으로 구분하여, 상기 각각의 발광 소자 영역에 복수의 피라미드 구조물을 각각 형성하는 단계,상기 피라미드 구조물 상부로부터, 상기 피라미드 구조물을 성장시켜 상기 각각의 발광 소자 영역에 해당하는 각각의 반도체층을 형성하되, 상기 반도체층과 상기 버퍼층은 상기 피라미드 구조물에 의해 연결되어, 상기 반도체층과 상기 버퍼층은 이격되어 있는 단계,상기 각각의 반도체층 상에 발광 적층 구조물을 형성하되, 상기 각각의 발광 소자 영역 사이의 간격에 대한 상기 발광 적층 구조물의 높이의 비를 조절하여 개별적인 발광 소자를 형성하는 단계,상기 피라미드 구조물을 절단하여 각각의 발광 소자를 형성하는 단계를 포함하는 발광 소자의 제조 방법.
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EP11763054.1A EP2555256A4 (en) | 2010-03-31 | 2011-03-31 | SUBSTRATE FOR SEMICONDUCTOR MODEL, LIGHT EMITTING ELEMENT USING SUBSTRATE FOR SEMICONDUCTOR MODEL, AND PROCESS FOR PRODUCING SAME |
JP2013502484A JP5512877B2 (ja) | 2010-03-31 | 2011-03-31 | 半導体テンプレート基板、半導体テンプレート基板を用いる発光素子及びその製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104638068B (zh) * | 2013-11-07 | 2018-08-24 | 上海蓝光科技有限公司 | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 |
JP2015201488A (ja) * | 2014-04-04 | 2015-11-12 | 旭化成イーマテリアルズ株式会社 | 積層体、及びこれを用いた発光素子の製造方法 |
JP6670683B2 (ja) * | 2016-06-07 | 2020-03-25 | 株式会社Screenラミナテック | キャリア基板と樹脂層からなるワークの分離方法および分離装置 |
US10440058B2 (en) * | 2016-06-09 | 2019-10-08 | LGS Innovations LLC | Methods and systems for controlling traffic to VPN servers |
CN106206875B (zh) * | 2016-08-16 | 2018-08-10 | 西安交通大学 | 一种柔性金字塔阵列GaN基半导体发光二级管及其制作方法 |
CN106169524B (zh) * | 2016-08-16 | 2019-02-05 | 西安交通大学 | 一种微纳金字塔氮化镓基发光二极管阵列及其制备方法 |
CN106098875B (zh) * | 2016-08-16 | 2019-02-05 | 西安交通大学 | 一种无荧光粉的白光金字塔阵列氮化镓基半导体发光二极管及其制备方法 |
CN108470804A (zh) * | 2018-03-27 | 2018-08-31 | 华灿光电(浙江)有限公司 | 一种发光二极管芯片的制作方法、衬底及发光二极管芯片 |
CN108878598B (zh) * | 2018-05-31 | 2020-03-27 | 华灿光电(浙江)有限公司 | 一种垂直结构发光二极管芯片的制作方法 |
CN109148653A (zh) * | 2018-08-30 | 2019-01-04 | 湘能华磊光电股份有限公司 | 6英寸图形化蓝宝石衬底及制备方法和led外延片 |
CN109994562A (zh) * | 2019-04-17 | 2019-07-09 | 华南理工大学 | 超多晶面六角锥图形化GaAs衬底上纳米柱及制备方法 |
CN110957407B (zh) * | 2019-12-13 | 2021-04-09 | 深圳第三代半导体研究院 | 衬底、led及其制造方法 |
FR3118305B1 (fr) * | 2020-12-22 | 2023-06-09 | Commissariat Energie Atomique | Procédé de réalisation d’une couche de nitrure |
KR102391807B1 (ko) * | 2021-09-16 | 2022-04-29 | 이지그룹 주식회사 | 발광시트 및 이를 이용한 도로 표지판 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6940098B1 (en) * | 1999-03-17 | 2005-09-06 | Mitsubishi Cable Industries, Ltd. | Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method |
JP3571641B2 (ja) * | 1999-11-15 | 2004-09-29 | 松下電器産業株式会社 | 窒化物半導体素子 |
TW518767B (en) * | 2000-03-31 | 2003-01-21 | Toyoda Gosei Kk | Production method of III nitride compound semiconductor and III nitride compound semiconductor element |
JP3882539B2 (ja) * | 2000-07-18 | 2007-02-21 | ソニー株式会社 | 半導体発光素子およびその製造方法、並びに画像表示装置 |
JP4206629B2 (ja) | 2000-10-04 | 2009-01-14 | パナソニック株式会社 | 半導体装置の製造方法および半導体装置ならびに半導体基板の製造方法 |
US6562701B2 (en) * | 2001-03-23 | 2003-05-13 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing nitride semiconductor substrate |
EP1422748A1 (en) * | 2001-08-01 | 2004-05-26 | Nagoya Industrial Science Research Institute | Group iii nitride semiconductor film and its production method |
JP2004158546A (ja) * | 2002-11-05 | 2004-06-03 | Matsushita Electric Works Ltd | 半導体発光素子 |
JP2004273661A (ja) | 2003-03-07 | 2004-09-30 | Sumitomo Chem Co Ltd | 窒化ガリウム単結晶基板の製造方法 |
JP2005142415A (ja) * | 2003-11-07 | 2005-06-02 | Sony Corp | GaN系III−V族化合物半導体層の選択成長方法、半導体発光素子の製造方法および画像表示装置の製造方法 |
KR100568830B1 (ko) * | 2004-08-26 | 2006-04-10 | 에피밸리 주식회사 | Ⅲ-질화물 반도체 발광소자 |
WO2010020077A1 (en) * | 2008-08-22 | 2010-02-25 | Lattice Power (Jiangxi) Corporation | Method for fabricating ingaain light-emitting device on a combined substrate |
JP5180050B2 (ja) * | 2008-12-17 | 2013-04-10 | スタンレー電気株式会社 | 半導体素子の製造方法 |
KR101142082B1 (ko) | 2009-03-12 | 2012-05-03 | 주식회사 엘지실트론 | 질화물 반도체 기판 및 그 제조 방법과 이를 이용한 질화물반도체 소자 |
-
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Non-Patent Citations (2)
Title |
---|
None |
See also references of EP2555256A4 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014026999A (ja) * | 2012-07-24 | 2014-02-06 | Sophia School Corp | 半導体装置、テンプレート基板、半導体装置の製造方法 |
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US8716042B2 (en) | 2014-05-06 |
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