WO2011087003A1 - ３次元実装方法および装置 - Google Patents

３次元実装方法および装置 Download PDF

Info

Publication number
WO2011087003A1
WO2011087003A1 PCT/JP2011/050304 JP2011050304W WO2011087003A1 WO 2011087003 A1 WO2011087003 A1 WO 2011087003A1 JP 2011050304 W JP2011050304 W JP 2011050304W WO 2011087003 A1 WO2011087003 A1 WO 2011087003A1
Authority
WO
WIPO (PCT)
Prior art keywords
upper layer
alignment
sequentially
recognized
objects
Prior art date
Application number
PCT/JP2011/050304
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
寺田勝美
大林拓治
Original Assignee
東レエンジニアリング株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東レエンジニアリング株式会社 filed Critical 東レエンジニアリング株式会社
Priority to KR1020127015218A priority Critical patent/KR101802173B1/ko
Priority to JP2011549979A priority patent/JP5984394B2/ja
Publication of WO2011087003A1 publication Critical patent/WO2011087003A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75801—Lower part of the bonding apparatus, e.g. XY table
    • H01L2224/75804—Translational mechanism
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
    • H01L2224/75824—Translational mechanism
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Definitions

  • the present invention relates to a three-dimensional mounting method and apparatus for sequentially stacking and bonding objects to be bonded such as semiconductor elements in the vertical direction.
  • a COC method Chip On Chip
  • COW method Chip On Wafer
  • a wafer there is a WOW method (Wafer On Wafer) in which wafers are sequentially stacked.
  • the upper layer bonded object is sequentially laminated and bonded in a state in which the position of the electrode of the upper bonded object is aligned with the position of the electrode (including the bump) of the lower bonded object.
  • the position of the lower object for example, the position of the electrode or the position of the alignment mark
  • the position of the upper layer object to be stacked on the lower layer object to be recognized is aligned with the position of the lower object to be recognized by the camera), and the position of the upper layer object to be stacked is recognized from above by the recognition means.
  • the upper layer bonded object sequentially laminated on the lowermost layer bonded object usually has one surface formed on the circuit surface and an electrode penetrating from the circuit surface to the back surface. After this circuit surface is the lower surface side, the electrodes are aligned with respect to the object to be bonded located below, and then laminated and bonded. The position of the bonded upper layer object is recognized from the back side opposite to the circuit surface, and the position of the upper layer object is further aligned and bonded based on the recognized position. Therefore, in the middle of stacking a plurality of upper layer bonded objects, the position of the stacked upper layer bonded objects must always be read and recognized from the back side.
  • the circuit surface side is usually clean, and it is in a state where the position of the electrode and the position of the alignment mark for alignment can be clearly recognized.
  • the mark shape or the like is usually not clearly imprinted or printed, and the mark is very small and is extremely difficult to read. Therefore, in the method of performing position recognition from the back side, recognition errors are likely to occur, and recognition errors such as alignment marks directly lead to deterioration in mounting accuracy. Further, in the case where mounting is performed based on the mark reference on the back surface of the upper layer bonded object, the mark errors are sequentially accumulated, so that the mounting shift with respect to the lowermost layer increases according to the number of layers.
  • the object of the present invention is to focus on the problems in the conventional position recognition as described above, and to reliably and easily align the upper layer objects to be sequentially stacked with high accuracy.
  • An object of the present invention is to provide a three-dimensional mounting method and apparatus capable of improving the mounting accuracy in a three-dimensional assembly state.
  • the three-dimensional mounting method according to the present invention is a state in which a plurality of upper layer bonded objects having through electrodes are placed on the lowermost layer bonded objects having electrodes and the positions of the electrodes are aligned.
  • the three-dimensional mounting method of sequentially stacking the position of alignment of the lowermost layer bonded object is recognized, and the electrodes sequentially position all upper layer bonded objects based on the recognized alignment position of the lowermost layer bonded object. It consists of the method characterized by sequentially laminating the upper layer objects to be joined at the predetermined positions while sequentially matching the predetermined positions to be connected.
  • the alignment position of the lowermost layer object is recognized, and all the upper layer objects sequentially stacked on the basis of the position of the lowermost layer object.
  • the alignment of the joint is performed sequentially. Therefore, no matter how many layers of the upper layer bonded object are stacked, the upper layer bonded object (the upper surface of the upper layer bonded object (the back surface opposite to the circuit surface) side) does not become a reference for alignment, There is no need to recognize the position on the hard-to-read surface.
  • the alignment position of the upper-layer object to be aligned only needs to be recognized on the lower surface side (circuit surface side) and can be recognized with high accuracy.
  • the first recognition means recognizes (recognizes from above) and stores the alignment position of the lowermost layer bonded object, and stores a plurality of upper layers.
  • the second recognition means sequentially recognizes the alignment position of the object to be bonded (recognized from below), and the upper layer object whose alignment position has been recognized is stored in the alignment of the lowermost layer object to be stored. Stacking may be performed sequentially while aligning with the predetermined position sequentially with reference to the use position.
  • the first recognizing unit and the second recognizing unit may be configured as a two-field recognizing unit having a visual field in the vertical direction, or may be configured as separate recognizing units.
  • the alignment position of each object to be bonded it is possible to recognize the position of the electrode and the outer position of the object to be bonded, but formed in a specific shape (for example, a cross shape, etc.) If the mark given for alignment is recognized, it can contribute to the improvement of recognition accuracy.
  • the alignment position of the lowermost layer bonded object is recognized by an alignment mark attached to the upper surface of the lowermost layer bonded object, and the alignment position of the plurality of upper layer bonded objects is determined for each upper layer bonded object. It can be recognized by an alignment mark attached to the lower surface of the object.
  • each upper layer bonded object since the height of each upper layer bonded object sequentially changes as the stacking progresses, the upper layer bonded object held by the head or the like is stacked on the lowermost layer bonded object or the lowermost layer bonded object.
  • the alignment position of the upper layer bonded object is preferably recognized by, for example, the second recognizing means when the upper layer bonded object is on the mounting position.
  • the position for alignment of the upper layer bonded object (for example, the position of the upper layer bonded object with respect to the head holding the upper layer bonded object) is recognized in the middle of conveying the upper layer bonded object to the mounting position, and the Implementation can also be performed based on the recognition position. In this case, it is possible to eliminate the advance / retreat operation of the recognition means for recognizing the alignment position of the upper-layer workpiece at the mounting position, so that the time required for a series of processes from conveyance to mounting can be reduced. is there.
  • an object to be bonded all forms and all kinds of objects to be bonded may be used as long as a plurality of upper layer bonded objects having through electrodes are three-dimensionally mounted on a lowermost layer bonded object having electrodes.
  • An object can be used, and typically, an object to be bonded is made of a chip or a wafer. In this case, any of the above-described COC method, COW method, and WOW method can be applied.
  • the present invention also provides a three-dimensional mounting apparatus. That is, the three-dimensional mounting apparatus according to the present invention is a three-dimensional mounting in which a plurality of upper layer objects having through electrodes are sequentially stacked on the lowermost object having electrodes.
  • first recognition means for recognizing an alignment position of the lowermost layer bonded object held on a stage, a head for holding the upper layer bonded object sequentially stacked, and the lowermost layer bonded object Is recognized by the first recognizing means
  • the second recognizing means for recognizing the alignment position of the upper layer object held by the head, and the first recognizing means.
  • the position of all the upper layer objects to be recognized by the second recognizing means with respect to the alignment position of the lowermost object to be bonded is sequentially adjusted to a predetermined position where the electrodes are sequentially connected, position A mounting control means for stacking the Align obtained upper joining target sequence consists of those characterized by having a.
  • the three-dimensional mounting apparatus includes a storage unit that stores the alignment position of the lowermost layer object recognized by the first recognition unit, and the mounting control unit sequentially uses the second recognition unit.
  • the upper layer object to be recognized is sequentially stacked with the position of the recognized upper layer object being sequentially aligned with the predetermined position with reference to the alignment position of the lowermost layer object stored in the storage means. it can.
  • the alignment position of the lowermost layer bonded object is recognized by an alignment mark attached to the upper surface of the lowermost layer bonded object
  • the alignment positions of the plurality of upper layer bonded objects are It can be configured to be recognized by an alignment mark attached to the lower surface of the object.
  • the mounting control means for each upper layer object to be sequentially stacked, the upper layer object to be mounted is changed so that the mounting height with respect to the position of the lowermost layer object in the stacking direction or the reference position corresponding thereto is changed. It is preferable to be configured to control the position in the stacking height direction.
  • the second recognizing means preferably comprises means for recognizing the upper layer bonded object when the head holding the upper layer bonded object is on the mounting position.
  • a typical object to be bonded can be a chip or a wafer.
  • the three-dimensional mounting method and apparatus since all upper layer objects are sequentially aligned and stacked based on the recognition position of the lowermost layer object, each upper layer that is difficult to read as in the prior art. It becomes unnecessary to read the upper surface of the object to be joined, and high-precision positioning can be easily performed, so that the mounting accuracy can be greatly improved and the reliability of high-precision three-dimensional mounting can be improved.
  • FIG. 1 shows a three-dimensional mounting apparatus according to an embodiment of the present invention.
  • the three-dimensional mounting apparatus 1 includes a plurality of upper-layer chips 5 as upper-layer objects to be bonded, each having a through-electrode 4, and electrodes 2, 4, on a lower-layer chip 3 as a lower-layer object having electrodes 2. It consists of what laminates
  • the three-dimensional mounting apparatus 1 recognizes the alignment position (for example, the position of the alignment mark) of the lowermost layer chip 3 held on the stage 6 (for example, held by suction).
  • First recognition means and second recognition means for recognizing the alignment position (for example, the position of the alignment mark) of the upper chip 5 held by the head 7 (for example, the pressure / heating head).
  • the first recognizing unit and the second recognizing unit are configured as a two-field camera 8 as a two-field recognizing unit having a field of view in two directions.
  • the two-field camera 8 is provided between the lowermost lower layer chip 3 and the upper upper layer chip 5, that is, with respect to the mounting position of the upper layer chip 5, so that it can advance and retreat as necessary.
  • the three-dimensional mounting apparatus 1 has moving means capable of controlling the relative position between the head 7 holding the upper layer chips 5 stacked sequentially and the stage 6 holding the lowermost layer chip 3.
  • the upper layer chip 5 is aligned with the lowermost layer chip 3 by the control of the moving means.
  • the position on the stage 6 side is controlled for this alignment, but the position on the head 7 side may be controlled, and the positions on both sides are controlled. You may comprise.
  • the three-dimensional mounting apparatus 1 penetrates through the positions of all the upper layer chips 5 recognized by the second recognition unit with reference to the alignment position of the lowermost layer chip 3 recognized by the first recognition unit.
  • a mounting control means 9 is provided for sequentially stacking the upper layer chip 5 aligned with the predetermined position on the lower layer while sequentially aligning with the predetermined position where the electrodes 4 are sequentially connected.
  • the three-dimensional mounting is performed as shown in FIG. 3, for example.
  • the alignment position (position of the alignment mark) of the lowermost chip 3 held on the stage 6 is recognized by the first recognition means (a camera having a field of view below the two-field camera 8), and the position. Information is stored in storage means in the mounting control means 9. Based on the alignment position information of the lowermost layer chip 3 stored in the storage means, the alignment of all the upper layer chips 5 that are sequentially stacked is sequentially performed.
  • the alignment position of the upper chip 5 (the position of the alignment mark) is recognized by the second recognition means (a camera having a field of view above the two-field camera 8), and this recognition position information is stored in the storage means.
  • the position of the upper layer chip 5 is controlled such that the positions of the electrodes 2 and 4 are matched with the alignment position information of the lowermost layer chip 3. Actually, since the position on the stage 6 side is controlled in this embodiment, the position control of the stage 6 is performed based on both position information.
  • the upper layer chip 5 that is the uppermost layer does not necessarily have to be the through electrode 4 similar to the intermediate layer.
  • the position recognition by the second recognition means (the camera having a field of view above the two-field camera 8) of the upper layer chip 5 is performed from the chip lower surface side at the mounting position.
  • second recognition means having a configuration different from the above (for example, a camera having a field of view only upward) while the upper layer chip 5 held by the head 7 is being transported to the mounting position. It is also possible to recognize the alignment position in 11) and align the position of the lowermost layer chip 3 at the mounting position with reference to the recognized position information. In this way, since the reading time of the upper layer chip 5 can be reduced, the time of the entire three-dimensional mounting process having a series of operations can be shortened.
  • the three-dimensional mounting method and apparatus according to the present invention can be applied to any three-dimensional mounting in which workpieces having electrodes are stacked in the vertical direction.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Supply And Installment Of Electrical Components (AREA)
PCT/JP2011/050304 2010-01-15 2011-01-12 ３次元実装方法および装置 WO2011087003A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020127015218A KR101802173B1 (ko) 2010-01-15 2011-01-12 3차원 실장방법 및 장치
JP2011549979A JP5984394B2 (ja) 2010-01-15 2011-01-12 ３次元実装方法および装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-006897 2010-01-15
JP2010006897 2010-01-15

Publications (1)

Publication Number Publication Date
WO2011087003A1 true WO2011087003A1 (ja) 2011-07-21

Family

ID=44304277

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/050304 WO2011087003A1 (ja) 2010-01-15 2011-01-12 ３次元実装方法および装置

Country Status (4)

Country Link
JP (1) JP5984394B2 (zh)
KR (1) KR101802173B1 (zh)
TW (1) TWI506717B (zh)
WO (1) WO2011087003A1 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013187292A1 (ja) * 2012-06-11 2013-12-19 株式会社新川 ボンディング装置および半導体装置の製造方法
JP2014187220A (ja) * 2013-03-25 2014-10-02 Toshiba Corp 半導体装置の製造方法
WO2015079991A1 (ja) * 2013-11-27 2015-06-04 東レエンジニアリング株式会社 ３次元実装方法および３次元実装装置
CN110383446A (zh) * 2017-03-16 2019-10-25 Ev 集团 E·索尔纳有限责任公司 用于接合至少三个衬底的方法
JP2020136389A (ja) * 2019-02-15 2020-08-31 日本放送協会 積層型半導体集積回路およびその製造方法
CN110383446B (zh) * 2017-03-16 2024-07-16 Ev集团E·索尔纳有限责任公司 用于接合至少三个衬底的方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014187185A (ja) * 2013-03-22 2014-10-02 Renesas Electronics Corp 半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273525A (ja) * 2003-03-05 2004-09-30 Seiko Epson Corp 半導体装置の製造方法、半導体装置、及び電子機器
JP2005183580A (ja) * 2003-12-18 2005-07-07 Seiko Epson Corp 半導体装置の製造方法、半導体装置、回路基板、電子機器
JP2007194491A (ja) * 2006-01-20 2007-08-02 Renesas Technology Corp 半導体装置、インタポーザチップ、および半導体装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8367471B2 (en) * 2007-06-15 2013-02-05 Micron Technology, Inc. Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273525A (ja) * 2003-03-05 2004-09-30 Seiko Epson Corp 半導体装置の製造方法、半導体装置、及び電子機器
JP2005183580A (ja) * 2003-12-18 2005-07-07 Seiko Epson Corp 半導体装置の製造方法、半導体装置、回路基板、電子機器
JP2007194491A (ja) * 2006-01-20 2007-08-02 Renesas Technology Corp 半導体装置、インタポーザチップ、および半導体装置の製造方法

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385104B2 (en) 2012-06-11 2016-07-05 Shinkawa Ltd. Bonding apparatus
JP2014017471A (ja) * 2012-06-11 2014-01-30 Shinkawa Ltd ボンディング装置およびボンディング方法
KR20140117543A (ko) * 2012-06-11 2014-10-07 가부시키가이샤 신가와 본딩 장치 및 반도체 장치의 제조 방법
WO2013187292A1 (ja) * 2012-06-11 2013-12-19 株式会社新川 ボンディング装置および半導体装置の製造方法
KR101630249B1 (ko) 2012-06-11 2016-06-14 가부시키가이샤 신가와 본딩 장치 및 반도체 장치의 제조 방법
JP2014187220A (ja) * 2013-03-25 2014-10-02 Toshiba Corp 半導体装置の製造方法
JPWO2015079991A1 (ja) * 2013-11-27 2017-03-16 東レエンジニアリング株式会社 ３次元実装方法および３次元実装装置
KR20160090842A (ko) 2013-11-27 2016-08-01 토레이 엔지니어링 컴퍼니, 리미티드 3차원 실장 방법 및 3차원 실장 장치
WO2015079991A1 (ja) * 2013-11-27 2015-06-04 東レエンジニアリング株式会社 ３次元実装方法および３次元実装装置
US9673166B2 (en) 2013-11-27 2017-06-06 Toray Engineering Co., Ltd. Three-dimensional mounting method and three-dimensional mounting device
CN110383446A (zh) * 2017-03-16 2019-10-25 Ev 集团 E·索尔纳有限责任公司 用于接合至少三个衬底的方法
JP2020511784A (ja) * 2017-03-16 2020-04-16 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 少なくとも３枚の基板を接合するための方法
JP7177781B2 (ja) 2017-03-16 2022-11-24 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 少なくとも３枚の基板を接合するための方法
CN110383446B (zh) * 2017-03-16 2024-07-16 Ev集团E·索尔纳有限责任公司 用于接合至少三个衬底的方法
JP2020136389A (ja) * 2019-02-15 2020-08-31 日本放送協会 積層型半導体集積回路およびその製造方法
JP7253402B2 (ja) 2019-02-15 2023-04-06 日本放送協会 積層型半導体集積回路およびその製造方法

Also Published As

Publication number Publication date
JPWO2011087003A1 (ja) 2013-05-20
KR20120118458A (ko) 2012-10-26
TW201140739A (en) 2011-11-16
KR101802173B1 (ko) 2017-11-28
TWI506717B (zh) 2015-11-01
JP5984394B2 (ja) 2016-09-06

Similar Documents

Publication Publication Date Title
WO2011087003A1 (ja) ３次元実装方法および装置
JP6454283B2 (ja) ３次元実装方法および３次元実装装置
JP5989313B2 (ja) ダイボンダ及びボンディング方法
JP6510838B2 (ja) ボンディング装置及びボンディング方法
JP5344145B2 (ja) ボンディング装置における電子部品と基板の位置合わせ方法
JP7045891B2 (ja) 半導体製造方法、半導体製造装置及び半導体装置
JP4618859B2 (ja) 積層ウエハーのアライメント方法
CN109314065B (zh) 安装装置和安装方法
TW201633441A (zh) 接合裝置及接合方法
JP2006100656A (ja) ウェハ積層時の重ね合わせ方法
TW201711085A (zh) 半導體裝置之製造方法及安裝裝置
KR102336342B1 (ko) 반도체 소자를 본딩하기 위한 시스템과 방법
JP4861690B2 (ja) チップの実装装置
JP2009260008A (ja) 半導体装置製造装置および半導体装置の製造方法
JP5702114B2 (ja) チップの積層装置及び積層方法
JP5953068B2 (ja) 電子部品の載置テーブルと同テーブルを備えたダイボンダ
JP2010192817A (ja) ピックアップ方法及びピックアップ装置
JP5656609B2 (ja) 治具プレートを使用した半導体デバイスチップの積層方法
JP6596653B2 (ja) 部品実装装置および部品実装方法ならびに部品実装システム
JP6589130B2 (ja) 部品実装装置および部品実装方法ならびに部品実装システム
JP6167412B2 (ja) 積層パッケージの製造システムおよび製造方法
JP2009164407A (ja) 樹脂封止装置および樹脂封止方法
CN114981936A (zh) 接合装置及接合方法
JP2010129576A (ja) 積層半導体基板、及び、積層半導体基板の製造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2011549979

Country of ref document: JP

ENP Entry into the national phase

Ref document number: 20127015218

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11732873

Country of ref document: EP

Kind code of ref document: A1