TW201711085A - 半導體裝置之製造方法及安裝裝置 - Google Patents

半導體裝置之製造方法及安裝裝置 Download PDF

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TW201711085A
TW201711085A TW105106352A TW105106352A TW201711085A TW 201711085 A TW201711085 A TW 201711085A TW 105106352 A TW105106352 A TW 105106352A TW 105106352 A TW105106352 A TW 105106352A TW 201711085 A TW201711085 A TW 201711085A
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semiconductor wafer
semiconductor
bonding head
wafer
gap
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TWI616928B (zh
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深山真哉
小牟田直幸
渡部博
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東芝股份有限公司
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Abstract

本發明之實施形態係提供一種可使經積層之半導體晶片間之連接可靠性提昇之半導體裝置之製造方法及安裝裝置。 根據實施形態，於間隙算出部7D，基於接合頭2之Z座標Z1、Z2及半導體晶片P2之晶片厚度T，算出半導體晶片P1、P2間之Z軸方向之間隙G，若間隙G為規格範圍內之情形時，使安裝裝置持續運轉，若間隙G為規格範圍以外之情形時，使安裝裝置告警停止。

Description

半導體裝置之製造方法及安裝裝置 [相關申請案]
本申請享有以日本專利申請2015-177482號(申請日：2015年9月9日)為基礎申請之優先權。本申請通過參照該基礎申請而包括基礎申請之全部內容。
本發明之實施形態係關於一種半導體裝置之製造方法及安裝裝置。
於半導體裝置中，存在為削減安裝面積，而將半導體晶片積層之情形。存在半導體晶片間之連接中使用微凸塊之情形。
本發明之實施形態係提供一種可使積層所得之半導體晶片間之連接可靠性提昇之半導體裝置之製造方法及安裝裝置。
實施形態之製造方法係將利用接合頭拾取之第2半導體晶片積層於第1半導體晶片上，且基於積層上述第2半導體晶片積層時之上述接合頭之垂直座標，算出上述第1半導體晶片與上述第2半導體晶片之垂直方向之間隙。
1‧‧‧接合台
2‧‧‧接合頭
3‧‧‧垂直活動體
4‧‧‧水平活動體
5‧‧‧導軌
6‧‧‧晶圓載置台
7‧‧‧控制裝置
7A‧‧‧保持控制部
7B‧‧‧水平控制部
7C‧‧‧垂直控制部
7D‧‧‧間隙算出部
7E‧‧‧負載控制部
7F‧‧‧溫度控制部
8‧‧‧雷射位移計
A1、A2‧‧‧背面電極
B1、B2‧‧‧凸塊電極
C0、C1、C2‧‧‧表面電極
K‧‧‧安裝基板
SA1、SA2‧‧‧隔片
P1、P2‧‧‧半導體晶片
W‧‧‧晶圓
T‧‧‧晶片厚度
G‧‧‧間隙
圖1係表示第1實施形態之安裝裝置之概略構成之立體圖。
圖2(a)~(c)係表示第2實施形態之半導體裝置之製造方法之剖視圖。
圖3係表示第2實施形態之半導體裝置之製造方法之流程圖。
圖4係表示第2實施形態之半導體晶片之安裝方法之流程圖。
圖5係表示第3實施形態之半導體裝置之製造方法之流程圖。
圖6(a)及(b)係表示第4實施形態之安裝裝置之概略構成之立體圖。
圖7係表示第5實施形態之半導體裝置之製造方法之流程圖。
圖8(a)~(c)係表示第6實施形態之半導體裝置之製造方法之剖視圖。
以下參照隨圖式式，詳細地說明實施形態之半導體裝置之製造方法及安裝裝置。再者，本發明並非被該等實施形態限定。
(第1實施形態)
圖1係表示第1實施形態之安裝裝置之概略構成之立體圖。
圖1中，於安裝裝置，設置有接合台1、接合頭2、垂直活動體3、水平活動體4、晶圓載置台6及控制裝置7。於接合台1，置放有安裝基板K及半導體晶片P1、P2。接合台1可沿著水平方向(沿X軸方向及視需要沿Y軸方向)移動。接合頭2係拾取半導體晶片P1、P2。垂直活動體3可使接合頭1沿垂直方向(Z軸方向)移動。垂直活動體3係由水平活動體4支持。水平活動體4可於接合台1與晶圓載置台6之間沿水平方向(Y軸方向)移動。水平活動體4係以可沿水平方向移動之方式，由導軌5支持於接合台1及接合頭2上。晶圓載置台6係保持晶圓W。此時，晶圓W被單片化為每一個半導體晶片P1、P2。
於控制裝置7，設置有保持控制部7A、水平控制部7B、垂直控制部7C、間隙算出部7D、負載控制部7E及溫度控制部7F。保持控制部7A係控制接合頭2對半導體晶片P1、P2之拾取。水平控制部7B係控制接合台1及水平活動體4之水平位置。垂直控制部7C係控制接合頭2之 垂直座標。間隙算出部7D係基於將半導體晶片P1、P2積層時之接合頭2之垂直座標(Z座標)，算出半導體晶片P1、P2間之垂直方向之間隙。於接合頭2之Z座標之計測中，例如作為使用滾珠螺桿與馬達使垂直活動體3沿Z軸方向移動之方法，可使用計測該馬達之旋轉角之旋轉編碼器。且，可藉由將由旋轉編碼器所計測之旋轉角轉換為Z軸方向之移動量，而計測接合頭2之Z座標。或者，若為使垂直活動體3沿Z軸方向移動，而使用線性導軌及線性馬達之情形時，例如，亦可藉由將雷射位移計等固定地安裝於水平活動體4，且對垂直活動體3之上表面照射雷射光，而計測接合頭2之Z座標。
負載控制部7E係控制將半導體晶片P1、P2積層時施加於半導體晶片P1、P2之負載。此時，可於接合頭2設置計測施加於半導體晶片P1、P2之負載之負載感測器。溫度控制部7F係控制將半導體晶片P1、P2積層時半導體晶片P1、P2之溫度。此時，於接合台1及接合頭2，可分別設置將接合台1及接合頭2加熱之加熱器。又，可於接合台1及接合頭2，分別設置計測接合台1及接合頭2的溫度之溫度感測器。
(第2實施形態)
圖2(a)~圖2(c)係表示第2實施形態之半導體裝置之製造方法之剖視圖。
圖2(a)~圖2(c)中，於安裝基板K上設置有表面電極C0。於半導體晶片P1之背面側設置有背面電極A1，且於半導體晶片P1之表面側設置有表面電極C1。於背面電極A1上設置有凸塊電極B1。於半導體晶片P2之背面側設置有背面電極A2，於半導體晶片P2之表面側設置有表面電極C2。於背面電極A2上設置有凸塊電極B2。凸塊電極B1、B2之間距可設定為10~100μm左右。凸塊電極B1、B2之直徑可設定為5~50μm左右。再者，安裝基板K可使用例如多層印刷配線板。於半導體晶片P1、P2形成有電晶體等器件。該器件可為NAND快閃記憶 體，亦可為邏輯電路，或者亦可為處理器。安裝基板K之基材可使用例如BT(Bismaleimide Triazine，雙馬來醯亞胺三嗪)樹脂等。表面電極C0之材料可使用Cu等。亦可於表面電極C0中自阻焊劑露出之部分形成Au覆膜。背面電極A1、A2及表面電極C1、C2之材料可為Au、Cu、Ni、Sn、Pg、Ag等之單層膜，亦可為積層膜。凸塊電極B1、B2之材料可使用焊料材等。
例如，作為表面電極C1、C2及背面電極A1、A2之材料，可使用Ni。此時，於Ni下，亦可為使用Ti之障壁金屬膜。於該Ni上、亦可為Au覆膜。作為凸塊電極B2之材料，可使用Sn。於該Sn下，作為基底層亦可為Cu。
繼而，如圖2(a)所示，於接合台1上置放安裝基板K。繼而，藉由將水平活動體4移動至晶圓載置台6上，且使垂直活動體3下降，而使接合頭2接觸於半導體晶片P1。繼而，利用接合頭2拾取半導體晶片P1之後，將水平活動體4移動至接合台1上。繼而，使接合台1沿水平方向移動之後，進行半導體晶片P1與安裝基板K之XY座標之位置對準，且使垂直活動體3下降，藉此，將半導體晶片P1配置於安裝基板K上。繼而，於介隔接合頭2對半導體晶片P1施加負載之狀態下將半導體晶片P1加熱。此時，凸塊電極B1熔融而與表面電極C0接合。此後，藉由介隔接合頭2將半導體晶片P1冷卻而使凸塊電極B1固化。繼而，藉由使接合頭2上升而使接合頭2自半導體晶片P1分離。此處，於凸塊電極B1與表面電極C0之接合時計測接合頭2之Z座標Z1，且將該Z座標Z1記憶於控制裝置7。該Z座標Z1之計測可於凸塊電極B1熔融時進行，亦可於凸塊電極B1熔融後之固化時進行。
其次，藉由將水平活動體4移動至晶圓載置台6上，且使垂直活動體3下降，而使接合頭2接觸於半導體晶片P2。繼而，利用接合頭2拾取半導體晶片P2之後，將水平活動體4移動至接合台1上。繼而，使 接合台1沿水平方向移動之後，於半導體晶片P1、P2間進行XY座標之位置對準，如圖2(b)所示，藉由使垂直活動體3下降，而將半導體晶片P2配置於半導體晶片P1上。繼而，如圖2(c)所示，於介隔接合頭2對半導體晶片P2施加負載之狀態下將半導體晶片P2加熱。此時，凸塊電極B2熔融而與表面電極C1接合。例如，凸塊電極B2中使用Sn且表面電極C1中使用Ni之情形時，於凸塊電極B2與表面電極C1之接合時形成Ni-Sn合金。此後，藉由介隔接合頭2將半導體晶片P2冷卻，而將凸塊電極B2固化。繼而，藉由使接合頭2上升而使接合頭2自半導體晶片P2分離。此處，於凸塊電極B2與表面電極C1之接合時計測接合頭2之Z座標Z2，且將該Z座標Z2記憶於控制裝置7中。該Z座標Z2之計測可於凸塊電極B2之熔融時進行，亦可於凸塊電極B2熔融後之固化時進行。此時，於控制裝置7中，載入半導體晶片P2之晶片厚度T之資料。該資料可為設計資料，亦可為半導體晶片P2之加工時所取得之加工資料。該加工資料例如可使用利用CMP(Chemical Mechanical Polishing，化學機械拋光)將晶圓W薄膜化時之晶圓W之晶片厚度資料。
繼而，於間隙算出部7D中，基於接合頭2之Z座標Z1、Z2及半導體晶片P2之晶片厚度T，算出半導體晶片P1、P2間之Z軸方向之間隙G。此時，能夠以G=Z2-Z1-T賦予。判定間隙G是否為規格範圍內，且於間隙G為規格範圍以外之情形時，使圖1之安裝裝置告警停止。再者，因於間隙G之算出時獲取Z座標Z1、Z2之差值，故Z座標Z1、Z2之原點位於任何處均可。又，接合頭2之Z座標Z1、Z2若與接合頭2一體地沿Z軸方向移動，則可於任何部分進行計測。例如，可計測接合頭2之Z座標，亦可計測垂直活動體3之Z座標。
此處，於將半導體晶片P2安裝於半導體晶片P1上時，可藉由算出半導體晶片P1、P2間之間隙G，而管理凸塊電極B2之接觸狀態，從 而可減少凸塊電極B2之接觸不良。此時，半導體晶片P1、P2間之間隙G會因凸塊電極B2之材料或尺寸等之偏差或施加於半導體晶片P2之負載等而變化。例如，若凸塊電極B2之尺寸偏差變大，則半導體晶片P1、P2間之間隙G變大，而可能發生凸塊電極B2之接觸不良。又，若施加於半導體晶片P2之負載變小，則半導體晶片P1、P2間之間隙G變大，而可能發生凸塊電極B2之接觸不良。又，若施加於半導體晶片P2之負載變大，則半導體晶片P1、P2間之間隙G變小，而可能發生鄰接之凸塊電極B2間短路之情形。又，若凸塊電極B2之材料之偏差變大，則凸塊電極B2之熔點偏差亦變大，從而半導體晶片P1、P2間之間隙G變小，故可能發生鄰接之凸塊電極B2間短路之情況。因此，於間隙G為規格範圍以外之情形時，可藉由使圖1之安裝裝置告警停止，而減少半導體晶片P2之安裝不良。
積層於安裝基板K上之半導體晶片P1、P2可應用於例如SiP(System in Package，系統級封裝)。為獲得半導體晶片P1、P2間之電性連接，可於各半導體晶片P1、P2形成貫通電極，亦可使用接合線。
圖3係表示第2實施形態之半導體裝置之製造方法之流程圖。
於圖3中，預先輸入半導體晶片之晶片厚度T之設計資料(S1)。繼而，安裝利用接合頭2拾取之本次之半導體晶片(S2)。此時，將接合頭2之Z座標Z1記憶作為基準座標。繼而，確認半導體晶片之積層階數(S3)，於積層階數為特定階數之情形時，結束安裝。另一方面，於積層階數不足之情形時，利用接合頭2拾取下一個半導體晶片(S4)，且將該半導體晶片之晶片厚度T之設計資料讀入至間隙算出部7D(S5)。繼而，將利用接合頭2所拾取之上層之半導體晶片安裝於下層之半導體晶片上(S6)。此時，記憶接合頭2之Z座標Z2。繼而，基於接合頭2之Z座標Z1、Z2及半導體晶片之晶片厚度T，算出積層後之半 導體晶片間之間隙G(S7)。此時，若間隙G為規格範圍以外，使圖1之安裝裝置告警停止(S8)。另一方面，於間隙G為規格範圍內之情形時，將基準座標自Z1重寫為Z2(S9)，且返回至S3。繼而，重複進行S3~S9之處理，直到半導體晶片之積層階數達到特定階數為止。
圖4係表示第2實施形態之半導體晶片之安裝方法之流程圖。再者，圖4之步驟可用於圖3之S2及S6。
於圖4中，若使利用接合頭2所拾取之半導體晶片移動至接合台1上，則進行半導體晶片之XY座標之位置對準(S51)。繼而，藉由使接合頭2下降(S52)，而將上層之半導體晶片配置於下層之半導體晶片上。繼而，於介隔接合頭2對半導體晶片施加負載之狀態下將半導體晶片加熱(S53、S54)。此時，介隔凸塊電極將上層之半導體晶片接合於下層之半導體晶片。此時，可記憶接合頭2之Z座標。此後，藉由介隔接合頭2將半導體晶片冷卻，而使凸塊電極固化(S55)。再者，亦可記憶凸塊電極已熔融時之接合頭2之Z座標，但亦可記憶凸塊電極已被固化時之接合頭2之Z座標。繼而，藉由使接合頭2上升而使接合頭2自半導體晶片分離(S56)。
(第3實施形態)
圖5係表示第3實施形態之半導體裝置之製造方法之流程圖。
於圖5中，該流程設置S1'而取代圖3之S1。其他則與圖3之流程相同。於S1中，輸入晶片厚度T之設計資料，但於S1'中，讀取晶圓W之晶片厚度T之加工資料。繼而，於S7之間隙G之算出中，使用加工資料而取代晶片厚度T之設計資料。藉此，於間隙G之算出時，可反映出晶圓加工時之製造偏差所造成之晶片厚度T之誤差，從而可使間隙G之算出精度提昇。
(第4實施形態)
圖6(a)及圖6(b)係表示第4實施形態之安裝裝置之概略構成之立體 圖。
於圖6(a)及圖6(b)之安裝裝置中，設置控制裝置7'而取代圖1之控制裝置7。於控制裝置7'中，將晶片厚度測定部7G追加至控制裝置7。晶片厚度測定部7G進行雷射位移計8對晶片厚度T之計測控制。又，於圖6(a)及圖6(b)之安裝裝置中，對於圖1之安裝裝置追加雷射位移計8。雷射位移計8可藉由自半導體晶片P2之上下對半導體晶片P2照射雷射，而計測半導體晶片P2之晶片厚度T。
繼而，如圖6(a)所示，於安裝基板K上積層半導體晶片P1之後，利用接合頭2拾取半導體晶片P2。繼而，藉由利用雷射位移計8將半導體晶片P2夾著，自半導體晶片P2之上下照射雷射，而實測半導體晶片P2之晶片厚度T。繼而，如圖6(b)所示，使利用接合頭2所拾取之半導體晶片P2移動至接合台1上。繼而，於半導體晶片P1、P2間進行XY座標之位置對準後，將半導體晶片P2積層於半導體晶片P1上。此處，於安裝基板K上積層半導體晶片P1時，記憶接合頭2之Z座標Z1。又，於將半導體晶片P2積層於半導體晶片P1上時，記憶接合頭2之Z座標Z2。繼而，於間隙算出部7D中，基於接合頭2之Z座標Z1、Z2及半導體晶片P2之晶片厚度T之實測資料，算出半導體晶片P1、P2間之間隙G。
此處，可藉由將晶片厚度T之實測資料用於間隙G之算出，而反映出半導體晶片P1、P2間之晶片厚度T之偏差，從而可使間隙G之算出精度提昇。
(第5實施形態)
圖7係表示第5實施形態之半導體裝置之製造方法之流程圖。
於圖7中，該流程設置S10、S11而取代圖3之S1。其他則與圖3之流程相同。S10係於安裝本次之半導體晶片之前，利用接合頭2拾取本次之半導體晶片。S11係於利用接合頭2拾取下一次之半導體晶片之 後，實測該半導體晶片之晶片厚度T。繼而，於S7之間隙G之算出中，使用實測資料而取代晶片厚度T之設計資料。
(第6實施形態)
圖8(a)~圖8(c)係表示第6實施形態之半導體裝置之製造方法之剖視圖。
於圖8(a)~圖8(c)之構成中，對於半導體晶片P1、P2分別追加隔片SA1、SA2。隔片SA1可確保安裝基板K與半導體晶片P1之間隔。隔片SA2可確保半導體晶片P1、P2間之間隔。隔片SA1、SA2之材料可使用未達凸塊電極B1、B2之熔融溫度且具有接著性之絕緣性樹脂。例如，隔片SA1、SA2之材料可使用環氧樹脂、聚醯亞胺樹脂、丙烯酸樹脂、酚醛樹脂或苯并環丁烯樹脂等。
繼而，如圖8(a)所示，將利用接合頭2所拾取之半導體晶片P1積層於安裝基板K上。此時，半導體晶片P1係利用隔片SA1固定於安裝基板K上。又，記憶接合頭2之Z座標Z1。此時，使凸塊電極B1避免熔融，將凸塊電極B1與表面電極C0維持為未接合之狀態。
繼而，如圖8(b)所示，利用接合頭2拾取半導體晶片P2。繼而，藉由使接合頭2下降至半導體晶片P1上，而如圖8(c)所示，將半導體晶片P2積層於半導體晶片P1上。又，記憶接合頭2之Z座標Z2。此時，使凸塊電極B2避免熔融，從而可將凸塊電極B1、B2維持為彼此未接合之狀態。繼而，基於接合頭2之Z座標Z1、Z2及半導體晶片P2之晶片厚度T，算出半導體晶片P1、P2間之間隙G。繼而，於間隙G為規格範圍內之情形時，使安裝裝置之運轉持續，且於間隙G為規格範圍以外之情形時，使安裝裝置告警停止。若半導體晶片P1、P2之積層階數達到特定階數，則藉由使該等半導體晶片P1、P2之凸塊電極B1、B2一次地熔融而將各凸塊電極B1、B2接合。
此處，可藉由於半導體晶片P1、P2設置隔片SA1、SA2，而無需 使各凸塊電極B1、B2接合，便將半導體晶片P1、P2固定。因此，無需將各半導體晶片P1、P2每積層1層便進行回流焊，從而無需將各半導體晶片P1、P2每積層1層便重複進行溫度之升降，故可使產出量提昇，並且減少施加於各半導體晶片P1、P2之熱應力。
對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提示者，且並非意圖限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施，且於不脫離發明主旨之範圍內，可進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利之範圍中記載之發明及其均等之範圍中。
1‧‧‧接合台
2‧‧‧接合頭
3‧‧‧垂直活動體
4‧‧‧水平活動體
5‧‧‧導軌
6‧‧‧晶圓載置台
7‧‧‧控制裝置
7A‧‧‧保持控制部
7B‧‧‧水平控制部
7C‧‧‧垂直控制部
7D‧‧‧間隙算出部
7E‧‧‧負載控制部
7F‧‧‧溫度控制部
K‧‧‧安裝基板
P1、P2‧‧‧半導體晶片
W‧‧‧晶圓

Claims (5)

  1. 一種半導體裝置之製造方法，其係將利用接合頭所拾取之第2半導體晶片積層於第1半導體晶片上，基於將上述第2半導體晶片積層時之上述接合頭之垂直座標，算出上述第1半導體晶片與上述第2半導體晶片之垂直方向之間隙。
  2. 如請求項1之半導體裝置之製造方法，其判定上述間隙是否為規格範圍內，且於上述間隙為規格範圍以外之情形時，停止將第3半導體晶片向上述第2半導體晶片上積層。
  3. 如請求項1或2之半導體裝置之製造方法，其中若將上述間隙設為G，將於上述第2半導體晶片積層於上述第1半導體晶片上之前之上述接合頭之垂直座標設為Z1，將於上述第2半導體晶片積層於上述第1半導體晶片上之後之上述接合頭之垂直座標設為Z2，且將上述第2半導體晶片之晶片厚度設為T，則上述間隙以G=Z2-Z1-T賦予。
  4. 如請求項3之半導體裝置之製造方法，其中當拾取將上述第2半導體晶片積層於上述第1半導體晶片上之前之上述第2半導體晶片時，計測上述第2半導體晶片之晶片厚度。
  5. 一種安裝裝置，其具備：接合台，其係供置放半導體晶片；接合頭，其係拾取上述半導體晶片；垂直活動體，其係使上述接合頭沿垂直方向移動；垂直控制部，其係控制上述接合頭之垂直座標；及間隙算出部，其係基於積層上述半導體晶片時之上述接合頭之垂直座標，算出上述半導體晶片間之垂直方向之間隙。
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