TWI680522B - 半導體製造方法、半導體製造裝置及半導體裝置 - Google Patents

半導體製造方法、半導體製造裝置及半導體裝置 Download PDF

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TWI680522B
TWI680522B TW107124041A TW107124041A TWI680522B TW I680522 B TWI680522 B TW I680522B TW 107124041 A TW107124041 A TW 107124041A TW 107124041 A TW107124041 A TW 107124041A TW I680522 B TWI680522 B TW I680522B
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semiconductor wafer
semiconductor
layer
mounting
coordinates
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TW107124041A
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TW201941329A (zh
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太駄俊彦
Toshihiko Ohda
黒澤哲也
Tetsuya Kurosawa
福田昌利
Masatoshi Fukuda
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日商東芝記憶體股份有限公司
Toshiba Memory Corporation
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Abstract

本發明之一形態提供一種將複數個半導體晶片積層時不會產生連接不良之半導體製造方法、半導體製造裝置及半導體裝置。 於載置於載置台上之支持基板上安裝半導體晶片或半導體晶片之積層體之實施形態之半導體製造方法具備以下步驟：正在進行半導體晶片或積層體之安裝處理中，判定是否滿足特定之條件；於判定為滿足特定之條件之情形時，使至該時為止安裝於支持基板上之半導體晶片或積層體與支持基板一併退避；於退避後，判定是否重新開始半導體晶片或積層體之安裝處理；當判定為重新開始安裝處理時，使已退避之半導體晶片或積層體返回至退避前之位置繼續進行安裝處理。

Description

半導體製造方法、半導體製造裝置及半導體裝置
本發明之實施形態係關於一種半導體製造方法、半導體製造裝置及半導體裝置。
為了實現半導體裝置之小型化及高功能化，將複數個半導體晶片積層並密封於1個封裝內之SiP(System In Package，系統級封裝)構造之半導體裝置正得以實用化。於SiP構造之半導體裝置中，要求高速地發送接收半導體晶片間之電氣信號。此種情形時，為了將半導體晶片間電性連接，多使用微凸塊。微凸塊係間距10~100μm左右、直徑5~50μm左右之突起，且由焊料等形成於半導體晶片之一面或兩面。一般而言，於將形成有微凸塊之半導體晶片積層之情形時，將微凸塊彼此進行位置對準，一面加熱一面將上下之半導體晶片壓接而連接。
於由於某些原因而使積層半導體晶片之裝置停止之情形時，於積層半導體晶片之載置台上半導體晶片會持續地受到加熱。於此情形時，由加熱而導致半導體晶片上之微凸塊之焊料持續氧化，過量地形成氧化膜。若於微凸塊之表面過量地形成氧化膜，將產生微凸塊之不連接等連接不良。
本發明之一形態提供一種於將複數個半導體晶片積層時不會產生連接不良之半導體製造方法、半導體製造裝置及半導體裝置。
根據本實施形態，提供一種半導體製造方法，於載置於載置台上之支持基板上安裝半導體晶片或半導體晶片之積層體，其具備以下步驟：正在進行上述半導體晶片或上述積層體之安裝處理中，判定是否滿足特定之條件；於判定為滿足上述特定條件之情形時，使至該時為止安裝於上述支持基板上之上述半導體晶片或上述積層體與上述支持基板一併退避；於上述退避後，判定是否重新開始上述半導體晶片或上述積層體之安裝處理；以及當判定為重新開始上述安裝處理時，使上述已退避之上述半導體晶片或上述積層體返回至退避前之位置繼續進行上述安裝處理。
1‧‧‧半導體製造裝置
2‧‧‧條件判定部
3‧‧‧退避控制部
4‧‧‧重新開始判定部
5‧‧‧回復控制部
11‧‧‧載置台
12‧‧‧相機
13‧‧‧頭
14‧‧‧搬送單元
15‧‧‧支持基板
16‧‧‧半導體晶片
16a‧‧‧最下層之半導體晶片
16b‧‧‧其他半導體晶片
16c‧‧‧半導體晶片
16d‧‧‧半導體晶片
17‧‧‧墊
18‧‧‧微凸塊
19‧‧‧對準標記
20‧‧‧積層體
21‧‧‧對準標記
22‧‧‧通道接點
23‧‧‧接著劑
24‧‧‧基板
25‧‧‧樹脂
30‧‧‧半導體裝置
S1~S131‧‧‧步驟
圖1係表示第1實施形態之半導體製造裝置之控制系統之概略構成之方塊圖。
圖2A係表示將複數個半導體晶片積層之工序順序之剖視圖。
圖2B係繼圖2A之後之工序剖視圖。
圖2C係繼圖2B之後之工序剖視圖。
圖2D係繼圖2C之後之工序剖視圖。
圖2E係繼圖2D之後之工序剖視圖。
圖2F係繼圖2E之後之工序剖視圖。
圖2G係繼圖2F之後之工序剖視圖。
圖3係表示第1實施形態之半導體製造裝置之處理動作之流程圖。
圖4係表示第2實施形態之半導體製造裝置之處理動作之流程圖。
圖5係表示第3實施形態之半導體製造裝置之處理動作之流程圖。
圖6係表示第4實施形態之半導體製造裝置之處理動作之流程圖。
圖7係表示第5實施形態之半導體製造裝置之處理動作之流程圖。
圖8A係自側方觀察積層於支持基板上之半導體晶片群之圖。
圖8B係自上方觀察半導體晶片群之圖。
圖9A係使第1層之半導體晶片於X方向上偏移之圖。
圖9B係使第1層之半導體晶片於X方向及Y方向上偏移之圖。
圖9C係利用相機識別設置於與圖9A及圖9B對應之最下層之半導體晶片上之對準標記之圖。
圖9D係使第1層之半導體晶片之配置角度與第2層以後之半導體晶片之配置角度不同之圖。
圖10A係表示於支持基板上設置對準標記之例之圖。
圖10B係與圖10A對應之俯視圖。
圖11係表示第6實施形態之半導體製造裝置之處理動作之流程圖。
圖12A係利用相機識別設置於最下層之半導體晶片或支持基板上之對準標記之圖。
圖12B表示為了與最下層之半導體晶片進行位置對準，利用相機拍攝、及識別自該積層之半導體晶片之背面側之對準標記之狀況之圖。
圖12C係表示使半導體晶片群退避後返回至初始位置之狀態之圖。
圖13A係表示配置於支持基板上之最下層之半導體晶片之圖。
圖13B係於配置於第2層之半導體晶片上形成貫通半導體晶片之通道之圖。
圖13C係將半導體晶片搭載於半導體晶片上之圖。
圖13D係表示將積層體顛倒而於基板24上進行覆晶安裝之例之圖。
圖13E係於晶片積層體24之各半導體晶片間及其周圍形成樹脂之圖。
以下，參考圖式對本發明之一實施形態進行說明。再者，於本案說明書中隨附之圖式中，為了方便圖示與容易理解，有時根據實物之情形將縮小比例、及縱橫之尺寸比等適當地變更誇大。
進而，關於本說明書中使用之特定出形狀、幾何學之條件以及其等之程度之例如「平行」、「正交」、「同一」等用語或長度或角度之值等，並不限於嚴格之意義，包含可期待相同功能之程度之範圍而解釋。
(第1實施形態)
圖1係表示第1實施形態之半導體製造裝置1之控制系統之概略構成之方塊圖。圖1之半導體製造裝置1係於載置於載置台上之支持基板上製作積層有複數個半導體晶片之積層體。所製作之積層體如下所述收納於一個封裝中。圖1之半導體製造裝置1具備條件判定部2、退避控制部3、重新開始判定部4、以及回復控制部5。
條件判定部2於將複數個半導體晶片積層至載置台上之安裝中途，判定是否滿足特定之條件。條件判定部2例如於複數個半導體晶片之安裝中途，判定是否停止安裝處理。安裝處理之停止可由各種因素而產生。例如，為進行安裝處理之裝置由於某些原因而停止之情形。有如下情形：由於裝置故障等裝置本身之原因而使裝置停止、由於環境溫度之異常等環境條件之原因而使裝置停止、或作業者故意地使裝置停止等。於 此，進行安裝處理之裝置係用於積層複數個半導體晶片積層之裝置之總稱，例如係晶片焊接裝置、用於位置對準之相機、加熱半導體晶片之加熱器、將半導體晶片搬送至載置台上之頭、以及使半導體晶片退避之搬送單元等。
退避控制部3於判定為停止安裝處理時，使至該時為止積層之半導體晶片群退避。於半導體晶片群之退避中使用下述之搬送單元。
重新開始判定部4於停止安裝處理之後判定是否重新開始安裝處理。重新開始判定部4於停止安裝處理之因素消失時，使安裝處理重新開始。例如，於進行安裝處理之裝置暫且停止之後開始動作之情形時重新開始安裝處理。
回復控制部5於由重新開始判定部4判定為重新開始安裝處理時，使已退避之半導體晶片群返回至退避前之位置繼續進行安裝處理。如此，回復控制部5將暫且退避之安裝中途之半導體晶片群再利用而不廢棄，形成具備最初預定之積層數之半導體晶片群之積層體。
圖2A~圖2G係表示將複數個半導體晶片積層之工序順序之剖視圖。如該等圖所示，進行安裝處理之裝置具備載置台11、相機12及頭13、以及搬送單元14。載置台11上載置有支持基板15，該支持基板15上積層有複數個半導體晶片16。正在進行之安裝處理中，對與半導體晶片16之墊17接合之微凸塊18進行加熱處理。相機12係用於進行應積層之複數個半導體晶片16之墊17與微凸塊18之位置對準。使對準標記19與墊17、以及對準標記19與微凸塊18之位置關係預先記憶於裝置中，利用相機12對各半導體晶片16上之對準標記19之周邊拍攝、識別而進行位置對準。頭13以吸附其次應積層之半導體晶片16之狀態而進行搬送、安裝。
搬送單元14係本實施形態之特徵之一，用於使安裝中途之半導體晶片群20與支持基板15一併退避。搬送單元14使半導體晶片群20以吸附於支持基板15之狀態而退避至載置台11外。退避目的地係不受載置台11上之溫度影響之部位。藉由利用搬送單元14使半導體晶片群20退避，例如於裝置停止之情形時，不會有半導體晶片群20於載置台11上持續地受到加熱之擔憂，可抑制微凸塊18之氧化。
圖3係表示第1實施形態之半導體製造裝置1之處理動作之流程圖。該流程圖表示於將第n(n係1以上之整數)層之半導體晶片16安裝之後，安裝第(n+1)層之半導體晶片16之處理動作。
首先，條件判定部2判定進行安裝處理之裝置是否停止(步驟S1)。於此，藉由表示進行安裝處理之裝置停止之旗標之值而判定。例如，於旗標為1時表示裝置停止之情形時，即使旗標為1，亦可能有實際上裝置尚未停止之情形。於下述之處理中，若對裝置發出停止之指示，裝置接收該指示而停止。
步驟S1中若判定為未停止，利用相機12識別第n層之半導體晶片16上之對準標記19(步驟S2)。其次，條件判定部2再次判定進行安裝處理之裝置是否停止(步驟S3)。若判定為未停止，利用相機12識別第(n+1)層之半導體晶片16(步驟S4)。
於此，如圖2A所示，使頭13吸附第(n+1)層之半導體晶片16而搬送，利用相機12拍攝及識別第n層之半導體晶片16上之對準標記19、及第(n+1)層之半導體晶片16上之對準標記19，進行位置對準。再者，圖2A中，圖示將相機12配置於第n層之半導體晶片16與第(n+1)層之半導體晶片16之間，拍攝及識別兩半導體晶片16之對準標記19之狀況， 但並非必須於相同時點拍攝及識別兩半導體晶片16之對準標記19。例如，於拍攝及識別第n層之半導體晶片16之對準標記19之後，拍攝及識別第(n+1)層之半導體晶片16之對準標記19。或者，亦可按照與此相反之順序拍攝及識別各半導體晶片16之對準標記19。或者，亦可於相同時點拍攝及識別。又，於相同時點拍攝及識別之情形時，可省略步驟S3之裝置是否停止之判定。之後，如圖2B所示，使頭13朝下方下降，使第(n+1)層之半導體晶片16上之微凸塊18接觸到第n層之半導體晶片16上之墊17，一面賦予熱或超音波一面進行壓接而接合。
其次，再次判定進行安裝處理之裝置是否停止(步驟S5)。於此，若判定為未停止，將第(n+1)層之半導體晶片16搬送至載置台11上且安裝於第n層之半導體晶片16之上(步驟S6)。其次，判定半導體晶片16之積層數是否達到事先預定之數k(步驟S7)。若尚未達到，使n遞增1(步驟S8)，並重複進行步驟S1以後之處理。圖2C表示下一層之半導體晶片16之定位狀況，圖2D表示該層之半導體晶片16之安裝狀況。步驟S7若判定為已達到事先預定之數k，結束處理。
步驟S1、S3或S5中，若判定為進行安裝處理之裝置停止，退避控制部3使至該時為止積層之半導體晶片群20與支持基板15一併由搬送單元14而退避(步驟S9)。若搬送單元14使半導體晶片16退避至退避目的地，於吸附有半導體晶片群20之狀態下使裝置停止(步驟S10)。圖2E表示使支持基板15吸附有搬送單元14之狀態。由於支持基板15上載置有所積層之半導體晶片群20，故而搬送單元14可將支持基板15與半導體晶片群20一併搬送。又，圖2F表示將吸附於搬送單元14之半導體晶片群20與支持基板15提昇至載置台11之上方之狀態。
其次，判定是否需要進行錯誤解除操作(步驟S11)。若判定為需要進行錯誤解除操作，進行錯誤解除操作(步驟S12)，若判定為無需進行錯誤解除操作，則決定重新開始安裝處理，回復控制部5重新開始安裝處理(步驟S13)。於此，由搬送單元14將已退避之半導體晶片群20返回至退避前之位置(步驟S14)。之後，如圖2G所示，於安裝中途之半導體晶片群20之上繼續積層新的半導體晶片16。再者，於圖2G中，實際上亦係例如於拍攝及識別配置於相機12之下側之半導體晶片16之對準標記19之後，拍攝及識別配置於相機12之上側之半導體晶片16之對準標記19。或者亦可按照與此相反之順序拍攝及識別對準標記19。或者，亦可於相同時點拍攝及識別。
如此，於第1實施形態中，於半導體晶片16之安裝中途，由於某些原因而使進行安裝處理之裝置停止之情形時，由搬送單元14使安裝中途之半導體晶片群20自載置台11上退避。於是，裝置停止，故而不會產生半導體晶片16於載置台11上持續地受到加熱之不良情形，可抑制半導體晶片16上之微凸塊18之氧化促進，不會產生微凸塊18之連接不良。
(第2實施形態)
第2實施形態係將半導體晶片16、或支持基板15搬送至載置台11上之後經過一定之設定時間後退避。
第2實施形態之半導體製造裝置1之控制系統具備與圖1相同之塊構成，但條件判定部2與退避控制部3之處理動作不同於第1實施形態。第2實施形態之條件判定部2進行以下處理：計測將半導體晶片16、或支持基板15搬送至載置台11上之後之經過時間；以及判定經過時間是否 為第1設定時間以上、或計測停留於載置台11上之累計時間，並判定累計時間(以下，記作載置台停滯累計時間)是否為第2設定時間以上。又，若判定為經過時間為第1設定時間以上，或載置台停滯累計時間為第2設定時間以上，第2實施形態之退避控制部3使安裝中途之半導體晶片群20退避。
圖4係表示第2實施形態之半導體製造裝置1之處理動作之流程圖。以下，以與圖3之流程圖之不同點為中心進行說明。首先，於緊隨特定動作之後開始時間計測(步驟S21)。特定動作係指將由搬送頭13搬送之第n層之半導體晶片16搬送至載置台11上、或將支持基板15搬送至載置台11上等。其次，判定特定動作後之經過時間是否為第1設定時間以上、或載置台停滯累計時間是否為第2設定時間以上(步驟22)。步驟S22中若判定為否，利用相機12識別第n層之半導體晶片16之對準標記19(步驟S23)。
其次，再次判定將第n層之半導體晶片16、或支持基板搬送至載置台11上之後之經過時間是否為第1設定時間以上、或載置台停滯累計時間是否為第2設定時間以上(步驟S24)。步驟S24中若判定為否，利用相機12識別由頭13搬送之第(n+1)層之半導體晶片16之對準標記19(步驟S25)。
其次，再次判定將第n層之半導體晶片16搬送至載置台11上之後之經過時間是否為第1設定時間以上、或載置台停滯累計時間是否為第2設定時間以上(步驟S26)。步驟S26中若判定為否，將第(n+1)層之半導體晶片16搬送至載置台11上且安裝於第n層之半導體晶片16之上(步驟S27)。其次，判定半導體晶片16之積層數是否達到事先預定之數k(步驟 S28)。若尚未達到，將n遞增1(步驟S29)，並重複進行步驟S21以後之處理。
步驟S22、S24或S26中若判定為是，則使用搬送單元14使安裝中途之半導體晶片群20退避(步驟S30)，使裝置停止(步驟S31)。
之後，判定是否重新開始安裝處理(步驟S32)。於不重新開始之情形時，使用搬送單元14將搬送中途之半導體晶片群20搬出(步驟S33)。於重新開始之情形時，計測構成安裝中途之半導體晶片群20之各半導體晶片16停留於載置台11上之累計時間，並判定累計時間是否為第2設定時間以內(步驟S34)。若為第2設定時間以內，則由搬送單元14將已退避之半導體晶片群20返回至退避前之位置(步驟S35)。若累計時間超出第2設定時間，轉移至步驟S33進行搬出處理。
如此，於第2實施形態中，若將各半導體晶片16、或支持基板15搬送至載置台11上之後經過時間為第1設定時間以上、或載置台停滯累計時間為第2設定時間以上，利用搬送單元14使安裝中途之半導體晶片群20退避，因此不會使安裝中途之半導體晶片群20較長時間地停留於載置台11上而導致半導體晶片16之微凸塊18過量地氧化，可防止微凸塊18之連接不良。
(第3實施形態)
第3實施形態係若進行安裝處理之裝置停止之後經過一定之設定時間，則使安裝中途之半導體晶片群20退避。
第3實施形態之半導體製造裝置1之控制系統具備與圖1相同之塊構成，但條件判定部2與退避控制部3之處理動作與第1實施形態不 同。第3實施形態之條件判定部2進行以下處理：計測進行安裝處理之裝置停止之後之經過時間；以及判定經過時間是否為第1設定時間以上、或載置台停滯累計時間是否為第2設定時間以上。又，若判定為經過時間為第1設定時間以上、或載置台停滯累計時間為第2設定時間以上，第3實施形態之退避控制部3使半導體晶片群20退避。
圖5係表示第3實施形態之半導體製造裝置1之處理動作之流程圖。以下，以與圖4之流程圖之不同點為中心進行說明。首先，判定進行安裝處理之裝置是否停止(步驟S41)。於此，與圖3之步驟S1同樣地藉由表示進行安裝處理之裝置停止之旗標之值而判定。於是，於步驟S41中判定為停止之時點，亦可能有裝置尚未停止之情形。
於步驟S41中若判定為未停止，其次利用相機12識別第n層之半導體晶片16之對準標記19(步驟S42)。其次，再次判定進行安裝處理之裝置是否停止(步驟S43)。若判定為未停止，其次利用相機12識別被頭13吸附而搬送之第(n+1)層之半導體晶片16(步驟S44)。其次，再次判定進行安裝處理之裝置是否停止(步驟S45)。若判定為未停止，其次將第(n+1)層之半導體晶片16搬送至載置台11上且安裝於第n層之半導體晶片16之上(步驟S46)。其次，判定半導體晶片16之積層數是否達到事先預定之數k(步驟S47)。若尚未達到，使n遞增1(步驟S48)，並重複進行步驟S41以後之處理。
步驟S41、S43或S45中若判定為裝置已停止，開始時間計測(步驟S49、S52、S55)。判定開始時間計測後之經過時間是否為第1設定時間以上、或載置台停滯累計時間是否為第2設定時間以上(步驟S50、S53、S56)。步驟S50、S53或S56中若判定為否，判定裝置是否已重新開 始動作(步驟S51、S54、S57)。於裝置不重新開始動作之情形時返回至步驟S50、S53或S56，於裝置已重新開始動作之情形時，前進至步驟S42、S44或S46。步驟S50、S53或S56中若判定為是，由搬送單元14使安裝中途之半導體晶片群20退避之後(步驟S58)，使裝置停止(步驟S59)。之後之處理(步驟S60~S63)與圖4之步驟S32~S35相同。
如此，第3實施形態中，於進行安裝處理之裝置停止之後之經過時間為第1設定時間以上、或載置台停滯累計時間為第2設定時間以上之情形時，由搬送單元14使安裝中途之半導體晶片群20退避，因此可防止於裝置停止之狀態下載置台11上半導體晶片16持續地受到加熱之不良情形。
(第4實施形態)
第4實施形態係於判定為停止安裝處理時檢測最後積層之半導體晶片16之搭載位置偏移之後，使安裝中途之半導體晶片群20退避。
第4實施形態之半導體製造裝置1之控制系統具備與圖1相同之塊構成，但條件判定部2之退避之處理動作與第1實施形態不同。第4實施形態之條件判定部2進行以下處理：檢測半導體晶片群20中之最後積層之半導體晶片16上之搭載座標、與其前一個積層之半導體晶片16上之基準座標之位置偏移量；以及判定所檢測之位置偏移量是否在特定範圍內。於判定為停止安裝處理之情形時，由條件判定部2檢測搭載位置偏移量之後，由退避控制部3使半導體晶片群20退避。進而，若檢測之位置偏移量超出特定範圍，進行特定之警告處理。
圖6係表示第4實施形態之半導體製造裝置1之處理動作之 流程圖。以下，以與圖5之流程圖之不同點為中心進行說明。首先，判定進行安裝處理之裝置是否停止(步驟S61)。若判定為未停止，使用相機12識別第n層之半導體晶片16之對準標記19，並將座標記憶於未圖示之記憶部(步驟S62)。對準標記19例如位於第n層之半導體晶片16之對角，其座標為(Xna，Yna)、(Xnb，Ynb)。將(Xna，Yna)、(Xnb，Ynb)之中心座標(Xn，Yn)作為基準座標而記憶於未圖示之記憶部。基準座標用於檢測與接下來要搭載之第(n+1)層之半導體晶片之位置偏移量。記憶部中記憶有對角之2點之座標與中心之基準座標之共計3點。
其次，再次判定進行安裝處理之裝置是否停止(步驟S63)。若判定為未停止，利用相機12識別第(n+1)層之半導體晶片16之對準標記19(步驟S64)。其次，再次判定進行安裝處理之裝置是否停止(步驟S65)。若判定為未停止，安裝第(n+1)層之半導體晶片16(步驟S66)。其次，再次判定進行安裝處理之裝置是否停止(步驟S67)。若判定為未停止，於安裝有第(n+1)層之半導體晶片16之對準標記19之狀態下使用相機12進行識別。將其等之座標記憶於未圖示之記憶部(步驟S68)。對準標記19例如位於第(n+1)層之半導體晶片16之對角，其座標為(Xn+1a，Yn+1a)、(Xn+1b，Yn+1b)。將(Xn+1a，Yn+1a)、(Xn+1b，Yn+1b)之中心座標(Xn+1，Yn+1)作為搭載座標而記憶於未圖示之記憶部。搭載座標用於檢查與第n層之半導體晶片16之位置偏移量。如此，搭載座標係位置偏移量之算出對象即最上層之半導體晶片16上之對角之2點之中心之座標。又，基準座標係成為算出位置偏移量之基準之半導體晶片16上之對角之2點之中心之座標。
其次，算出上述之基準座標與搭載座標之差即位置偏移 量，並判定位置偏移量是否在特定範圍內(步驟S69)。若位置偏移量為特定範圍內，判斷為滿足規格，並將步驟S68中所記憶之第(n+1)層之半導體晶片16上之2點之座標、以及其中心之搭載座標作為接下來要搭載之、例如成為搭載第(n+2)層之半導體晶片16時之基準之2點之座標、以及其中心之基準座標而記憶(步驟S70)。即，(Xna←Xn+1a，Yna←Yn+1a)、(Xnb←Xn+1b，Ynb←Yn+1b)、(Xn1←Xn+1，Yn←Yn+1)。
於此，位置偏移量可由(X，Y，θ)之資訊表示。其中，(X，Y)可藉由識別第n層與第(n+1)層之半導體晶片16上之2點，並將其等之中點彼此之座標加以比較且取得差而算出。又，θ偏移量根據將第n層與第(n+1)層之半導體晶片16之上述2點之對準標記連結之線段彼此之相交角度而算出即可。
其次，判定半導體晶片16之積層數是否達到事先預定之數k(步驟S71)。若尚未達到，使n遞增1(步驟S72)，並重複進行步驟S61以後之處理。
步驟S67中若判定為裝置已停止，於使安裝中途之半導體晶片群20退避之前，利用相機12識別第(n+1)層之半導體晶片16之對準標記19，並將座標記憶於未圖示之記憶部(步驟S73)。對準標記19例如位於第(n+1)層之半導體晶片16之對角，其座標為(Xn+1a，Yn+1a)、(Xn+1b，Yn+1b)。將(Xn+1a，Yn+1a)、(Xn+1b，Yn+1b)之中心座標(Xn+1，Yn+1)作為搭載座標而記憶。該步驟S73中，與步驟S68同樣地，算出第(n+1)層之半導體晶片16之搭載座標與第n層之半導體晶片16之基準座標之位置偏移量(X，Y)、以及根據將各半導體晶片16之2點之對準標記連結之線段彼此之相交角度算出之位置偏移量(θ)。於使半導體晶 片群20暫且退避之後即使返回至初始位置，亦因裝置之機械精度而使退避前後之半導體晶片群20之位置產生偏移。因此，於搭載第(n+1)層之半導體晶片16且算出位置偏移量之前半導體晶片群20退避，返回至初始位置且算出位置偏移量之情形時，算出退避前之第n層之基準座標與退避後之第(n+1)層之搭載座標之位置偏移，因此於搭載位置偏移檢測結果中產生相當於搬送偏移之量之誤差。
另一方面，於退避前算出位置偏移量之情形時，可不受搬送偏移之影響而算出位置偏移量。
其次，判定位置偏移量是否在特定範圍內(步驟S74)。於步驟S69或S74中，若判定為位置偏移量為特定範圍外，則由搬送單元14使安裝中途之半導體晶片群20退避(步驟S75)。之後，進行特定之警告處理，並且使裝置停止(步驟S76)。
於步驟S61、S63或S65中判定為裝置已停止之情形時，或於步驟S74中判定為位置偏移量為特定範圍內之情形時，由搬送單元14使安裝中途之半導體晶片群20退避(步驟S77)，使裝置停止(步驟S78)。之後，判定是否重新開始安裝處理(步驟S79)，於重新開始之情形時，進行使已退避之半導體晶片群20返回至退避前之位置之處理(步驟S80a)。於不重新開始之情形時，將半導體晶片群20搬出(步驟S80b)。
如此，第4實施形態中，於使安裝中途之半導體晶片群20退避之前，算出最後積層之半導體晶片16與其前一個積層之半導體晶片16之位置偏移量並記憶之後退避，因此於使半導體晶片群20退避後而返回至初始位置之後，可不受搬送偏移之影響而準確地進行位置偏移檢測，因此可繼續高精度地進行積層處理。又，第4實施形態中，若最後積層之 半導體晶片16上之搭載座標、與其前一個積層之半導體晶片16上之基準座標之位置偏移量(X，Y)、以及根據將各半導體晶片16之晶片之2點之對準標記連結之線段彼此之相交角度而算出之位置偏移量(θ)不在特定範圍內，使安裝中途之半導體晶片群20退避並進行警告處理，因此可迅速地檢測積層時之位置偏移，可抑制不良之產生。
(第5實施形態)
第5實施形態例如係以最下層之半導體晶片16上之對準標記19為基準而檢測位置偏移。
第5實施形態之半導體製造裝置1之控制系統具備與圖1相同之塊構成，但條件判定部2與退避控制部3之處理動作與第1實施形態不同。第5實施形態之條件判定部2進行以下處理：檢測所積層之m個半導體晶片16中之積層於第n層(n為1以上且未達m之整數)之半導體晶片16上之基準座標與積層於第m層之半導體晶片16上之搭載座標之位置偏移量(X，Y)、及根據將各半導體晶片16之2點之對準標記連結之線段彼此之相交角度而算出之位置偏移量(θ)；以及判定所檢測之位置偏移量是否在特定範圍內。又，於判定為停止安裝處理之情形時，第5實施形態中，由條件判定部2檢測搭載位置偏移量之後，由退避控制部3使半導體晶片群20退避。進而，若檢測之位置偏移量超出特定範圍，進行特定之警告處理。
圖7係表示第5實施形態之半導體製造裝置1之處理動作之流程圖。以下，以與圖6之流程圖之不同點為中心進行說明。首先，利用相機12識別第n(n為1以上之整數)層之半導體晶片16之對準標記19，且將對準標記19之座標記憶於未圖示之記憶部(步驟S81)。對準標記19例如位 於第n層之半導體晶片16之對角，其座標為(Xna，Yna)、(Xnb，Ynb)。將(Xna，Yna)、(Xnb，Ynb)之中心座標(Xn，Yn)作為基準座標n而記憶。
其次，識別第m層之半導體晶片16，且以基準座標n為基準進行安裝(步驟S82)。於此，1≦n≦m≦k，安裝第m層之半導體晶片16直至m=k(步驟S86)。對於每一層，利用相機12拍攝及識別半導體晶片16之對準標記19，之後進行裝置停止之判定處理，若裝置未停止，利用相機識別對準標記19，並重複進行安裝半導體晶片16之處理。
其次，判定進行安裝處理之裝置是否停止(步驟S83)。於裝置未停止之情形時，利用相機12識別第m層之半導體晶片16之對準標記19，將對準標記19之座標記憶於未圖示之記憶部，並算出與第n層之半導體晶片16之位置偏移量(步驟S84)。對準標記19例如位於第m層之半導體晶片16之對角，其座標為(Xma，Yma)、(Xmb，Ymb)。將(Xma，Yma)、(Xmb，Ymb)之中心座標(Xm，Ym)作為搭載座標m而記憶。
其次，判定位置偏移量是否在特定範圍內(步驟S85)。若在特定範圍內，則判定m是否與設定數k相等(步驟S86)。若m<k，則使m遞增1(步驟S87)，並重複進行步驟S82以後之處理。
步驟S83中若判定為裝置已停止，則利用第m層之半導體晶片16之相機12識別對準標記19，將該等對準標記19之座標記憶於未圖示之記憶部，並算出與第n層之半導體晶片16之位置偏移量(步驟S88)。該步驟S88中，與圖6之步驟S73同樣地，於使半導體晶片群20退避之前算出最上層之半導體晶片16之位置偏移量，因此可不受半導體晶片群20退避後之搬送偏移之影響而算出位置偏移。
其次，判定位置偏移量是否在特定範圍內(步驟S89)。步驟S85或S89中若判定為在特定範圍外，則由搬送單元14使安裝中途之半導體晶片群20退避(步驟S90)，進行特定之警告處理並且使裝置停止(步驟S91)。
步驟S89中若判定為在特定範圍內，則由搬送單元14使安裝中途之半導體晶片群20退避(步驟S92)，使裝置停止(步驟S93)。
其次，判定是否繼續進行安裝處理(步驟S94)，於不繼續進行安裝處理之情形時，由搬送單元14將安裝中途之半導體晶片群20搬出(步驟S95)。於繼續進行安裝處理之情形時，由搬送單元14使安裝中途之半導體晶片群20返回至退避前之位置(步驟S96)。其次，返回至初始位置之後利用相機12識別第m層之半導體晶片16之對準標記19，並記憶其等之座標(步驟S97)。對準標記19例如位於第m層之半導體晶片16之對角，其座標為(Xm'a，Ym'a)、(Xm’b，Ym'b)。將(Xm'a，Ym'a)、(Xm'b，Ym'b)之中心座標(Xm'，Ym')作為修正搭載座標m'而記憶。
其次，算出使半導體晶片群20返回至初始位置之後之第m層之半導體晶片16之座標(Xm'a，Ym'a)、(Xm'b，Ym'b)與退避前之半導體晶片16之座標(Xma，Yma)、(Xmb，Ymb)之搬送偏移量αa、及αb(步驟S98)。搬送偏移量分別為(Xαa=Xm'a-Xma，Yαa=Ym'a-Yma)、(Xαb=Xm'b-Xmb，Yαb=Ym'b-Ymb)。
其次，將載置台11上第n層之半導體晶片16之座標加上搬送偏移量αa、αb所得之座標記憶至未圖示之記憶部(步驟S99)。座標分別為(Xn'a=Xna+Xαa，Yn’a=Yna+Yαa)、(Xn'b=Xnb+Xαb，Yn'b=Ynb+Yαb)。將(Xn'a，Yn'a)、(Xn'b，Ynb')之中心座標(Xn'，Yn')作為 修正基準座標n'而記憶。
其次，將用於步驟S81~S88之處理之基準座標n替換為修正基準座標n'(步驟S100)。之後，進行步驟S86以後之處理。
如此，第5實施形態中，將積層半導體晶片群20時之基準座標例如設為最下層之半導體晶片16之對準標記19，因此即使將半導體晶片16積層為複數層，亦不會引起位置偏移量累積性地增加之不良。尤其第5實施形態中，於使積層中途之半導體晶片群20退避之後返回至初始位置時，算出最上層之半導體晶片16之搬送偏移量，並根據該搬送偏移量而修正最下層之半導體晶片16之基準座標，因此於返回至初始位置之後可不受搬送偏移之影響，將最下層之半導體晶片16作為基準而高精度地進行積層處理。
(第6實施形態)
第5實施形態中，於積層半導體晶片16時，例如算出與最下層之半導體晶片16之基準座標之位置偏移量，但最下層之半導體晶片16之對準標記19若於其上積層其他半導體晶片16，會由於其遮擋而無法利用相機12進行識別。因此，於使半導體晶片群20退避後返回至初始位置時，無法直接算出基準座標之搬送偏移量。因此，第6實施形態係於無法始終利用相機12識別之位置設置其他對準標記21。
第6實施形態之半導體製造裝置1之控制系統具備與圖1相同之塊構成，但條件判定部2與退避控制部3之處理動作與第1實施形態不同。第6實施形態之條件判定部2進行以下處理：檢測所積層之m個半導體晶片16中之最下層之半導體晶片16、或積層於第n層(n為1以上且未達m之 整數)之半導體晶片16上之基準座標與積層於第m層之半導體晶片16上之搭載座標之位置偏移量；以及判定所檢測之位置偏移量是否在特定範圍內。又，第6實施形態中，於由條件判定部2檢測搭載位置偏移量之後，由退避控制部3使半導體晶片群20退避。進而，若所檢測之位置偏移量超出特定範圍，進行特定之警告處理。
圖8A及圖8B係表示於第1層之半導體晶片16追加設置之對準標記21之圖。圖8A係自側方觀察積層於支持基板15上之半導體晶片群20之圖，圖8B係自上方觀察之圖。第1層之半導體晶片16具有較第2層以後之半導體晶片16更大之面積。上述對準標記21配置於與第2層以後之半導體晶片16於上下不重疊之位置。因此，如圖8A所示當於上方配置有相機12時，不拘導體晶片16之積層數，相機12始終能夠識別對準標記21。圖8B表示將該對準標記21設置於第1層之半導體晶片16之對角線上之2個部位之例，但對準標記21之配置部位未必係如圖8B之對角位置。
例如，圖9A~圖9D係表示對準標記21之配置部位之各種變化例之圖。圖9A表示使第1層之半導體晶片16具有與第2層以後之半導體晶片16相同之面積，但使第1層之半導體晶片於X方向上偏移，並將對準標記21設置於藉由偏移而與第2層以後之半導體晶片16於上下不重疊之2個部位之例。又，圖9B表示使第1層之半導體晶片16具有與第2層以後之半導體晶片16相同之面積，但使第1層之半導體晶片於X方向及Y方向上偏移，並將對準標記21設置於藉由偏移而與第2層以後之半導體晶片16於上下不重疊之2個部位之例。
圖9A與圖9B之任一情形均可如圖9C般，將相機12配置於上方時，不受第2層以後之半導體晶片16之影響而識別對準標記21。
或者亦可如圖9D，使第1層之半導體晶片16具有與第2層以後之半導體晶片16相同之面積，但使第1層之半導體晶片16之配置角度與第2層以後之半導體晶片16之配置角度不同。
又，上述對準標記21未必設置於第1層之半導體晶片16，亦可配置於支持複數層半導體晶片群20之支持基板15上。圖10A及圖10B表示於支持基板15上設置對準標記21之例。支持基板15支持半導體晶片群20，多數情形時較半導體晶片群20之設置面積大。於是，若將對準標記21配置於與支持基板15上之半導體晶片群20於上下不重疊之位置，可始終利用相機12識別對準標記21。
圖11係表示第6實施形態之半導體製造裝置1之處理動作之流程圖。以下，以與圖6之流程圖之不同點為中心進行說明。又，圖12A~圖12C係表示將半導體晶片16積層之狀況之圖。
首先，利用相機12識別最下層之半導體晶片16、或第n(n為1以上之整數)層之半導體晶片16之對準標記19，將其等之座標記憶於未圖示之記憶部(步驟S111)。對準標記19例如位於第n層之半導體晶片16之對角，其座標為(Xna1，Yna1)、(Xnb1，Ynb1)。將(Xna1，Yna1)、(Xnb1，Ynb1)之中心座標(Xn1，Yn1)設為基準座標n1而記憶。
其次，如圖12A所示，利用相機12識別最下層之半導體晶片16、或第n層之半導體晶片16、或設置於支持基板15之對準標記21，並將其等之座標記憶於未圖示之記憶部(步驟S112)。該對準標記21之座標例如位於第n層之半導體晶片16，其座標為(Xna2，Yna2)、(Xnb2，Xnb2)。將(Xna2，Yna2)、(Xnb2，Xnb2)之中心座標(Xn2，Yn2)作為基準座標n2而記憶。
其次，識別第m層之半導體晶片16，並以基準座標n1為基準而安裝(步驟S113)。於此，1≦n≦m≦k，安裝第m層之半導體晶片16直至m=k。更具體而言，如圖12B所示，使用所記憶之最下層之半導體晶片16之對準標記19之座標、與將自該積層之半導體晶片16之背面側之對準標記19利用相機12拍攝及識別之位置之座標而進行位置對準。之後進行裝置停止之判定處理，若裝置未停止，則利用相機12識別對準標記19，並重複進行安裝半導體晶片16之處理。
其次，判定進行安裝處理之裝置是否停止(步驟S114)。若判定為未停止，則利用相機12識別第m層之半導體晶片16之對準標記19，並將其等之座標記憶於未圖示之記憶部(步驟S115)。對準標記19例如位於第m層之半導體晶片16，其座標為(Xm1a，Ym1a)、(Xm1b，Ym1b)。將(Xm1a，Ym1a)、(Xm1b，Ym1b)之中心座標(Xm1，Ym1)作為搭載座標m1而記憶。
其次，判定位置偏移量是否在特定範圍內(步驟S116)。若在特定範圍內，則判定m是否與設定數k相等(步驟S117)。若m<k，則使m遞增1(步驟S118)，並重複進行步驟S113以後之處理。
步驟S114中若判定為裝置已停止，則利用相機12識別第m層之半導體晶片16之對準標記19，並將其等之座標(搭載座標m1)記憶於未圖示之記憶部(步驟S119)。又，該步驟S119中，與步驟S115同樣地算出位置偏移量。該步驟S119中，與圖6之步驟S73同樣地，於退避前算出最上層之半導體晶片16之位置偏移量，因此可不受搬送偏移之影響而算出位置偏移量。
其次，判定位置偏移量是否在特定範圍內(步驟S120)。步 驟S116或S120中若判定為不在特定範圍內，則由搬送單元14使安裝中途之半導體晶片群20與支持基板15一併退避(步驟S121)。之後，進行特定之警告處理，使進行安裝處理之裝置停止(步驟S122)。步驟S120中若判定為在特定範圍內，則由搬送單元14使安裝中途之半導體晶片群20退避(步驟S123)，使裝置停止(步驟S124)。
之後，判定是否繼續進行安裝處理(步驟S125)，於不繼續進行安裝處理之情形時，由搬送單元14將安裝中途之半導體晶片群20搬出(步驟S126)，結束處理。
若判定為繼續進行安裝處理，則由搬送單元14使安裝中途之半導體晶片群20返回至退避前之位置(步驟S127)。其次，如圖12C所示，識別最下層之半導體晶片16、或第n層之半導體晶片16、或支持基板15上之對準標記21，並將其等之座標記憶於未圖示之記憶部(步驟S128)。對準標記21例如位於最下層之半導體晶片16或支持基板15之對角，其座標為(Xn2'a，Yn2'a)、(Xn2'b，Yn2'b)。將(Xn2'a，Yn2'a)、(Xn2'b，Yn2'b)之中心座標(Xn2'，Yn2')作為基準座標n2'而記憶。
其次，算出使半導體晶片群20返回至初始位置之後之座標(Xn2'a，Yn2'a)、(Xn2'b，Yn2'b)與退避前之座標(Xn2a，Yn2a)、(Xn2b，Yn2b)之搬送偏移量αa、及αb(步驟S129)。搬送偏移量分別為(Xαa=Xn2'a-Xn2a，Yαa=Yn2'a-Yn2a)、(Xαb=Xn2'b-Xn2b，Yαb=Yn2'b-Yn2b)。
其次，將最下層之半導體晶片16、或載置台11上第n層之半導體晶片16之座標加上搬送偏移量αa、αb所得之座標記憶於未圖示之記憶部(步驟S130)。座標分別為(Xn1'a=Xn1a+Xαa，Yn1'a=Yn1a+ Yαa)，(Xn1'b=Xn1b+Xαb，Yn1'b=Yn1b+Yαb)。將(Xn1'a，Yn1'a)、(Xn1'b，Yn1'b)之中心座標(Xn1'，Yn1')作為修正基準座標n1'而記憶。
其次，將基準座標n1替換為修正基準座標n1'(步驟S131)，且進行步驟S117以後之處理。
如此，第6實施形態中，於最下層之半導體晶片16或支持基板15上，以不被所積層之半導體晶片群20遮蔽之方式配置對準標記21，且將該對準標記21之座標作為基準，算出使半導體晶片群20退避後返回至初始位置時之搬送偏移量。由此，可精度良好地檢測搬送偏移量，即使於退避後返回至初始位置繼續進行安裝處理之情形時，亦可不受搬送偏移之影響，將最下層之半導體晶片16作為基準而高精度地進行積層處理。
(第7實施形態)
於上述第1~第6實施形態中，對於支持基板15上積層複數個半導體晶片16之例進行了說明，但亦可應用於將預先積層有複數個半導體晶片16之積層體安裝於支持基板15上之情形、或於該積層體之上積層1個以上之半導體晶片16之情形。支持基板15可為具有配線之包含有機或無機材料之基板、以矽為材料之支持體、引線框架。又，亦可應用於將複數個半導體晶片16或積層體安裝於支持基板15或引線框架上所配置之黏著性之帶上之情形。
又，上述第1~第6實施形態中，說明了於支持基板15上僅安裝一個積層有複數個半導體晶片16之半導體晶片群20之例，亦可應用 於在支持基板15上安裝複數個半導體晶片群20之情形。該情形時之複數個半導體晶片群20之積層順序為任意。例如，可反覆進行以下工序：於一個半導體晶片群20之製作結束之後，於其他場所製作下一個半導體晶片群20(Z方向優先處理)。或者亦可反覆進行以下工序：於複數個部位依序安裝第n層之半導體晶片16之後，同樣於複數個場所依序積層第(n+1)層之半導體晶片16(XY方向優先處理)。
於上述第4~第6實施形態中，於採用XY方向優先處理之情形時，較理想為於由搬送單元14連同支持基板15一併退避之前，利用相機12識別所有最上層之半導體晶片16之對準標記19，並記憶其位置。
進而，第4~第6實施形態之圖6、圖7以及圖11之流程圖中，判定裝置是否停止，但亦可與圖4同樣地，判定於將半導體晶片16搬送至載置台11上之後之經過時間是否為第1設定時間以上、或載置台停滯累計時間是否為第2設定時間以上。
(第8實施形態)
對使用上述第6實施形態之半導體製造裝置1將積層有複數個半導體晶片之積層體封裝之處理順序更詳細地進行說明。圖13係說明第8實施形態之圖。
首先，如圖13A所示，準備配置於支持基板15上之最下層之半導體晶片16a。於該半導體晶片16a上，形成用以積層其他半導體晶片16b之電極墊17。對於電極墊17，使用Al、Cu、Au、Ni、Pd等單一成分、複合材、合金等。電極墊17上進而亦可形成金屬凸塊。作為金屬凸塊，使用Sn、Ag、Cu、Au、Bi、Zn、In等單一成分或其複合材、合金。
其次，如圖13B所示，於配置於第2層之半導體晶片16b上形成貫通半導體晶片16b之通道(開口部)。於半導體晶片16b上使用電漿裝置等形成開口部，且於該開口部形成SiO2或SiN等作為絕緣膜。該絕緣膜亦可為SiO2與SiN之積層膜。朝開口部形成包含金屬膜之通道接點22。對於通道接點22，例如使用Ti、Cr、Cu、Ni、Au、Pd、W等單一成分或複合材、合金，藉由蒸鍍、濺鍍、CVD(chemical vapor deposition，化學氣相沈積)等而形成。其次，將金屬膜作為晶種膜於開口部鍍覆金屬。作為鍍覆材料，亦可使用Cu、Ni、Pd、Au、Ag等，製成形成其複合材或合金之狀態。之後，對晶種膜進行蝕刻而形成墊。再者，於墊上形成金屬凸塊之情形時，亦可將Sn、Ag、Cu、Au、Bi、Zn、In等之1種、或複數種連續地進行鍍覆。
於半導體晶片16b之表面形成電極墊17。電極墊使用Al、Cu、Au、Ni、Pd等單一成分、複合膜、合金等。亦可於電極墊上進而形成金屬凸塊。作為金屬凸塊，使用Sn、Ag、Cu、Au、Bi、Zn、In等或其複合膜、合金。
其次，如圖13C所示，將半導體晶片16b搭載於半導體晶片16a上。如上所述，於半導體晶片16a上具有用以與半導體晶片16a電性連接之電極墊17或凸塊。又，亦可於搭載半導體晶片16b之面形成接著劑23。接著劑23可塗佈樹脂狀，亦可貼附膜狀。亦可塗佈樹脂並進行曝光、顯影而形成。以相同之方式，於半導體晶片16b之上積層半導體晶片16c，進而於半導體晶片16c之上依序積層半導體晶片16d而形成積層體20。
其次，如圖13D所示，將該積層體20顛倒而於基板24上進 行覆晶安裝。於基板24上形成焊料凸塊18。又，於該基板24上塗佈接著劑23。接著劑23可為樹脂狀，亦可為膜狀。亦可於積層體20上塗佈接著劑23。之後，將積層體20覆晶安裝於基板24。將形成於積層體20之墊17與基板上之焊料凸塊18位置對準並進行電性連接。亦可於積層體20之墊17上預先形成焊料凸塊18。
亦可將形成有焊料凸塊18之積層體20與基板之電極墊17進行位置對準而電性連接。
於覆晶安裝時提高工具之溫度，利用接著劑23使積層體20與基板24緊固。覆晶安裝時之溫度可上升至使焊料熔融之溫度，亦可為不熔融之溫度。
其次，將搭載有晶片積層體20之基板24投入至還原氣氛回焊爐中，將金屬凸塊18與電極墊17電性連接。於氫、甲酸等氣氛中進行回焊。氫或甲酸之濃度亦可使用氮等進行適當地稀釋。使溫度上升至焊料之熔融溫度而將半導體晶片間、以及晶片積層體與基板連接。此時亦可使用治具將基板固定以不使其活動。
其次，如圖13E所示，於晶片積層體24之各半導體晶片間與其周圍形成樹脂25。樹脂25可為模具樹脂，亦可為底部填充材。可向半導體晶片間及晶片積層體20與基板24間同時添加樹脂25，亦可分成若干次進行添加。
圖13C之最下層之半導體晶片16a亦可具有貫通半導體晶片16a之通道。又，亦可於半導體晶片16a上直接搭載積層體20。
於將最下層之半導體晶片16a自晶圓上切割時，可使其較積層於半導體晶片16a上之半導體晶片16b~16d稍大地偏移而切割。或於 自晶圓上切割時，亦可將最下層之半導體晶片16a設為基準尺寸，且使半導體晶片16b~16d較基準尺寸稍小而進行切割。或者，亦可將一邊尺寸較半導體晶片16b~16d長之晶片用作半導體晶片16a。或者，亦可將半導體晶片16a~16d之尺寸設為相同，僅使最下層之半導體晶片16a偏移而配置，由此將電極墊17以不被半導體晶片16b~16d遮蔽之方式積層。
形成於半導體晶片16b~16d之貫通通道可為自晶片表面側形成之前側面通道，亦可為自晶片背面側形成之後側面通道。
如此，按照圖13A~圖13E之工序製作之半導體裝置30具備n(n係2以上之整數)層之半導體晶片16，n層中第2層以後之半導體晶片16分別具有：用以與下一層之半導體晶片16連接之墊17、及用以與下一層之半導體晶片16進行位置對準之第1對準標記19，最下層之半導體晶片具有配置於與n層半導體晶片之積層體於上下不重疊之位置之第2對準標記21。
雖對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出者，並非意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍及主旨中，並且包含於申請專利範圍記載之發明及其均等範圍內。
[相關申請]
本案享有以日本專利申請案2018-53369號(申請日：2018年3月20日)作為基礎申請案之優先權。本案藉由參考該基礎申請案而包含基礎申請案之全部內容。

Claims (12)

  1. 一種半導體製造方法，其係於載置於載置台上之支持基板上安裝半導體晶片或半導體晶片之積層體，且其具備以下步驟：正在進行上述半導體晶片或上述積層體之安裝處理中，判定是否滿足特定之條件；於判定為滿足上述特定條件之情形時，使至該時為止已安裝於上述支持基板上之上述半導體晶片或上述積層體與上述支持基板一併退避；於上述退避後，判定是否重新開始上述半導體晶片或上述積層體之安裝處理；及當判定為重新開始上述安裝處理時，使上述已退避之上述半導體晶片或上述積層體返回至退避前之位置繼續進行上述安裝處理。
  2. 如請求項1之半導體製造方法，其中判定是否滿足上述特定條件之步驟係判定進行上述安裝處理之裝置是否停止，於判定為上述裝置已停止之情形時，上述退避之步驟使上述半導體晶片或上述積層體退避。
  3. 如請求項1之半導體製造方法，其中判定是否滿足上述特定條件之步驟具有以下步驟：計測將安裝上述半導體晶片或上述積層體之上述支持基板搬送至進行安裝處理之載置台上之後之經過時間、或安裝至上述載置台上之後之經過時間；及判定上述經過時間是否為第1設定時間以上；且若判定為上述經過時間為上述第1設定時間以上，則上述退避之步驟使上述半導體晶片或上述積層體退避。
  4. 如請求項1之半導體製造方法，其中判定是否滿足上述特定條件之步驟具有以下步驟：計測進行上述安裝處理之裝置停止之後之經過時間；及判定上述經過時間是否為第1設定時間以上；且若判定為上述經過時間為上述第1設定時間以上，則上述退避之步驟使上述半導體晶片或上述積層體退避。
  5. 如請求項3或4之半導體製造方法，其具備以下步驟：於判定為重新開始上述安裝處理之情形時，計測各個半導體晶片停留於上述載置台上之累計時間；及判定上述累計時間是否為第2設定時間以內；且若上述累計時間為上述第2設定時間以內，則繼續上述安裝處理之步驟使上述半導體晶片或上述積層體返回至退避前之位置繼續進行上述安裝處理，若上述累計時間超出上述第2設定時間，則將上述半導體晶片或上述積層體搬出。
  6. 如請求項1至4中任一項之半導體製造方法，其中上述半導體晶片或上述積層體具有包含所積層之複數個上述半導體晶片之半導體晶片群；上述半導體製造方法具備以下步驟：檢測所積層之複數個上述半導體晶片中之最後積層之半導體晶片上之搭載座標與前一個積層之半導體晶片上之基準座標之位置偏移量；及判定上述檢測出之位置偏移量是否在特定範圍內；且於判定為進行上述安裝處理之裝置停止之情形時，上述退避之步驟係於檢測出上述位置偏移量之後使上述半導體晶片群退避，若上述檢測出之位置偏移量超出上述特定範圍，則於檢測出上述位置偏移量之後使上述半導體晶片群退避，並且進行特定之警告處理。
  7. 如請求項1至4中任一項之半導體製造方法，其中上述半導體晶片或上述積層體具有包含所積層之m個(m係2以上之整數)半導體晶片之半導體晶片群；上述半導體製造方法具備以下步驟：檢測上述積層之m個半導體晶片中之積層於第n層(n係1以上且未達m之整數)之半導體晶片上之基準座標與積層於第m層之半導體晶片上之搭載座標之位置偏移量；及判定上述檢測出之位置偏移量是否在特定範圍內；且於判定為進行上述安裝處理之裝置停止之情形時，上述退避之步驟係於檢測出上述位置偏移量之後使上述半導體晶片群退避，若上述檢測出之位置偏移量超出上述特定範圍，則使上述半導體晶片群退避，並且進行特定之警告處理。
  8. 如請求項7之半導體製造方法，其中繼續進行上述安裝處理之步驟係：檢測上述退避前之積層於上述第m層之半導體晶片上之搭載座標與上述退避後已返回至退避前之位置之積層於上述第m層之半導體晶片上之搭載座標之搬送偏移量，並根據上述搬送偏移量而修正積層於上述第n層之半導體晶片上之上述基準座標，一邊檢測修正後之上述基準座標與積層於第(m+1)層以後之半導體晶片上之搭載座標之位置偏移量，一邊根據上述已修正之基準座標積層第(m+1)層以後之半導體晶片。
  9. 如請求項1至4中任一項之半導體製造方法，其中上述半導體晶片或上述積層體具有包含所積層之m個(m係2以上之整數)半導體晶片之半導體晶片群，於上述載置台上支持上述半導體晶片或上述積層體中最下層之半導體晶片之支持基板、或上述最下層之半導體晶片具有第1基準指標，該第1基準指標設置於能夠於上述半導體晶片群之積層中自上述支持基板之上方辨識之位置，上述最下層之半導體晶片具有第2基準指標，該第2基準指標設置於無法於上述半導體晶片群之積層中自上述支持基板之上方辨識之位置；上述半導體製造方法具備以下步驟：檢測上述第1基準指標及上述第2基準指標之座標；檢測積層於上述第m層之半導體晶片上之搭載座標與基於上述第2基準指標之基準座標之位置偏移量；及判定上述檢測出之位置偏移量是否在特定範圍內；且於判定為進行上述安裝處理之裝置停止之情形時，上述退避之步驟係於檢測出上述位置偏移量之後使上述半導體晶片群退避，若上述檢測出之位置偏移量超出上述特定範圍，則使上述半導體晶片群退避，並且進行特定之警告處理。
  10. 如請求項9之半導體製造方法，其中檢測上述位置偏移量之步驟係：於上述退避後繼續進行上述安裝處理時，檢測上述退避前之上述第1基準指標之位置與上述退避後返回至原來之位置之後之上述第1基準指標之位置之搬送偏移量，並根據上述搬送偏移量而修正上述基準座標，檢測上述已修正之基準座標與積層於第(m+1)層以後之半導體晶片上之搭載座標之位置偏移量。
  11. 一種半導體製造裝置，其於載置台上一邊將複數個半導體晶片進行位置對準一邊依序積層，且具備：條件判定部，其於上述複數個半導體晶片之安裝處理之中途，判定是否滿足特定之條件；退避控制部，其於判定為滿足上述特定條件之情形時，使至該時為止已積層之半導體晶片群退避；重新開始判定部，其於判定為滿足上述特定條件之後，判定是否重新開始上述安裝處理；及回復控制部，其於判定為重新開始上述安裝處理時，使上述已退避之半導體晶片群返回至退避前之位置繼續進行上述安裝處理。
  12. 一種半導體裝置，其具備n(n係2以上之整數)層半導體晶片，上述n層中之第2層以後之半導體晶片分別具有：墊，其用以與下一層之半導體晶片進行連接；及第1對準標記，其用以與下一層之半導體晶片進行位置對準；且上述n層中之最下層之半導體晶片具有第2對準標記，該第2對準標記配置於與上述n層半導體晶片之積層體於上下不重疊之位置。
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