CN106531648A - 半导体装置的制造方法及安装装置 - Google Patents

半导体装置的制造方法及安装装置 Download PDF

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CN106531648A
CN106531648A CN201610240001.2A CN201610240001A CN106531648A CN 106531648 A CN106531648 A CN 106531648A CN 201610240001 A CN201610240001 A CN 201610240001A CN 106531648 A CN106531648 A CN 106531648A
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semiconductor chip
engaging head
chip
semiconductor
lamination
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CN106531648B (zh
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深山真哉
小牟田直幸
渡部博
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Kioxia Corp
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Toshiba Corp
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Abstract

本发明的实施方式提供一种能够使积层所得的半导体芯片间的连接可靠性提升的半导体装置的制造方法及安装装置。根据实施方式，在间隙运算部(7D)，基于接合头(2)的Z坐标(Z1、Z2)及半导体芯片(P2)的芯片厚度(T)，运算半导体芯片(P1、P2)间的Z轴方向的间隙(G)，且在间隙(G)为规格范围内的情形时，使安装装置持续运转，在间隙(G)为规格范围以外的情形时，使安装装置报警停止。

Description

半导体装置的制造方法及安装装置
[相关申请案]
本申请享有以日本专利申请2015-177482号(申请日：2015年9月9日)为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置的制造方法及安装装置。
背景技术
在半导体装置中，存在为削减安装面积，而将半导体芯片积层的情形。存在半导体芯片间的连接使用微凸块的情形。
发明内容
本发明的实施方式提供一种能够使积层所得的半导体芯片间的连接可靠性提升的半导体装置的制造方法及安装装置。
实施方式的制造方法是将利用接合头拾取的第2半导体芯片积层在第1半导体芯片上，且基于积层所述第2半导体芯片积层时的所述接合头的垂直坐标，运算所述第1半导体芯片与所述第2半导体芯片的垂直方向的间隙。
附图说明
图1是表示第1实施方式的安装装置的概略构成的立体图。
图2(a)～(c)是表示第2实施方式的半导体装置的制造方法的剖视图。
图3是表示第2实施方式的半导体装置的制造方法的流程图。
图4是表示第2实施方式的半导体芯片的安装方法的流程图。
图5是表示第3实施方式的半导体装置的制造方法的流程图。
图6(a)及(b)是表示第4实施方式的安装装置的概略构成的立体图。
图7是表示第5实施方式的半导体装置的制造方法的流程图。
图8(a)～(c)是表示第6实施方式的半导体装置的制造方法的剖视图。
具体实施方式
以下参照随附附图，详细地说明实施方式的半导体装置的制造方法及安装装置。另外，本发明并非被该等实施方式限定。
(第1实施方式)
图1是表示第1实施方式的安装装置的概略构成的立体图。
图1中，在安装装置，设置有接合台1、接合头2、垂直活动体3、水平活动体4、晶片载置台6及控制装置7。在接合台1，置放有安装衬底K及半导体芯片P1、P2。接合台1可沿着水平方向(沿X轴方向及视需要沿Y轴方向)移动。接合头2是拾取半导体芯片P1、P2。垂直活动体3可使接合头1沿垂直方向(Z轴方向)移动。垂直活动体3是由水平活动体4支撑。水平活动体4可在接合台1与晶片载置台6之间沿水平方向(Y轴方向)移动。水平活动体4以可沿水平方向移动的方式，由导轨5支撑在接合台1及接合头2上。晶片载置台6是保持晶片W。此时，晶片W被单片化为半导体芯片P1、P2。
在控制装置7，设置有保持控制部7A、水平控制部7B、垂直控制部7C、间隙运算部7D、负载控制部7E及温度控制部7F。保持控制部7A是控制接合头2对半导体芯片P1、P2的拾取。水平控制部7B是控制接合台1及水平活动体4的水平位置。垂直控制部7C是控制接合头2的垂直坐标。间隙运算部7D是基于将半导体芯片P1、P2积层时的接合头2的垂直坐标(Z坐标)，运算半导体芯片P1、P2间的垂直方向的间隙。在接合头2的Z坐标的测量中，例如作为使用滚珠丝杠与电机使垂直活动体3沿Z轴方向移动的方法，可使用测量该电机的旋转角的旋转编码器。接着，可通过将由旋转编码器所测量的旋转角转换为Z轴方向的移动量，而测量接合头2的Z坐标。或者，在为使垂直活动体3沿Z轴方向移动，而使用线性导轨及线性电机的情形时，例如，也可以通过将激光位移计等固定地安装在水平活动体4，且对垂直活动体3的上表面照射激光光线，而测量接合头2的Z坐标。
负载控制部7E是控制将半导体芯片P1、P2积层时半导体芯片P1、P2所受到的负载。此时，可在接合头2，设置测量半导体芯片P1、P2所受到的负载的负载传感器。温度控制部7F是控制将半导体芯片P1、P2积层时半导体芯片P1、P2的温度。此时，在接合台1及接合头2，可分别设置将接合台1及接合头2加热的加热器。而且，可在接合台1及接合头2，分别设置测量接合台1及接合头2的温度的温度传感器。
(第2实施方式)
图2(a)～图2(c)是表示第2实施方式的半导体装置的制造方法的剖视图。
图2(a)～图2(c)中，在安装衬底K上设置有表面电极C0。在半导体芯片P1的背面侧设置有背面电极A1，且在半导体芯片P1的表面侧设置有表面电极C1。在背面电极A1上设置有凸块电极B1。在半导体芯片P2的背面侧设置有背面电极A2，在半导体芯片P2的表面侧设置有表面电极C2。在背面电极A2上设置有凸块电极B2。凸块电极B1、B2的间距可设定为10～100μm左右。凸块电极B1、B2的直径可设定为5～50μm左右。另外，安装衬底K可使用例如多层印刷布线板。在半导体芯片P1、P2，形成有晶体管等器件。该器件既可为NAND闪速存储器，也可以是逻辑电路，或者也可为处理器。安装衬底K的基材可使用例如BT(BismaleimideTriazine，双马来酰亚胺三嗪)树脂等。表面电极C0的材料可使用Cu等。也可以在表面电极C0中自阻焊剂露出的部分形成Au覆膜。背面电极A1、A2及表面电极C1、C2的材料既可为Au、Cu、Ni、Sn、Pg、Ag等的单层膜，也可以是积层膜。凸块电极B1、B2的材料可使用焊料等。
例如，作为表面电极C1、C2及背面电极A1、A2的材料，可使用Ni。此时，在Ni下，也可以是使用Ti的势垒金属膜。在该Ni上、也可以是Au覆膜。作为凸块电极B2的材料，可使用Sn。在该Sn下，作为基底层也可以是Cu。
接着，如图2(a)所示，在接合台1上置放安装衬底K。接着，通过将水平活动体4移动至晶片载置台6上，且使垂直活动体3下降，而使接合头2接触于半导体芯片P1。接着，利用接合头2拾取半导体芯片P1之后，将水平活动体4移动至接合台1上。接着，使接合台1沿水平方向移动之后，进行半导体芯片P1与安装衬底K的XY坐标的位置对准，且使垂直活动体3下降，由此，将半导体芯片P1配置在安装衬底K上。接着，在隔着接合头2对半导体芯片P1施加负载的状态下将半导体芯片P1加热。此时，凸块电极B1熔融而与表面电极C0接合。此后，通过隔着接合头2将半导体芯片P1冷却而使凸块电极B1固化。接着，通过使接合头2上升而使接合头2自半导体芯片P1分离。此处，在凸块电极B1与表面电极C0接合时测量接合头2的Z坐标Z1，且将该Z坐标Z1存储于控制装置7。该Z坐标Z1的测量既可在凸块电极B1熔融时进行，也可以在凸块电极B1熔融后的固化时进行。
其次，通过将水平活动体4移动至晶片载置台6上，且使垂直活动体3下降，而使接合头2接触于半导体芯片P2。接着，利用接合头2拾取半导体芯片P2之后，将水平活动体4移动至接合台1上。接着，使接合台1沿水平方向移动之后，在半导体芯片P1、P2间进行XY坐标的位置对准，如图2(b)所示，通过使垂直活动体3下降，而将半导体芯片P2配置在半导体芯片P1上。接着，如图2(c)所示，在隔着接合头2对半导体芯片P2施加负载的状态下将半导体芯片P2加热。此时，凸块电极B2熔融而与表面电极C1接合。例如，凸块电极B2中使用Sn且表面电极C1中使用Ni的情形时，在凸块电极B2与表面电极C1接合时形成Ni-Sn合金。此后，通过隔着接合头2将半导体芯片P2冷却，将凸块电极B2固化。接着，通过使接合头2上升而使接合头2自半导体芯片P2分离。此处，在凸块电极B2与表面电极C1接合时测量接合头2的Z坐标Z2，且将该Z坐标Z2存储在控制装置7中。该Z坐标Z2的测量既可在凸块电极B2熔融时进行，也可以在凸块电极B2熔融后的固化时进行。此时，在控制装置7中，载入半导体芯片P2的芯片厚度T的数据。该数据既可为设计数据，也可以是半导体芯片P2加工时所取得的加工数据。该加工数据例如可使用利用CMP(Chemical Mechanical Polishing，化学机械抛光)将晶片W薄膜化时的晶片W的芯片厚度数据。
接着，在间隙运算部7D中，基于接合头2的Z坐标Z1、Z2及半导体芯片P2的芯片厚度T，运算半导体芯片P1、P2间的Z轴方向的间隙G。此时，可利用G＝Z2－Z1－T赋予。判定间隙G是否为规格范围内，且在间隙G为规格范围以外的情形时，使图1的安装装置报警停止。另外，因在间隙G的运算时获取Z坐标Z1、Z2的差值，故Z坐标Z1、Z2的原点位于何处均可。而且，接合头2的Z坐标Z1、Z2若与接合头2一体地沿Z轴方向移动，则可在任何部分进行测量。例如，既可测量接合头2的Z坐标，也可以测量垂直活动体3的Z坐标。
此处，在将半导体芯片P2安装在半导体芯片P1上时，能够通过运算半导体芯片P1、P2间的间隙G，而管理凸块电极B2的接触状态，从而减少凸块电极B2的接触不良。此时，半导体芯片P1、P2间的间隙G会因凸块电极B2的材料或尺寸等的不均或半导体芯片P2所受到的负载等而变化。例如，若凸块电极B2的尺寸不均变大，则存在半导体芯片P1、P2间的间隙G变大，从而产生凸块电极B2的接触不良的情形。而且，若半导体芯片P2所受到的负载变小，则存在半导体芯片P1、P2间的间隙G变大，从而产生凸块电极B2的接触不良的情形。而且，若半导体芯片P2所受到的负载变大，则存在半导体芯片P1、P2间的间隙G变小，从而邻接的凸块电极B2间产生短路的情形。而且，若凸块电极B2的材料的不均变大，则凸块电极B2的熔点不均也变大，从而半导体芯片P1、P2间的间隙G变小，故存在邻接的凸块电极B2间产生短路的情况。因此，在间隙G为规格范围以外的情形时，可通过使图1的安装装置报警停止，而减少半导体芯片P2的安装不良。
积层在安装衬底K上的半导体芯片P1、P2可适用于例如SiP(SysteminPackage，系统级封装)。为获得半导体芯片P1、P2间的电连接，既可以在各半导体芯片P1、P2形成贯穿电极，也可以使用接合线。
图3是表示第2实施方式的半导体装置的制造方法的流程图。
在图3中，预先输入半导体芯片的芯片厚度T的设计数据(S1)。接着，安装利用接合头2拾取的本次的半导体芯片(S2)。此时，存储接合头2的Z坐标Z1作为基准坐标。接着，确认半导体芯片的积层阶数(S3)，在积层阶数为特定阶数的情形时，使安装结束。另一方面，在积层阶数不足的情形时，利用接合头2拾取下一个半导体芯片(S4)，且将该半导体芯片的芯片厚度T的设计数据读入至间隙运算部7D(S5)。接着，将利用接合头2所拾取的上层的半导体芯片安装在下层的半导体芯片上(S6)。此时，存储接合头2的Z坐标Z2。接着，基于接合头2的Z坐标Z1、Z2及半导体芯片的芯片厚度T，运算积层所得的半导体芯片间的间隙G(S7)。此时，在间隙G为规格范围以外的情形时，使图1的安装装置报警停止(S8)。另一方面，在间隙G为规格范围内的情形时，将基准坐标自Z1重写为Z2(S9)，且返回至S3。接着，直至半导体芯片的积层阶数达到特定阶数之前，重复进行S3～S9的处理。
图4是表示第2实施方式的半导体芯片的安装方法的流程图。另外，图4的步骤可用于图3的S2及S6。
在图4中，若使利用接合头2所拾取的半导体芯片移动至接合台1上，则进行半导体芯片的XY坐标的位置对准(S51)。接着，通过使接合头2下降(S52)，而将上层的半导体芯片配置在下层的半导体芯片上。接着，在隔着接合头2对半导体芯片施加负载的状态下将半导体芯片加热(S53、S54)。此时，隔着凸块电极将上层的半导体芯片接合于下层的半导体芯片。此时，可存储接合头2的Z坐标。此后，通过隔着接合头2将半导体芯片冷却，而使凸块电极固化(S55)。另外，也可以存储凸块电极已熔融时的接合头2的Z坐标，但也可以存储凸块电极已被固化时的接合头2的Z坐标。接着，通过使接合头2上升而使接合头2自半导体芯片分离(S56)。
(第3实施方式)
图5是表示第3实施方式的半导体装置的制造方法的流程图。
在图5中，该流程设置S1'而取代图3的S1。其他则与图3的流程相同。在S1中，输入芯片厚度T的设计数据，但在S1'中，读取晶片W的芯片厚度T的加工数据。接着，在S7的间隙G的运算中，使用加工数据而取代芯片厚度T的设计数据。由此，在间隙G的运算时，可反映出晶片加工时的制造不均所造成的芯片厚度T的误差，从而可使间隙G的运算精度提升。
(第4实施方式)
图6(a)及图6(b)是表示第4实施方式的安装装置的概略构成的立体图。
在图6(a)及图6(b)的安装装置中，设置控制装置7'而取代图1的控制装置7。在控制装置7'中，将芯片厚度测定部7G追加至控制装置7中。芯片厚度测定部7G进行激光位移计8对芯片厚度T的测量控制。而且，在图6(a)及图6(b)的安装装置中，对于图1的安装装置追加激光位移计8。激光位移计8可通过自半导体芯片P2的上下对半导体芯片P2照射激光，而测量半导体芯片P2的芯片厚度T。
接着，如图6(a)所示，在安装衬底K上积层半导体芯片P1之后，利用接合头2拾取半导体芯片P2。接着，通过将半导体芯片P2利用激光位移计8夹着，自半导体芯片P2之上下照射激光，而实测半导体芯片P2的芯片厚度T。接着，如图6(b)所示，使利用接合头2所拾取的半导体芯片P2移动至接合台1上。接着，在半导体芯片P1、P2间进行XY坐标的位置对准后，将半导体芯片P2积层在半导体芯片P1上。此处，在安装衬底K上积层半导体芯片P1时，存储接合头2的Z坐标Z1。而且，在将半导体芯片P2积层在半导体芯片P1上时，存储接合头2的Z坐标Z2。接着，在间隙运算部7D中，基于接合头2的Z坐标Z1、Z2及半导体芯片P2的芯片厚度T的实测数据，运算半导体芯片P1、P2间的间隙G。
此处，可通过将芯片厚度T的实测数据用于间隙G的运算，而反映出半导体芯片P1、P2间的芯片厚度T的不均，从而使间隙G的运算精度提升。
(第5实施方式)
图7是表示第5实施方式的半导体装置的制造方法的流程图。
在图7中，该流程设置S10、S11而取代图3的S1。其他则与图3的流程相同。S10是在安装本次的半导体芯片之前，利用接合头2拾取本次的半导体芯片。S11是在利用接合头2拾取下一次的半导体芯片之后，实测该半导体芯片的芯片厚度T。接着，在S7的间隙G的运算中，使用实测数据而取代芯片厚度T的设计数据。
(第6实施方式)
图8(a)～图8(c)是表示第6实施方式的半导体装置的制造方法的剖视图。
在图8(a)～图8(c)的构成中，对于半导体芯片P1、P2分别追加间隔物SA1、SA2。间隔物SA1可确保安装衬底K与半导体芯片P1的间隔。间隔物SA2可确保半导体芯片P1、P2间的间隔。间隔物SA1、SA2的材料可使用未达凸块电极B1、B2的熔融温度且具有粘着性的绝缘性树脂。例如，间隔物SA1、SA2的材料可使用环氧树脂、聚酰亚胺树脂、丙烯酸树脂、酚醛树脂或苯并环丁烯树脂等。
接着，如图8(a)所示，将利用接合头2所拾取的半导体芯片P1积层在安装衬底K上。此时，半导体芯片P1是利用间隔物SA1固定在安装衬底K上。而且，存储接合头2的Z坐标Z1。此时，使凸块电极B1避免熔融，且将凸块电极B1与表面电极C0维持为未接合的状态。
接着，如图8(b)所示，利用接合头2拾取半导体芯片P2。接着，通过使接合头2下降至半导体芯片P1上，而如图8(c)所示，将半导体芯片P2积层在半导体芯片P1上。而且，存储接合头2的Z坐标Z2。此时，使凸块电极B2避免熔融，从而可将凸块电极B1、B2维持为彼此未接合的状态。接着，基于接合头2的Z坐标Z1、Z2及半导体芯片P2的芯片厚度T，运算半导体芯片P1、P2间的间隙G。接着，在间隙G为规格范围内的情形时，使安装装置的运转持续，且在间隙G为规格范围以外的情形时，使安装装置报警停止。若半导体芯片P1、P2的积层阶数达到特定阶数，则通过使该等半导体芯片P1、P2的凸块电极B1、B2一次地熔融而将各凸块电极B1、B2接合。
此处，可通过在半导体芯片P1、P2设置间隔物SA1、SA2，而无需使各凸块电极B1、B2接合，便将半导体芯片P1、P2固定。因此，无需将各半导体芯片P1、P2每积层1层便进行回流焊，从而无需将各半导体芯片P1、P2每积层1层便重复进行温度的升降，故能够使产率提升，并且减少各半导体芯片P1、P2所受到的热应力。
对本发明的若干个实施方式进行了说明，但该等实施方式是作为示例而提示，且并非意图限定发明的范围。该等新颖的实施方式能够以其他各种方式实施，且在不脱离发明主旨的范围内，可进行各种省略、置换、变更。该等实施方式或其变化包含于发明的范围或主旨中，并且包含于专利申请的范围中记载的发明及其均等的范围中。
[符号说明]
1 接合台
2 接合头
3 垂直活动体
4 水平活动体
5 导轨
6 晶片载置台
K 安装衬底
P1、P2 半导体芯片
7 控制装置
7A 保持控制部
7B 水平控制部
7C 垂直控制部
7D 间隙运算部
7E 负载控制部
7F 温度控制部

Claims (5)

1.一种半导体装置的制造方法，其特征在于：
将利用接合头所拾取的第2半导体芯片积层在第1半导体芯片上，
基于将所述第2半导体芯片积层时的所述接合头的垂直坐标，运算所述第1半导体芯片与所述第2半导体芯片的垂直方向的间隙。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于：判定所述间隙是否为规格范围内，且
在所述间隙为规格范围以外的情形时，停止第3半导体芯片向所述第2半导体芯片上的积层。
3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：所述间隙是若将所述间隙设为G，将所述第2半导体芯片积层在所述第1半导体芯片上之前的所述接合头的垂直坐标设为Z1，将所述第2半导体芯片积层在所述第1半导体芯片上之后的所述接合头的垂直坐标设为Z2，且将所述第2半导体芯片的芯片厚度设为T，则以G＝Z2－Z1－T赋予。
4.根据权利要求3所述的半导体装置的制造方法，其特征在于：当拾取将所述第2半导体芯片积层在所述第1半导体芯片上之前的所述第2半导体芯片时，测量所述第2半导体芯片的芯片厚度。
5.一种安装装置，其特征在于具备：
接合台，被置放半导体芯片；
接合头，拾取所述半导体芯片；
垂直活动体，使所述接合头沿垂直方向移动；
垂直控制部，控制所述接合头的垂直坐标；及
间隙运算部，基于积层所述半导体芯片时的所述接合头的垂直坐标，运算所述半导体芯片间的垂直方向的间隙。
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