CN102473591A - 互连封装结构及制造和使用该互连封装结构的方法 - Google Patents

互连封装结构及制造和使用该互连封装结构的方法 Download PDF

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CN102473591A
CN102473591A CN2010800313203A CN201080031320A CN102473591A CN 102473591 A CN102473591 A CN 102473591A CN 2010800313203 A CN2010800313203 A CN 2010800313203A CN 201080031320 A CN201080031320 A CN 201080031320A CN 102473591 A CN102473591 A CN 102473591A
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substrate
pad
projection
package structure
interconnect package
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CN102473591B (zh
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尼泰史·卡玛怀特
艾博黑沙克·查德胡瑞
温科·桑德锐曼
罗·R·特玛拉
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Georgia Tech Research Corp
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Georgia Tech Research Corp
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Abstract

本发明的各种实施方式提供了细节距，芯片至基底互连封装结构，以及制造和实用该封装结构的方法。该封装结构通常包括一具有设置于其上的晶粒焊盘和凸块的半导体，及具有设置于其上的基底焊盘的基底。该凸块被配置为在凸块与基底焊盘接触时使半导体的至少一部分与基底的至少一部分电性互连。另外，在凸块与基底焊盘接触时，凸块的至少一部分和基底焊盘的至少一部分发生变形以在二者之间形成一非冶金结合。

Description

互连封装结构及制造和使用该互连封装结构的方法
技术领域
本发明的各种实施例主要涉及细节距，芯片至基底互连结构，以及制造和使用细节距、芯片至基底互连结构的方法，其中，芯片至基底互连结构利用凸块互连实现。
背景技术
在实现小型封装的持续推动作用下，芯片至基底互连装置已从传统的基于焊接的连接技术得到了进一步的发展。由于微电子系统的发展趋势为实现多功能且要减小尺寸，所以电气系统的小型化要求具有更广阔的前景，需要将无源器件和有源装置集成于一单一的微米级和纳米级的平台上。“系统级封装”(SOP)技术实现了前述的目标，因为，该种技术使电气系统规模化，以系统被认知的方式允许模式的转变，并为以新颖的互连方案实现超小型化设定了方向。
例如，一种该种互连方案涉及利用“倒装芯片”技术实现芯片至基底互连装配。通常，焊料凸块设置于芯片的有源表面上，随后将该芯片倒置以使该焊料凸块可与基底焊盘连接。然而，互连在几何学上的物理约束成为减小凸块节距或增大密度及获得高可靠性的障碍。另外，电迁移问题和金属间化合物构成提出了另外需要关注的问题。一些互连封装结构已发展为可获得超细节距，例如，焊盘至焊盘的金邦定(bonding)及凸块至焊盘的镍邦定。焊盘至焊盘的金邦定消除了以上提到的焊料凸块的缺陷，但邦定的实施成本相对较高。另外，凸块至焊盘的镍邦定无法在低的邦定温度下进行。因此，对于本领域，需要一种可兼容倒装芯片技术，比金互连成本低，及具有处理增大输入/输出(I/O)密度的能力的芯片至基底互连封装结构。
发明内容
本发明的一些实施方式提供了细节距，芯片至基底互连封装结构，其他实施例提供了制造细节距，芯片至基底互连封装结构的方法。最后，本发明的一些实施方式提供了使用细节距，芯片至基底互连封装结构的方法。
根据本发明的一些实施方式，一互连封装结构可包括一半导体，一设置于该半导体的一表面的至少一部分上的导电晶粒焊盘，及设置于该晶粒焊盘的至少一部分上的导电凸块。另外，该互连封装结构可包括一基底和一设置于该基底的一表面的至少一部分上的导电基底焊盘。该凸块可被配置为在该凸块与该基底焊盘接触时使该半导体的至少一部分与该基底的至少一部分电性互连。在凸块与基底焊盘接触时，该凸块的至少一部分和该基底焊盘的至少一部分可发生实质变形以在二者之间形成非冶金邦定。在一些实施例中，该种非冶金结合是压力接触结合。
该互连封装结构还可包括一设置于基底和基底焊盘之间的电介质层。在该种实施例中，该电介质层的至少一部分在凸块与基底焊盘接触时至少局部地发生变形是可能的。
该互连封装结构还可包括一设置于该凸块和基底焊盘之间的中间邦定层。
该凸块的至少部分的变形和基底焊盘的至少部分的变形可形成自一外加的至少约300兆帕的压强。
该互连封装结构也可包括一设置于该凸块和该基底焊盘间的非反应型粘结剂，其中，该非反应型粘结剂被配置为用于加强该非冶金邦定。在一些实施例中，该非反应型粘结剂可由非导电性膜制成。在另外的实施例中，该非反应型粘结剂可由各项异性导电材料制成。
在一些实施例中，该晶粒焊盘，凸块，及/或基底焊盘可由铜，Cu，制成。这可实现半导体与有机基底，无机基底或其他半导体间的互连。
在设置至少两个凸块的情况下，一个凸块和与之邻近的凸块间的距离可小于或者等于约30微米。在一些实施例中，每个凸块均和与各自邻近的凸块间的距离小于或者等于约30微米。
根据本发明的一些实施方式，制造一互连封装结构的方法包括提供一半导体，该半导体包括一设置于该半导体的一表面的至少一部分上的导电晶粒焊盘和一设置于该晶粒焊盘的至少一部分上的导电凸块。该方法还可包括提供一基底，该基底包括一设置于该基底的一表面的至少一部分上的导电基底焊盘。另外，该方法还可包括使该导电凸块与该导电基底焊盘接触。该方法也可包括使该凸块的至少一部分和该基底焊盘的至少一部分发生实质
应当注意的是，该基底焊盘可设置于作为基底的该表面的一电介质层上。在该种实施例中，该电介质层的至少一部分可在该变形步骤期间发生变形。
该变形步骤可包括施加一至少约300兆帕的压强。
该方法还可包括在该凸块和基底焊盘间设置一非反应型粘结剂，该非反应型粘结剂被配置为用于加强该非冶金结合。在设置至少两个凸块的情况下，一个凸块和与之邻近的凸块间的距离可小于或者等于约30微米。在一些实施例中，每个凸块和与之邻近的凸块间的距离均小于或者等于约30微米。
根据本发明的一些实施方式的另外的互连封装结构，可包括一半导体，一设置于该半导体的一表面的至少一部分上的铜晶粒焊盘，以及一设置于该铜晶粒焊盘的至少一部分上的铜凸块。该互连封装结构也可包括一基底和一设置于该基底的一表面的至少一部分上的铜基底焊盘。该互连封装结构也可包括一非反应型粘结剂。在该互连封装结构内部，该铜凸块可被配置为在该铜凸块与该铜基底焊盘接触时使该半导体的至少一部分与该基底的至少一部分电性互连。在铜凸块与铜基底焊盘接触时，该凸块的至少一部分和该基底焊盘的至少一部分可发生充分变形以在二者之间形成非冶金结合。该种非冶金结合可通过非反应型粘结剂加强。
本领域的普通技术人员可通过阅读以下细节性说明，参照附图给出的本发明的实施例更清楚地了解本发明的其他方面和特征。虽然，本发明的一些特征可能是针对特定的实施方式和附图进行讨论，但本发明的所有实施方式均可包括在该种应用中讨论的至少一个特征。虽然，可能在具有特定有利的特征的情况下讨论至少一种实施方式，但也可将至少一个该种特征与在该种应用中讨论的本发明的其他各种实施方式结合使用。以相似的方式，虽然一些实施例是在系统或者方法实施方式下进行讨论，但应当清楚的是，该种实施例也可在各种装置，系统和方法中实施。从而，在某一实施方式中讨论的某一特征并没有限制其他实施方式使用和包括同样的特征。
附图说明
图1示出了根据本发明一些实施方式的半导体、晶粒焊盘和凸块。
图2示出了根据本发明一些实施方式的芯片至基底互连封装结构。
图3为根据本发明一些实施方式的芯片至基底互连封装结构的扫描电子显微镜(SEM)图像。
图4示出了制造根据本发明一些实施方式的芯片至基底封装结构的方法。
图5为根据本发明一些实施方式的互连封装结构的横截面示意图。
图6示出了说明根据本发明一些实施方式的开尔文探针和菊链结构的晶粒(左)和基底(右)的设计。
图7示出了根据本发明一些实施方式的说明菊链结构的基底设计。
图8为根据本发明一些实施方式的晶粒和基底的SEM图像。
图9示出了根据本发明一些实施方式的说明菊链和中心阵列结构的晶粒(左)和基底(右)设计。
图10示出了根据本发明一些实施方式的具有不同节距的晶粒和基底。
图11为根据本发明一些实施方式的四个基本共面的铜凸块的SEM图像。
图12的图表给出了根据本发明一些实施方式的设置在给定晶粒上的38个随机测量的凸块的高度值。
图13的图表给出了根据本发明一些实施方式的在对互连封装结构进行超过2200次热循环的热循环测试期间的各菊链电阻值。
图14提供了根据本发明一些实施方式的互连菊链在完成超过2000次热循环后的横截面的SEM图像，图14还提供了显示与本发明一些实施方式相对应的铜凸块和铜基底焊盘间互连结构的插图。
图15的图表给出了根据本发明一些实施方式的在互连封装结构完成超过1825次热循环的热循环测试期间的各菊链的电阻值。
图16(a)提供了根据本发明一些实施方式的在完成约1995次热循环后菊链的失效部分的横截面的SEM图像。
图16(b)提供了根据本发明一些实施方式的实现由图16(a)中的圆形区标记的互连结构的铜凸块和铜基底焊盘的交界面的SEM图像。
图17的图表给出了根据本发明一些实施方式的使互连封装结构经历约1180次热循环的热循环测试期间的各菊链的电阻值。
图18示出了互连封装结构的制造步骤，其中，晶粒设置于基底内的凹孔中，图中示出了工具头和非导电性填充物的浓度根据基底的表面粗糙度进行调整。
图19的图表给出了根据本发明一些实施方式的在互连封装结构经历约955次热循环的热循环测试期间的各菊链的电阻值。
图20(a)提供了根据本发明一些实施方式的在施加约7千克(约220MPa)的载荷后，铜焊盘上的铜凸块的横截面的SEM图像。
图20(b)提供了根据本发明一些实施方式的在施加约9.5千克(约300MPa)的载荷后，铜焊盘上的铜凸块的横截面的SEM图像。
图21的图表给出了根据本发明一些实施方式的在互连封装结构经历约500次热循环的热循环测试期间的各菊链的电阻值。
具体实施方式
现参照附图，对本发明的实施例进行详细说明，其中，在所有附图中，用相似的参考标记表示相似的部件。在整篇说明书中，可能为各种元件确定了特定的数值或者参数，但这些数值或者参数只是作为实施例提供。事实上，该实施例并不意于限制本发明的各方面和概念，因为本发明可以各种适当的参数、尺寸、范围及/或数值实施。术语“第一”、“第二”、“主要的”、“次要的”、“顶部”、“底部”、“末端”、“近端”等并不代表任何顺序、数量或者重要性，仅是用于区分不同的元件。另外，术语“一”和“该”并不代表对数量的限制，仅说明所涉及的术语出现了“至少一次”。
本发明的各种实施方式涉及用于在半导体和基底间实现互连的改进的细节距、芯片至基底互连结构。特别是通过使凸块和与其相对应的基底焊盘发生变形而在半导体和基底间形成非冶金结合，而且可选择利用非反应型粘结剂加强这种非冶金结合。在此也将说明其制造方法。
在此说明的用于形成互连的凸块可由各种金属或者合金制成。如果选用一种金属，该凸块可由铜，Cu、铝，Al、银，Ag、镍，Ni、铅，Pb、钯Pd，和铂，Pt制成，也可由其他金属制成；如果选用合金，该凸块可由锡银、锡金、锡银金或者其他类似的合金制成。由于铜具有极好的导电性、力学稳定性和相对低的成本，因此，在一些示例性的实施例中，凸块由铜制成。另外，由于大部分制造半导体的工厂现在都配备有先进的铜电镀系统，因此，易于将铜凸块互连结构的制造集成至整个工艺中，从而使铜凸块互连结构的制造保持相对低的成本。
现参照图1，图1示出了半导体101，按照与在此公开的技术内容相关的技术领域的技术人员的理解，半导体101可涉及晶粒、集成电路(IC)、晶圆、微电路、微芯片、硅片、半导体芯片或者芯片。在一些示例性的实施例中，半导体101由硅，Si，制成。在一些实施例中，对硅半导体101的表面进行了氧化，以加强邦定特性。在另外的实施例中，可利用玻璃代替硅半导体。
可将一个或者多个晶粒焊盘102设置于半导体101的被氧化的或者未被氧化的表面上。为了便于说明，图1中仅示出了一个晶粒焊盘102，但应当理解的是，半导体101可具有设置于其上的若干个晶粒焊盘102。晶粒焊盘102可由铝、铜、钛或者合金，或者包含至少一种上述物质的混合物制成。许多其他导电金属或者导电金属合金或导电金属混合物也可用于制造晶粒焊盘102。
可在每个晶粒焊盘102上设置至少一个凸块103。根据上述说明，凸块103可由许多金属材料制成。凸块103也可由保护涂层包覆。然而，重要的是凸块103具有可在小于或者等于约300兆帕(MPa)的压强的作用下发生变形的适当特性，以及可承受高达约300至约400摄氏度(℃)的特性。凸块103可采用多种形状，在一些实施例中，将凸块103设计为圆柱形，并具有椭圆形的头部。当设置至少一个凸块103时，使每个凸块103与其他凸块103共面是有利的。
半导体101、晶粒焊盘102和凸块103通常构成芯片封装结构100，芯片封装结构100可被“倒置”在基底204上，使凸块103面向基底204，图2对此给出了较详细的说明。按照与在此公开的技术内容相关的技术领域的技术人员的理解，“基底”也可指印制电路板(PCB)、印刷线路板(PWB)、蚀刻线路板、印刷电路组件或印刷电路板组件。基底204可由有机或无机材料制成。基底204的表面上还可设置电介质层202，电介质层202用于防止短路，并保证芯片至基底封装结构200的整体刚性。电介质层202可由本领域技术人员所知道的任何适于在该种装置中使用的电介质材料制成。例如，较软的电介质材料(具有低杨氏模量的材料)可能允许发生较大的变形，从而提高可靠性，但即使对其他无法轻易发生变形的电介质材料，也可通过调整压力保证可靠性，使焊盘在电介质层不发生变形的情况下仍然产生变形。
可在电介质层202上设置至少一个基底焊盘或走线201。芯片封装结构100以凸块103面向基底204并与基底焊盘201接触的方式倒置。各基底焊盘201可与一个或者多个凸块103相对应，以提高电连接性。基底焊盘201可由多种材料制成，重要的是制作材料要使基底焊盘201与凸块103之间充分导电。在一些示例性的实施例中，基底焊盘201的材质与凸块103的材质相同。凸块103和相对应的基底焊盘201通过接触彼此电连接。在芯片至基底封装结构200上施加压力将至少引起凸块103和基底焊盘201发生变形，因此，形成非冶金接触或连接，也就是凸块103与基底焊盘201间形成压力接触结合。
如果需要，也可利用局部的冶金邦定加强凸块103和基底焊盘201间的连接。在该种实施例中，通过设置于凸块103和基底焊盘201间的中间邦定层形成局部的冶金邦定，该中间邦定层可以是凸块、焊盘，或者粘结剂的一部分。在此，当实施局部的冶金邦定时，凸块103和基底焊盘201间的相互作用将不仅是物理上的压力接触。
在一些实施例中，可利用粘结剂203加强凸块103与基底焊盘201间的相互作用。在凸块103与基底焊盘201接触之前，例如是可将厚度为约3至约5微米(μm)的粘结剂203设置于基底焊盘201的表面上。粘结剂203可由非导电性绝缘膜(NCF)制成，非导电性绝缘膜例如但不局限于是聚合物材料。粘结剂203也可由各向异性导电材料制成。粘结剂203优选是由与该装置或封装结构的其他组件不发生反应的材料制成。可通过添加例如是粘合增进剂、缓蚀剂和降低粘结剂吸水能力的固化剂等添加剂优化粘结剂203的粘结性能。在优选的实施例中，粘结剂203具有约2千兆帕(GPa)的储能模量，约115℃的玻璃化转变温度，以及在约65ppm/℃至约70ppm/℃间的热膨胀系数。可通过加热粘结剂203获得凝胶状结构，使凸块103可穿透粘结剂与基底焊盘201电连接。
晶粒焊盘102、凸块103和基底焊盘201共同形成了互连结构。互连结构的高度可变，在一些示例性实施例中，互连结构的高度为约20μm。互连结构适于将半导体101的至少一部分和基底204的至少一部分相互电连接。
制造芯片至基底封装结构200的方法大致可包括制作半导体101，制作基底204，以及将二者通过凸块103互连，使二者彼此电连接。由于本领域技术人员熟知半导体和基底的制作工艺，因此，在此不再进行详细的说明。在一些实施方式中，通过将硅芯片封装在玻璃基底上制成半导体，透过玻璃基底能从背面观察被封装的芯片，这样，以30μm的节距封装的芯片可获得高排列精确度。在另外的实施方式中，使半导体101的表面氧化。随后，可将一个或者多个晶粒焊盘102设置于半导体101的被氧化或者未被氧化的表面上，继而可将一个或者多个凸块103设置于一个或者多个晶粒焊盘102的表面上。在各种实施方式中，凸块103由铜制成，且这些凸块103基本是共面的。利用镀铜工艺可实现凸块103的共面性。晶粒焊盘102和凸块103可通过以下方式制成，即使他们的总高度为约13.1μm，标准差为0.45μm。
可在封装半导体101、晶粒焊盘102和凸块103之前、之后或者同时，准备基底204。在一些实施方式中，电介质层202可作为基底204的上表面。在该种实施例中，可将基底焊盘201设置于电介质层202的表面上。当电介质层202并不作为基底204的上表面使用时，可将基底焊盘201直接设置于基底204本身的上表面上。可将一薄层受热粘结剂203设置于基底焊盘201上。随后，可将包括半导体101、晶粒焊盘102和凸块103的芯片封装结构100“倒置”于基底204上，使凸块103穿透粘结剂203且和与之相对应的基底焊盘201相接触。可在形成的芯片至基底封装结构200上施加约300MPa的压强，以至少使凸块103和基底焊盘201发生实质变形。这种变形在半导体103和基底204之间形成了非冶金压力接触结合。芯片至基底封装结构200的其他组件也可在所施加压力的作用下发生变形。例如，在一些实施例中，电介质层202可在该压强的作用下至少局部地发生变形。这种压力接触结合使粘结剂203分散并充满半导体101和基底204间的空白空间，进而加强了二者间的结合。如果需要，可随后将粘结剂203硬化。
图4示例性地给出了一互连的封装流程。在这些实施方式中，在制造芯片至基底封装结构200的过程中，利用FINETECH 
Figure BDA0000130130720000091
的封装工具保证排列精度(例如达到约±1μm的精度)。晶粒在设置于基底上时发生倾斜的问题可利用具有框架的工具头处理，其允许在封装期间进行预调平和自动调平。芯片结合于有机基底的表面上及/或结合于有机基底的凹孔中的封装工艺可以是相同的。有机基底可与NCF在约90℃的温度下预先结合约15秒，随后冷却至室温并移除NCF衬垫。可控制NCF的结合于有机基底的凹孔内的尺寸，以避免NCF在凹孔内过度流动，NCF的过度流动将使其越过凹孔壁向外溢出。随后可使半导体或晶粒与基底对准，并在将基底预加热至约85℃使NCF的粘度降低后，将半导体或晶粒放置于基底上。最后，使晶粒和基底在约180℃的温度下承受预先确定的载荷/压力约30秒。施加于3毫米(mm)×3毫米mm晶粒尺寸上的载荷约为21牛顿(N)，转换为作用于凸块表面上的接触压强为300MPa。若基于所有凸块的有效横截面积计算施加于7mm×7mm晶粒尺寸上的载荷，接触压强仍然约为300MPa。
实施例
在以下的实施例中，制作了多种互连封装结构。给出多种互连设计是为了系统地学习不同晶粒尺寸和厚度间互连的可靠性。通过在特定有机基底中嵌入晶粒也可评估互连性能，即令具有不同厚度的倒装晶粒与有机基底互连，该有机基底的表面或者不具有凹孔或者具有凹孔。
图5示出了这些实施例中每个实施例的互连封装结构的总体结构。通常，采用标准半加成工艺(SAP)制成晶粒。通过在厚度为约400埃
Figure BDA0000130130720000092
的钛，Ti，层上电镀铜形成厚度为约1μm至约2μm的晶粒焊盘层。随后将高度为约12μm的铜凸块图形化并电镀于晶粒焊盘上。通过电化学镍金(ENIG)技术在铜凸块的表面形成镍和金涂层。铜凸块形成于厚度为约500μm的晶圆上，除了厚度为约500μm的晶圆，使一些晶圆变薄至厚度为约55μm。在下面说明的一些实施例中，在将该种晶粒嵌入凹孔内之前，利用厚度为约55μm的晶粒完成该种晶粒的处理和封装工艺。
基底由一有机，超高布线密度、积层基底材料制成，该有机，超高布线密度、积层基底材料用于实现具有约30μm的节距的芯片至基底互连。这种有机基底包括低损耗薄芯薄基板和低介电常数/低损耗积层电介质。基底上的焊盘和走线也通过ENIG技术形成保护涂层。
实施例1：设计和制造芯片至基底互连封装结构
在该实施例中，该装置被设计为可获得单凸块电阻和菊链电阻数据，为了便于说明，该装置被称为“TV1”。该装置针对3mm×3mm的晶粒设计，且互连布图外周具有360个围绕晶粒的凸块。该设计包括4个开尔文测试结构和8个菊链，每个菊链具有32个凸块。图6示出了开尔文测试结构(KP)和菊链(DC)在晶粒中的位置和基底设计。晶粒设计也包括排列和方位基准。
基底被设计为用于探测菊链中的每8个凸块。基底的尺寸为约25mm×约25mm，并且其表面上无凹孔。如图6所示，每个角上各四个共十六个探针焊盘用于进行四端探针测试，每边各十个共四十个探针焊盘设计为进行菊链测试。
实施例2：设计和制造芯片至基底互连封装结构
在该实施例中，该装置被设计为在将薄晶粒嵌入至有机基底中后测试互连的可靠性，为了便于说明，该装置被称为“TV2”。TV2是针对具有216个外围凸块的约3mm×约3mm晶粒的设计。由于该试验车的物理公差相对TV1更严格，因此，节距可放宽至约50μm。如图7中基底的设计快照所示，该设计包括4个开尔文测试结构和3个全菊链和2个半菊链。
该基底被设计为用于探测各菊链。基底的尺寸为约12mm×约12mm，且基底的表面上形成有凹孔。该凹孔壁与晶粒边缘间的间隙为约400μm。凹孔的尺寸根据芯片尺寸及各种误差确定，所需考虑的误差诸如是芯片尺寸误差、凹孔工艺误差和在封装期间产生的芯片放置误差。图7示出了凹孔壁边缘邻近焊盘的基底设计。
为了形成用于嵌入晶粒的凹孔，可有三种不同的选择，即：光刻、等离子体刻蚀和激光打孔。对于等离子体刻蚀样品，通过在金属化层上层压一厚度为约60μm的集结电介质层并利用CO2激光器打出凹孔的方法在基底的表面上形成凹孔，凹孔的尺寸略大于晶粒的尺寸。额外的积层电介质层的厚度以确保晶粒的顶面基本与积层电介质层的表面位于同一水平面上为准。在封装之前，要对凹孔的底面进行清理，通过等离子体去除任何在激光打孔工艺中累积的残渣并保证铜焊盘表面的清洁。利用CF4/O2/N2等离子体在约100℃的温度下作用约5分钟完成清洁工序。在厚度为约60μm的积层材料上提供通向下方的探针焊盘的开口。如图8的样品的横截面的扫描电子显微镜(SEM)图像所示，晶粒以完全包含于凹孔内的方式封装于凹孔的内部。
实施例3：设计和制作芯片至基底互连封装结构
在该实施例中，装置被设计为用于评估较大晶粒上的铜互连的可靠性，为了便于说明，该装置被称为“TV3”。该实施例采用的晶粒尺寸为约7mm×约7mm，晶粒的厚度为约550μm。晶粒设计为包括537个凸块，这些凸块以约50μm的节距排列在晶粒的外周。约10×约10个凸块以200μm的节距(在两个方向上)排列形成的方阵也被加在晶粒的中心。该设计被分为沿晶粒边缘布置的3个全菊链和2个半菊链。基底被设计为用于探测各菊链及位于中心的凸块阵列。基底的尺寸为约12mm×约12mm。如图9的基底快照所示，该设计能够从2个极端探测外围菊链和中心凸块的整个阵列。基底的表面没有生成凹孔。
为了便于理解，图10给出了TV1、TV2和TV3样品的示意图及相关尺寸。
实施例4：铜凸块的共面性分析
在该实施例中，利用从同一晶圆上随机选取的三个晶粒评价晶粒凸块的共面性，并在晶粒的所有四个边缘的位置上随机选取38个读物。图11示出了一晶粒上的共面的铜凸块的具有代表性的SEM图像。图12的图表给出了分析结果。研究中的大多数铜凸块的总高度(包括晶粒边上的焊盘)接近保持在13.1μm，标准差为0.45μm。从而，达到了铜凸块要基本共面的要求。
实施例5：互连封装的可靠性
在该实施例中，测试实施例1至3制作的样品的可靠性。特别地，利用JEDEC工业标准JESD22-A104C(条件B)中给出的热循环测试(TCT)对样品TV1，TV2，TV3进行分析。封装结构在大气环境下承受温度范围在约-55℃至约125℃的循环热负荷，各极限温度的保持时间为约15分钟。为了与工业中的标准可靠性测试程序保持一致性，所有样品在进行任何可靠性测试之前均按照IPC/JEDEC J-STD-020A联合标准进行预处理(precon)。这包括在约125℃的温度下烘烤样品约24个小时，样品在烘烤之前需要进行如下操作：先在约60℃的温度下承受湿度敏感等级3(MSL-3)和承受约60％的相对湿度(RH)约40个小时，以及进行随后的3次回流焊峰值温度为约260℃的回流焊。
在预处理之前和之后利用c型超声波扫描显微镜(C-SAM)密切监测封装结构进行比较。在热循环测试期间周期性地获取各菊链电阻的测量值。
现讨论TV1样品的稳定性。图10中给出了TV1的两种结构。这些样品特别是厚度为约550μm和约55μm的晶粒封装于相似有机基底上的封装结构，以测试他们在TCT下的性能。在每完成约100次循环后记录菊链电阻值。以下将讨论两种结构的结果。
首先，说明具有厚度为550μm的晶粒的TV1封装结构。所有这些样品的菊链电阻值在完成约1500次循环的过程中发生的变化可忽略不计。超过1500次循环，一些样品在不同点处的菊链电阻值开始在测试中增大。对所有样品进行热循环直至其失效，以调查其失效的方式。在此，利用SEM采集失效菊链的横截面的图像进行失效分析。例如，根据图13的图表所示，菊链电阻值到完成1500次循环时发生的改变可忽略不计，到完成约2300次循环时有微量的增加。
图14包括铜至铜互连结构在完成2000次循环后的菊链的横截面的具有代表性的SEM图像。图14的插图中示出了具有代表性的铜凸块/铜焊盘互连结构。
应当注意的是，如图15所示，一些样品在完成约1800次循环后表现为菊链电阻值显著增加，这表明连接断开。采用SEM调查这些样品的失效方式。图16(a)示出了失效菊链的具有代表性的SEM图像。如图16(b)所示，菊链的失效原因为铜凸块与铜焊盘发生了分离。
现说明具有厚度为55μm的晶粒的TV1样品。具有变薄晶粒的封装结构也要承受超过1000次的TCT循环测试。图17的图表示出了TCT结果。应当注意的是，这些结果并不包括以下这些菊链的数据，即在TCT开始时由于晶粒存在缺陷而无法在封装期间进行电连接的菊链。变薄晶粒的封装工艺要确保将约300MPa的载荷施加于铜凸块上时不会损坏晶粒本身。可靠性结果证实了针对厚度为约55μm的晶粒的封装工艺的可实施性。
现讨论TV2样品的可靠性。封装工艺对于这些样品来说是有挑战性的，因为，晶粒要完全嵌入基底表面上的凹孔内。实现高可靠性封装的一个关键点在于确保在铜凸块上施加的载荷等于在先前针对晶粒封装于基底的表面上的情况下施加于铜凸块上的载荷。另一个问题是确保具有足够厚度的NCF，以完全填充晶粒与基底间的空隙。该种封装工艺采用恰当的工具头放置晶粒并采用更厚的NCF的定制实施，从而解释了凹孔的底座因激光打孔变的粗糙，请参见图18。
在工艺得到发展后，如图19所示，样品在进行约1000次热循环下展现了稳定的菊链电阻值。C-SAM图像证实了NCF在晶粒和基底之间均匀流动，且在工艺改进后没有观察到气隙。
现讨论TV3样品的可靠性。根据先前的监测，这些样品相对较小的(即约3mm×约3mm)晶粒，铜凸块与焊盘的接触面积较大。由此，需要施加更大的载荷，使凸块和焊盘发生充分变形。在考虑凸块与焊盘的总接触表面的情况下计算得到适当的载荷。根据图20的SEM图像所示，在增大载荷后可观察到更大的变形。具体地讲，图20(a)中的局部互连的凸块和焊盘承受约220MPa的载荷，而图20(b)中的互连的凸块和焊盘承受约300MPa的载荷。
施加了较大载荷的封装结构在可靠性方面显示出了明显的改进。如图21的图表所示，在完成约500次循环的过程中，菊链呈现出稳定的接触阻值。
这些实施例表明了本发明的互连封装结构的制作和效果。这种技术使超细节距和低姿态(low profile)成为可能，进而可实现高I/O密度、低邦定温度、可维修性、可测试性和易于与现有的加工工厂整合。概括地说，利用NCF在约160℃的温度下使硅晶粒上的铜凸块与有机基底上的铜焊盘结合。晶粒可被封装于有机基底的表面上和凹孔内。样品被设计为具有约30至50μm的节距，以获取单凸块电阻，NCF的绝缘电阻和菊链电阻。TCT结果巩固了这些互连结构的优良的可靠性。厚晶粒和薄晶粒封装结构均在热循环中获得了良好的结果，并在测试期间保持稳定的接触电阻。具有尺寸为约7mm×约7mm的较大晶粒的封装结构经历了大于500次的热循环。这些针对大晶粒的初始结果表明，这些互连结构可适用于具有高I/O数量的较大晶粒。铜凸块和焊盘在所施加的载荷下发生的变形产生了优良的可靠性。
本发明的实施例并不局限于在此公开的特定的配方、工艺步骤和材料，该种配方、工艺步骤和材料可进行一定程度的变化。再者，在此应用的技术仅是为了说明实施例，并不意于限制所能应用的技术，本发明的各种实施方式的保护范围仅由所附的权利要求的技术方案及与之等同的技术方案限定。例如，尺寸、温度和压力参数可根据所使用的特定材料改变。
虽然此次公开的实施方式已参照特定的实施例进行了详细的说明，但本领域的技术人员应当清楚，可在所附的权利要求定义的范围内进行变形和修饰。相应地，本发明各种实施方式的保护范围应当并不局限于上面讨论的实施方式，应当仅由随后的权利要求的技术方案和与之等同的技术方案定义。

Claims (20)

1.一种互连封装结构，包括：
一半导体；
一晶粒焊盘，该晶粒焊盘设置于该半导体的一表面的至少一部分上，其中，该晶粒焊盘由一导电材料制成；
一凸块，该凸块设置于该晶粒焊盘的至少一部分上，其中，该凸块由一导电材料制成；
一基底；以及，
一基底焊盘，该基底焊盘设置于该基底的一表面的至少一部分上，其中，该基底焊盘由导电材料制成；
其中，该凸块配置为在该凸块与该基底焊盘接触时使该半导体的至少一部分与该基底的至少一部分电性互连；
其中，在该凸块与该基底焊盘接触时，凸块的至少一部分和基底焊盘的至少一部分发生实质变形以在二者之间形成一非冶金结合。
2.根据权利要求1的互连封装结构，其中，该非冶金结合是压力接触结合。
3.根据权利要求1的互连封装结构，还包括一电介质层，该电介质层设置于该基底和该基底焊盘之间。
4.根据权利要求3的互连封装结构，其中，该电介质层的至少一部分在该凸块与该基底焊盘接触时至少局部地发生变形。
5.根据权利要求1的互连封装结构，还包括一中间邦定层，该中间邦定层设置于该凸块和基底焊盘之间。
6.根据权利要求1的互连封装结构，其中，该凸块的至少部分的充分变形和基底焊盘的至少部分的实质变形形成自所施加的至少约300兆帕的压强。
7.根据权利要求1的互连封装结构，还包括一设置于该凸块和该基底焊盘间的非反应型粘结剂，其中，该非反应型粘结剂被配置为用于加强该非冶金结合。
8.根据权利要求7的互连封装结构，其中，该非反应型粘结剂由非导电性绝缘膜制成。
9.根据权利要求7的互连封装结构，其中，该非反应型粘结剂由各项异性导电材料制成。
10.根据权利要求1的互连封装结构，其中，该凸块由铜制成。
11.根据权利要求1的互连封装结构，其中，该基底焊盘由铜制成。
12.根据权利要求1的互连封装结构，其中，该基底由有机材料制成。
13.根据权利要求1的互连封装结构，其中，该凸块和与之邻近的凸块间的距离小于或者等于约30微米。
14.一种制造互连封装结构的方法，该方法包括：
提供一半导体，该半导体包括一导电晶粒焊盘和一导电凸块，该导电晶粒焊盘设置于该半导体的一表面的至少一部分上，该导电凸块设置于该晶粒焊盘的至少一部分上；
提供一基底，该基底包括一导电基底焊盘，该导电基底焊盘设置于该基底的一表面的至少一部分上；以及，
使该导电凸块与该导电基底焊盘接触；以及，
使该凸块的至少一部分和该基底焊盘的至少一部分发生实质变形以在二者之间形成一非冶金结合。
15.根据权利要求14的制造互连封装结构的方法，其中，将该基底焊盘设置在形成于该基底的表面上的一电介质层上。
16.根据权利要求15的制造互连封装结构的方法，其中，该电介质层的至少一部分在该变形期间发生变形。
17.根据权利要求14的制造互连封装结构的方法，其中，该变形包括施加一至少约300兆帕的压强。
18.根据权利要求14的制造互连封装结构的方法，其中，还包括在该凸块和基底焊盘间设置一非反应型粘结剂的步骤，其中，该非反应型粘结剂被配置为用于加强该非冶金结合。
19.根据权利要求14的制造互连封装结构的方法，其中，使该凸块和与之邻近的凸块间的距离小于或者等于约30微米。
20.一种互连封装结构，包括：
一半导体；
一铜晶粒焊盘，该铜晶粒焊盘设置于该半导体的一表面的至少一部分上；
一铜凸块，该铜凸块设置于该铜晶粒焊盘的至少一部分上；
一基底；
一铜基底焊盘，该铜基底焊盘设置于该基底的一表面的至少一部分上；
一非反应型粘结剂；
其中，该铜凸块被配置为在该铜凸块与该铜基底焊盘接触时使该半导体的至少一部分与该基底的至少一部分电性互连；
其中，在铜凸块与铜基底焊盘接触时，该凸块的至少一部分和该基底焊盘的至少一部分发生实质变形以在二者之间形成一非冶金结合；以及，
其中，通过该非反应型粘结剂加强该非冶金结合。
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