CN105164798B - 电子组件和制造电子组件的方法 - Google Patents

电子组件和制造电子组件的方法 Download PDF

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CN105164798B
CN105164798B CN201480025065.XA CN201480025065A CN105164798B CN 105164798 B CN105164798 B CN 105164798B CN 201480025065 A CN201480025065 A CN 201480025065A CN 105164798 B CN105164798 B CN 105164798B
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layer
conductive layer
groove
building brick
electronic building
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CN105164798A (zh
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T.戈特瓦尔德
A.诺伊曼
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Schweizer Electronic AG
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Schweizer Electronic AG
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Abstract

一种电子组件(36)，具有至少一个嵌入层序列中的电子元件(14)，其中，所述电子元件(14)布置在导电中心层(16)的凹槽中，并且在两面直接邻接相应的树脂层(12,20)。

Description

电子组件和制造电子组件的方法
技术领域
本发明涉及一种电子组件以及制造电子组件的方法。
背景技术
电子组件是已知的。其通常包括由导电和不导电层构成的或多或少复杂的层结构，并且在层序列中或上安装有电子元件(例如功率半导体等)。元件的接触通过位于其上的层结构的层来实现。
发明内容
根据本发明，提出了具有权利要求1的特征的制造电子组件的方法以及具有权利要求9的特征的电子组件和根据权利要求15的具有根据本发明的电子组件的印刷电路板。
根据本发明的思想在于，提供一种电子组件，其具有关于存在于组件中的至少一个电子元件对称的层结构。根据本发明的另一个思想在于，提供一种电子组件，其中，在层压中引入功率电子部件，而不事先进行至少一个触点的电接触。
这通过将元件在轻微加热的状态下直接安装在电绝缘层上来实现。由此，根据本发明，能够省去附加的焊接、烧结或者粘接的工作步骤。所安装的元件的充分固定通过至少在元件下方的区域中的电绝缘层的短暂液化以及随后的再固化来实现。
然而，在稍后的层压处理中，该层可能再次变软，这可能导致定位精度的损失。为了防止这一点，根据本发明，作为接下来的层设置要引入层结构中的“屏蔽罩”，其用作“模板”并且在进行压合期间将元件保持在其位置。该层包括至少一个凹槽，其尺寸针对要容纳的元件的尺寸确定，从而凹槽紧密地包围元件，并且防止在另外的处理期间滑移。此外，该层用于具有低电阻的散热路径的形成以及元件到大电流路径的低欧姆连接。
由此得到对称层结构的可能性，使得将至少一个元件嵌入“向上”和“向下”都相同的层序列中。相关层可以分别具有相同的尺寸，从而尽可能排除了元件的“上方”和“下方”区域之间的应力差异本身。由此防止薄的元件(半导体)扭曲。
当然，在本发明的范围内，安装至少一个电子元件和铺设“屏蔽罩”的顺序可以颠倒，方法是首先将屏蔽罩施加在电绝缘层上，随后将至少一个元件嵌入“屏蔽罩”的至少一个为此设置的对应的凹槽中。为了在电绝缘层上实现屏蔽罩的平的定位，在放在电绝缘层上时可以将屏蔽罩轻微地加热，以实现与前面结合电子元件的安装所描述的效果相同的效果。
从将至少一个元件引入具有基本相同的厚度的完全包围元件的片层中的事实，还得到具有高热容量的低热阻。
此外，通过消除元件下面的连接点(即焊接或烧结或者粘接点)，明显降低了易受侵蚀性。
本发明的其它优点和构造从描述和附图中得到。
很明显，上面提及的特征和下面还要说明的特征不仅能够以相应地给出的组合、而且能够以其它组合或者单独地应用，而不脱离本发明的范围。
根据实施例在附图中极其示意性地、而不是按照比例地示出了本发明，以进行图示，下面将参考附图详细地描述本发明。
附图说明
图1示出了本发明的电子组件的起始基板。
图2示出了施加有电绝缘层的图1的起始基板。
图3示出了安装有电子元件的图2的层序列。
图4A示出了施加有具有凹槽的导电层的图3的层序列。
图4B示出了包括具有凹槽的导电层的一个替换构造的图4A的层序列。
图4C示出了包括具有凹槽的导电层的另一个替换构造的图4A的层序列。
图5示出了在两面施加有预浸料和铜层的图4A的层序列。
图6示出了压合之后的图5的层序列。
图7示出了在两面引入了用于接触的盲孔的图6的层序列。
图8示出了盲孔被电镀或填充的图7的层序列。
图9示出了根据现有技术的晶体管的布置。
图10示出了根据本发明的晶体管的布置。
具体实施方式
图1示出了根据本发明的电子组件的起始基板10。起始基板10由导电材料制成。在此，其可以是铜片。替换地，其也可以是由具有低热膨胀系数的材料、例如由合适的铁镍合金制成的基板，其两面被铜覆盖。其一个示例是如在市场上可获得的预先制造好的铜-殷钢()-铜片(CIC片)。这种可获得的制造好的CIC层的一般厚度是150μm的和分别18μm的铜。
在接下来的步骤中，在起始基板10上施加由电绝缘材料构成的第一层12(参见图2)。如在电子组件的制造中所公知的，该层是由可固化的含树脂的材料构成的层。本领域技术人员还将这种材料称为Prepreg(预浸料)，其是“preimpregnated fibres”(预浸渍纤维)的英语简称。
然后，对由电绝缘材料构成的第一层12直接安装元件14(诸如例如功率元件、半导体芯片)，如在图3中所示出的。
根据本发明，在进行安装时将元件14轻微加热。在根据本发明的这种安装中，利用如下事实：由电绝缘材料构成的第一层12(下面为了简单起见称为预浸料层)的树脂材料在升高的温度下液化；如果现在将被加热的元件14放置在预浸料层12上，则其结果是，预浸材料的局限于元件14下方的区域部分液化，随后在冷却之后重新固化，由此该元件能够被粘住或附接。由此，元件14仅通过加热、而不需要其它辅助工具(例如粘接剂等)就充分地固定在希望的位置，用于进一步进行处理或加工。对元件14的加热例如借助加热的安装工具、例如所谓的热电极进行。
在接下来的步骤中，铺设具有至少一个凹槽18的第一导电层16。该层16例如可以例如由铜片等制成的是“屏蔽罩”或模板。该至少一个凹槽18的布置和尺寸被设计用于安装至少一个元件14(参见图4A)。或者换句话说：凹槽18的宽度和深度(即X-Y方向上的延伸长度)对应于元件14的宽度和深度加上定位公差d1，并且凹槽18的高度(即其材料厚度)对应于元件14的高度加上针对在随后进行压合时出现的第一导电层16的(轻微的)高度损失的补偿公差d2(用于压合过程中的元件14的压力释放)。
图4B示出了“屏蔽罩”或模板的一种替换构造，其中，导电层16的凹槽18`具有台阶或肩形的横截面。虽然一方面“屏蔽罩”的凹槽应当与元件(芯片)14间隔开，但是又应当尽可能紧地邻接元件(芯片)14，以确保元件在进一步的处理中的固定。然而，另一方面存在如下风险：在元件14与导电层16之间的距离d1太小的情况下，发生电流击穿。为了防止这一点，凹槽18`被构造为到导电层的上面和下面具有较大的直径，从而元件14和导电层16之间的距离在元件的导电表面处大幅增大，使得击穿风险被排除或者大大降低。在导电层16的中间区域，由于所述台阶的突出部19而保持较小的距离d1，从而继续满足固定功能。在此，对于附图的横截面表示选择了术语“直径”，而不应当被理解为凹槽是圆形的；相反，凹槽可以具有任意的形状，例如矩形、多边形、不规则形状等。
应当指出，突出部19的构造不局限于在图4B中示出的形状，其它形状也是可以的，并且对于本领域技术人员是显而易见的。特别地，可以想到具有倾斜延伸(漏斗形状)的表面19`的构造，其方便元件的事后插入，如例如根据在图4C中示出的实施方式的凹槽18``所示出的。“双漏斗形状”也是可以的。图4B和4C中的图示是极其示意性的，并且仅用于说明的目的；所示出的尺寸不是按比例绘制的，而是进行了大幅夸大。
定位公差d1例如可以在所谓的高精度芯片射枪情况下处于3μm数量级而在高速安装器情况下处于大约25至50μm的数量级。由于模板本身的铺设精度，凹陷的尺寸一般处于50至100μm的数量级。补偿公差d2例如可以取0至30μm，其是所选择的屏蔽罩16的片的厚度更厚的量。第一导电层16的厚度(即高度)能够以相对小的开销(例如通过辊压或电镀沉积或者与电镀产生的结构组合地)匹配于元件的高度。
随后，施加由电绝缘材料构成的第二层20和至少一个第二导电层22，如在图5中所示出的。由电绝缘材料构成的第二层20又可以是具有提高的热导率的预浸料层，并且第二导电层22可以是铜层或CIC层(如前面所述)。然后，将如此获得的层序列24以通常的方式压合/层压在一起。
根据本发明，层序列24被设计为得到如下的对称结构，即元件14嵌入中心层16(第一导电层)中，在元件14的两面(即在与该结构、由此与元件和中心层的主延伸平面垂直的两个方向上)覆盖预浸料层12、20和位于其上的导电层10、22(起始基板和第二导电层)。
如从附图的图示中还可以看到，至少一个元件分别向上和向下与其接触的表面是一致的，即不存在或者仅存在很小的差异，从而使表面应力的差异最小化。由此能够明显减小并且在很大程度上避免所嵌入的元件的拱曲。
在这种情况下应当指出，在本申请的范围内，应当相对于在附图中示出的元件和层序列的朝向来理解术语“上”和“下”。当然，其是相对的称谓，当层序列翻转时，这些称谓原则上也改变，然而这对于根据本发明的对称结构没有影响。然而，这对于本领域技术人员也是显而易见的。
在图6中示出了层序列24的压合状态24`。在压合期间，元件14被第一导电层16的尺寸紧密的凹槽18保持在其位置处，并且位于元件14两面的预浸料层12、20的液化的树脂进入元件14和第一导电层16之间的间隙d1。随后，液化的树脂固化，然后以固体材料26填充所述间隙。
图7示出了如何在随后的步骤中在两面在层10、12或20、22中引入引导到元件14的两个表面的盲孔28。这以对于本领域技术人员来说本身已知的方式进行，例如通过激光处理或者通过蚀刻处理进行。已经表明特别有利的是，根据本发明，至少一个元件的接触完全在嵌入之后进行，并且省去了前面的构造和连接处理。
然后，将用于接触元件14的盲孔28以导电材料、例如特别是铜填充。这例如通过镀敷处理来进行，其中，在层序列的两面，在最外面的导电层10、22上分别施加铜层30、32，其还填充盲孔28(参见图8)。为此，至少一个元件具有允许具有足够高的附着力的电接触的表面，例如铜。然后，与印刷电路板功能的进一步设计有关地对所施加的铜层30、32进行所谓的光刻结构化，即进行保护层涂敷，之后进行曝光、显影和蚀刻处理，以例如形成下面描述的晶体管布置。在此，其是本领域技术人员熟知的过程。
如从图7和8的图示中可以看到的，本发明的层序列的特征在于，即使在制作并且填充通路孔28之后，也以元件14为中心的层对称性。
根据本发明，这种层对称性可以用于有利地构造电子组件，即在设计组件时使用，如下面将描述的。
通常，在设计要安装有源元件(例如MOS-FET晶体管)的电子组件时，要考虑这种元件的至少三个接头(栅极、源极、漏极)位于元件的相对的面上，因此在安装多个元件/晶体管(例如用于实现桥式电路)时，需要在元件上方具有附加的通路孔或附加的接线的复杂的结构。在图9中示意性地示出了已知的这种结构。
本发明实现了明显简化的结构，因为现在可以在两面接触元件，其结果是，可以交替地布置元件(即例如漏极在上/源极在下，随后漏极在下/源极在上等等)。
这在图10中示出。图10示出了具有两个晶体管元件42、44(下面简称为晶体管)的根据本发明的层结构40。
在图10的图示中位于左侧的第一晶体管42的漏极接头D1指向下，并且其栅极和源极接头G1、S1指向上。如前面所描述的，接头D1、G1、S1与由盲孔28形成的通路孔接触。在图10的图示中位于右侧的第二晶体管44的漏极接头D2指向上，而栅极和源极接头G2、S2对应地指向下。由此，两个晶体管42、44的朝向彼此交替地布置。
如从图10的图示可以看到的，根据本发明，由此相邻的晶体管的源极和漏极接头能够简单地彼此连接，因为它们现在处于一个连接平面上。在所示出的示例中，这意味着，第一晶体管42的源极接头S1能够在镀敷的层32的平面上简单地与第二晶体管44的漏极接头D2连接。
根据本发明的晶体管的交替取向(以垂直朝向，即沿着电子组件40的纵向延伸方向或通过电子组件40展开的平面，如通过图10的图示所示出的)也可以描述为“面朝上/面朝下”布置。
第一导电层16(制造好的电子组件中的中心层)的模板或屏蔽罩可以通过穿孔和支撑接片的组合而分成片段。在进行层压(压合)之后，可以将支撑接片从外部移除，由此形成能够连接到不同的电势的区域。支撑接片被一起层压在层结构中，并且将通过对整个结构打孔的步骤而移除。为此，孔直径至少对应于接片长度。通过这些措施，中心导电层可以在电路布置完成之后用于以低电阻输送大电流。通过在电子组件的内部(即在中心导电层中)和在至少一个外部层中引导电流，可以实现非常低的感应连接，这对于电路以低损耗工作是有利的。
将“模板”16集成到电子组件的电功能性中例如可以通过以层16的希望的子区域接触外部层来实现，例如借助盲孔(未进一步示出)。在需要时，其它接触方法对于本领域技术人员也是显而易见的。
由于根据本发明的对嵌入的至少一个电子元件的两面接触，制造好的电子组件向外不是无电势的。因此，通常还需要例如相对于仍然需要设置的(未描述并且未示出的)本身已知的散热器的电绝缘。其它可能性是借助所谓的热界面材料(TIM，thermischenInterface-Material)设置绝缘层，或者借助附加的压合设置至少一个另外的绝缘层。在将制造好的电子组件装入印刷电路板时，通过嵌入印刷电路板结构的电绝缘层来进行电绝缘。在需要时，本领域技术人员熟知为此所需的措施。

Claims (9)

1.一种制造电子组件(36,40)的方法，具有如下步骤：
-制备导电的起始基板(10)，
-在起始基板上铺设由电绝缘层材料构成的第一层(12)，
-在所述第一层(12)上安装至少一个元件(14；42,44)，
-在所述第一层(12)上敷设具有至少一个凹槽(18,18`)的第一导电层(16)，其中，针对所述至少一个元件(14；42,44)设计所述至少一个凹槽(18,18`)的布置和尺寸以使所述至少一个元件安装在所述至少一个凹槽(18,18`)中，
-在所述至少一个元件(14；42,44)和所述第一导电层(16)上施加由电绝缘材料构成的第二层(20)和至少一个第二导电层(22)，以及
-压合所产生的层序列(24)，
其中，在安装至少一个元件(14；42,44)的步骤之后进行敷设第一导电层(16)的步骤，其中，在进行安装的时刻，所述至少一个元件(14；42,44)具有升高的温度。
2.一种制造电子组件(36,40)的方法，具有如下步骤：
-制备导电的起始基板(10)，
-在所述起始基板上铺设由电绝缘层材料构成的第一层(12)，
-在所述第一层(12)上安装至少一个元件(14；42,44)，
-在所述第一层(12)上敷设具有至少一个凹槽(18,18`)的第一导电层(16)，其中，针对所述至少一个元件(14；42,44)设计所述至少一个凹槽(18,18`)的布置和尺寸以使所述至少一个元件安装在所述至少一个凹槽(18,18`)中，
-在所述至少一个元件(14；42,44)和所述第一导电层(16)上施加由电绝缘材料构成的第二层(20)和至少一个第二导电层(22)，以及
-压合所产生的层序列(24)，
其中，在敷设第一导电层(16)的步骤之后进行安装至少一个元件(14；42,44)的步骤，其中，在进行安装的时刻，所述第一导电层(16)具有升高的温度。
3.根据权利要求1或2所述的方法，其中，所述元件(14；42,44)是功率半导体。
4.根据权利要求1或2所述的方法，其中，所述元件(14；42,44)借助热电极进行安装。
5.根据权利要求1或2所述的方法，其中，所述元件(14；42,44)和所述第一导电层(16)具有基本上相同的高度，或者其中，所述第一导电层(16)具有基本上与所述元件(14；42,44)加上补偿公差(d2)相同的高度。
6.根据权利要求1或2所述的方法，其中，所述第一导电层(16)的至少一个凹槽(18,18`)的长度和宽度的尺寸至少局部地对应于所述元件(14；42,44)的尺寸加上定位公差(d1)。
7.根据权利要求1或2所述的方法，具有将通路孔(28,30,32)在两面引入到所述元件(14；42,44)的步骤。
8.根据权利要求7所述的方法，其中，所述通路孔(28,30,32)借助激光刻孔和随后的电镀镀敷，或者借助蚀刻铜层和对电介质的激光刻孔以及随后的电镀镀敷来产生。
9.根据权利要求1或2所述的方法，其中，安装步骤包括安装至少两个功率半导体(42,44)，其接头(D1,G1,S1；D2,G2,S2)以垂直的取向彼此交替地布置。
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