WO2010116887A9 - 絶縁ゲート型電界効果トランジスタ - Google Patents
絶縁ゲート型電界効果トランジスタ Download PDFInfo
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- WO2010116887A9 WO2010116887A9 PCT/JP2010/054951 JP2010054951W WO2010116887A9 WO 2010116887 A9 WO2010116887 A9 WO 2010116887A9 JP 2010054951 W JP2010054951 W JP 2010054951W WO 2010116887 A9 WO2010116887 A9 WO 2010116887A9
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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Definitions
- the present invention relates to an insulated gate field effect transistor, and more particularly to an insulated gate field effect transistor capable of improving channel mobility.
- silicon carbide (SiC) is being adopted as a material constituting a semiconductor device in order to enable a semiconductor device to have a high breakdown voltage, low loss, and use in a high temperature environment.
- Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon (Si) that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device.
- a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- the conventional MOSFETs including the MOSFETs disclosed in Patent Documents 1 and 2 cannot be said to have sufficiently high channel mobility, and the on-resistance is not sufficiently reduced. It was. More specifically, when the gate voltage is low, the channel mobility of the storage MOSFET disclosed in Patent Documents 1 and 2 is large. However, when the gate voltage increases, the influence of the interface between SiC that forms the channel and SiO 2 that is the gate oxide film increases, and the mobility becomes equivalent to that of the conventional inversion MOSFET (S.
- an object of the present invention is to provide a MOSFET capable of reducing on-resistance by improving channel mobility even when the gate voltage is high.
- a MOSFET which is an insulated gate field effect transistor according to the present invention includes a substrate, a breakdown voltage holding layer, a well region, an oxide film, a first conductivity type contact region, a channel region, and an electrode.
- the substrate is made of silicon carbide (SiC), has a main surface with an off angle of 50 ° or more and 65 ° or less with respect to the ⁇ 0001 ⁇ plane, and is of the first conductivity type.
- the breakdown voltage holding layer is made of SiC, is formed on the main surface of the substrate, and has the first conductivity type.
- the well region is formed away from the first main surface, which is the main surface on the substrate side, in the breakdown voltage holding layer, and has a second conductivity type different from the first conductivity type.
- the oxide film is formed on the well region and is made of an oxide.
- the first conductivity type contact region is disposed between the well region and the oxide film, and is of the first conductivity type by containing the first conductivity type impurity at a higher concentration than the breakdown voltage holding layer.
- the channel region is disposed between the well region and the oxide film so as to be in contact with the well region and the oxide film, connects the first conductivity type contact region and the breakdown voltage holding layer, and is more than the first conductivity type contact region.
- the first conductivity type is obtained by containing a low-concentration first conductivity type impurity.
- the electrode is disposed on the oxide film. In a region including the interface between the channel region and the oxide film, a high nitrogen concentration region having a higher nitrogen concentration than the channel region and the oxide film is formed.
- the SiC substrate used in the storage MOSFET employing SiC as a material generally has a main surface with an off angle of about 8 ° with respect to the plane orientation ⁇ 0001 ⁇ .
- a breakdown voltage holding layer, a well region, a channel region, an oxide film, an electrode, and the like are formed on the main surface, and a storage MOSFET is obtained.
- the storage type MOSFET having such a structure there are many in the vicinity of the interface between the channel region and the oxide film because the off angle with respect to the plane orientation ⁇ 0001 ⁇ of the main surface of the substrate is about 8 °. Interface states are formed, which hinders the travel of electrons. Since the influence of the interface state is small under a low gate voltage, a high channel mobility can be obtained. However, under the high gate voltage, the channel mobility is lowered due to the influence of the interface state.
- an SiC substrate having a main surface with an off angle with respect to the plane orientation ⁇ 0001 ⁇ of 50 ° or more and 65 ° or less is adopted, so that the formation of the interface state is reduced, Channel mobility under high gate voltage is improved.
- the channel mobility under a high gate voltage is improved by forming a high nitrogen concentration region in a region including the interface between the channel region and the oxide film. Therefore, the channel mobility is further improved in the MOSFET of the present invention.
- the lower limit of the off-angle is set to 50 ° because the relationship between the off-angle and the channel mobility of the inverting MOSFET that determines the channel mobility under a high gate voltage in the storage MOSFET is examined. From the (01-14) plane having an angle of 43.3 ° to the (01-13) plane having an off angle of 51.5 °, a significant increase in channel mobility was observed with an increase in the off angle, and the above ( This is based on the fact that there is no natural surface in the range of the off angle between the (01-14) plane and the (01-13) plane.
- the upper limit of the off-angle is 65 ° because the off-angle increases and the carrier mobility increases from the (01-12) plane with an off-angle of 62.1 ° to the (01-10) plane with an off-angle of 90 °. This is based on the fact that there was a significant decrease in the above and that there is no natural surface in the range of the off angle between the (01-12) surface and the (01-10) surface.
- the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the channel region and the oxide film is preferably 1 ⁇ 10 21 cm ⁇ 3 or more.
- the off orientation of the main surface of the substrate may be in the range of ⁇ 11-20> direction ⁇ 5 ° or less.
- the ⁇ 11-20> direction is a typical off orientation in the SiC substrate. Then, by setting the variation in off orientation caused by slicing variations in the substrate manufacturing process to ⁇ 5 °, it is easy to form an epitaxial layer on the SiC substrate, and the MOSFET is easily manufactured. be able to.
- the off orientation of the main surface of the substrate may be in the range of ⁇ 01-10> direction ⁇ 5 ° or less.
- the ⁇ 01-10> direction is a typical off orientation in the SiC substrate, similar to the ⁇ 11-20> direction. Then, by setting the variation in off orientation caused by slicing variations in the substrate manufacturing process to ⁇ 5 °, it is easy to form an epitaxial layer on the SiC substrate, and the MOSFET is easily manufactured. be able to.
- the plane orientation of the main surface of the substrate can be set to an off angle of ⁇ 3 ° to + 5 ° with respect to the plane orientation ⁇ 03-38 ⁇ .
- the channel mobility can be further improved.
- the off angle with respect to the plane orientation ⁇ 03-38 ⁇ is set to ⁇ 3 ° or more and + 5 ° or less.
- the channel mobility is particularly high within this range. Is based on the obtained.
- the state that “the off angle is ⁇ 3 ° or more and + 5 ° or less with respect to the plane orientation ⁇ 03-38 ⁇ ” means that the ⁇ 0001> direction and the ⁇ 01-10> direction as a reference for the off orientation are stretched.
- This means that the angle formed between the normal projection of the principal surface to the plane and the normal of the ⁇ 03-38 ⁇ plane is -3 ° or more and + 5 ° or less, and the sign is The case where it approaches parallel to the ⁇ 01-10> direction is positive, and the case where the orthographic projection approaches parallel to the ⁇ 0001> direction is negative.
- the surface orientation of the main surface is more preferably ⁇ 03-38 ⁇ , and the surface orientation of the main surface is more preferably ⁇ 03-38 ⁇ .
- the surface orientation of the main surface is substantially ⁇ 03-38 ⁇ , taking into account the processing accuracy of the substrate, etc., the substrate is within an off-angle range where the surface orientation can be substantially regarded as ⁇ 03-38 ⁇ .
- the off angle range is, for example, a range of ⁇ 2 ° with respect to ⁇ 03-38 ⁇ .
- the main surface of the substrate may have an off angle of ⁇ 3 ° to + 5 ° with respect to the (0-33-8) plane in the ⁇ 01-10> direction.
- the (0001) plane of hexagonal single crystal silicon carbide is defined as the silicon plane
- the (000-1) plane is defined as the carbon plane.
- the “off angle with respect to the (0-33-8) plane in the ⁇ 01-10> direction” refers to the above described plane extending in the ⁇ 01-10> direction as a reference for the ⁇ 000-1> direction and the off orientation. This is the angle formed between the orthogonal projection of the normal of the principal surface and the normal of the (0-33-8) surface, and the sign is that the orthogonal projection may approach parallel to the ⁇ 01-10> direction. It is positive and negative when the orthographic projection approaches parallel to the ⁇ 000-1> direction.
- the main surface having an off angle with respect to the (0-33-8) plane in the ⁇ 01-10> direction of -3 ° or more and + 5 ° or less is a carbon surface satisfying the above conditions in a silicon carbide crystal. It means the side surface.
- the (0-33-8) plane includes an equivalent carbon plane-side plane whose expression differs depending on the setting of an axis for defining a crystal plane, and does not include a silicon plane-side plane.
- MOSFET 1 in the present embodiment includes substrate 11, buffer layer 12, breakdown voltage holding layer 13, well region 14, n-type contact region 15, p-type contact region 16, and channel. A region 17 and a gate oxide film 18 are provided.
- the substrate 11 is made of hexagonal SiC, for example, 4H—SiC, and has a main surface 11A having an off angle with respect to the plane orientation ⁇ 0001 ⁇ of 50 ° or more and 65 ° or less, for example, the plane orientation (03-38).
- the conductivity type is n-type (first conductivity type).
- the resistivity of the substrate 11 is, for example, about 0.02 ⁇ cm.
- the buffer layer 12 is a SiC layer having a thickness of about 0.5 ⁇ m formed by epitaxial growth on the main surface 11A of the substrate 11, for example, and contains n-type impurities at a concentration of about 5 ⁇ 10 17 cm ⁇ 3.
- the type is n-type (first conductivity type).
- the breakdown voltage holding layer 13 is made of SiC, is formed on the main surface 11A of the substrate 11 with the buffer layer 12 interposed therebetween, and includes an n-type impurity at a concentration of about 5 ⁇ 10 15 cm ⁇ 3 so that the conductivity type is n-type. It has become. Moreover, the thickness of the pressure
- the well regions 14 are formed in the breakdown voltage holding layer 13 as a pair apart from the first main surface 13A, which is the main surface on the substrate 11 side, and contain p-type impurities, whereby the conductivity type is p-type (second conductivity type). ).
- the gate oxide film 18 is formed on the well region 14 (on the breakdown voltage holding layer 13) and is made of silicon dioxide (SiO 2 ) which is an oxide.
- the thickness of the gate oxide film 18 is, for example, about 40 nm.
- a pair of n-type contact regions 15 as first conductivity type contact regions are disposed between the well region 14 and the gate oxide film 18 so as to be in contact with the well region 14 and the gate oxide film 18. Since n-type impurities are contained at a high concentration, the conductivity type is n-type.
- the n-type contact region 15 is arranged so as to be included in the well region 14 in plan view. In other words, the n-type contact region 15 is included in the well region 14 when viewed from the upper side (gate oxide film 18 side) perpendicular to the main surface 11A of the substrate 11.
- the p-type contact region 16 as the second conductivity type contact region is disposed adjacent to the n-type contact region 15 and contains p-type impurities at a higher concentration than the well region 14 so that the conductivity type becomes p-type. Yes. More specifically, the p-type contact region 16 is adjacent to each of the pair of n-type contact regions 15 on the side opposite to the other n-type contact region 15 when viewed from one n-type contact region 15. Has been placed. The p-type contact region 16 is disposed between the well region 14 and the ohmic contact electrode 19 (described later) in contact with the well region 14 and the ohmic contact electrode 19.
- Channel region 17 is arranged between well region 14 and gate oxide film 18 so as to be in contact with well region 14 and gate oxide film 18, and connects n-type contact region 15 and breakdown voltage holding layer 13. . Further, the channel region 17 has an n-type conductivity by containing an n-type impurity at a lower concentration than the n-type contact region 15. From another viewpoint, the channel region 17 is arranged along the gate oxide film 18 so as to extend from the n-type contact region 15 to the side opposite to the p-type contact region 16 adjacent to the n-type contact region 15. The n-type contact region 15 and the breakdown voltage holding layer 13 are connected.
- MOSFET 1 in the present embodiment includes a gate electrode 20, an ohmic contact electrode 19, a source electrode 21, and a drain electrode 22.
- Gate electrode 20 is arranged in contact with gate oxide film 18 and extends from the region on n-type contact region 15 to the side opposite to p-type contact region 16 when viewed from n-type contact region 15. Thus, the channel region 17 is opposed to the gate oxide film 18 therebetween.
- the gate electrode 20 is made of a conductor such as Al (aluminum) or polysilicon.
- the ohmic contact electrode 19 is arranged on the n-type contact region 15 and the p-type contact region 16 so as to extend from a region in contact with the n-type contact region 15 to a region in contact with the p-type contact region 16. .
- the ohmic contact electrode 19 is made of a conductor such as Ni (nickel) that can secure an ohmic contact with the n-type contact region 15 by siliciding at least a part thereof.
- the source electrode 21 is disposed in contact with the ohmic contact electrode 19 and is made of a conductor such as Al.
- the drain electrode 22 is disposed in contact with the main surface of the substrate 11 opposite to the side on which the breakdown voltage holding layer 13 is formed, and at least a part thereof such as Ni (nickel) is silicided. Thus, it is made of a conductor capable of ensuring ohmic contact with the substrate 11.
- a high nitrogen concentration region 23 having a higher nitrogen concentration than the channel region 17 and the gate oxide film 18 is formed.
- MOSFET 1 when the voltage applied to gate electrode 20 is less than the threshold value, a depletion layer is formed in channel region 17 sandwiched between well region 14 and gate electrode 20. As a result, the n-type contact region 15 and the breakdown voltage holding layer 13 are not electrically connected, and the MOSFET 1 is turned off. On the other hand, when the voltage applied to the gate electrode 20 exceeds the threshold value, the depletion layer in the channel region 17 under the gate oxide film 18 is reduced, and the n-type contact region 15 and the breakdown voltage holding layer 13 are electrically connected. Is done. As a result, the MOSFET 1 is turned on, and a current flows between the source electrode 21 and the drain electrode 22.
- substrate 11 having main surface 11A having an off angle of 50 ° or more and 65 ° or less with respect to the plane orientation ⁇ 0001 ⁇ is employed.
- the buffer layer 12, the breakdown voltage holding layer 13, and the channel region 17 are formed on the main surface 11A by epitaxial growth. Therefore, the formation of interface states near the interface between the gate oxide film 18 and the channel region 17 is reduced, and the channel mobility under a high gate voltage is improved.
- the channel mobility can be further improved by setting the plane orientation of the main surface 11A to (0-33-8).
- the channel mobility under a high gate voltage is further improved. This is considered to be due to the following reasons. That is, when the gate oxide film 18 is formed by thermal oxidation or the like, many interface states are formed near the interface between the gate oxide film 18 and the channel region 17. As it is, the channel mobility in the vicinity of the interface, which is a problem under a high gate voltage, is greatly reduced compared to the theoretical value. In contrast, by introducing nitrogen into the region including the interface between the gate oxide film 18 and the channel region 17 as described above, the influence of the above-described interface state is reduced.
- the MOSFET 1 in the present embodiment is a MOSFET with reduced on-resistance by improving channel mobility even when the gate voltage is high.
- the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the channel region 17 and the gate oxide film 18 is 1 ⁇ 10 21 cm ⁇ 3 or more. Thereby, channel mobility can be further improved.
- a substrate having a main surface having an off orientation in the ⁇ 11-20> direction ⁇ 5 ° or less is used instead of the substrate 11 having the main surface having a plane orientation of (03-38). It may be adopted. This facilitates formation of an epitaxial layer on the SiC substrate and facilitates manufacture of the MOSFET.
- a substrate preparation step is performed as a step (S10).
- step (S10) referring to FIG. 3, main surface 11A made of, for example, 4H—SiC and having an off angle with respect to surface orientation ⁇ 0001 ⁇ of 50 ° or more and 65 ° or less, eg, surface orientation (03-38).
- the substrate 11 having the n-type conductivity is prepared by containing n-type impurities. From the viewpoint of further improving the channel mobility of MOSFET 1 to be manufactured, substrate 11 having main surface 11A having a plane orientation of (0-33-8) may be prepared.
- a first epitaxial growth step is performed as a step (S20).
- step (S20) referring to FIG. 3, buffer layer 12 and breakdown voltage holding layer 13 are formed by epitaxial growth on main surface 11A of substrate 11 prepared in step (S10).
- Epitaxial growth can be performed, for example, using a mixed gas of SiH 4 (silane) and C 3 H 8 (propane) as a source gas and introducing n-type impurities.
- a SiC layer into which n-type impurities are introduced at a concentration of about 5 ⁇ 10 17 cm ⁇ 3 is formed to a thickness of about 0.5 ⁇ m to form the buffer layer 12, and then the concentration of the n-type impurities to be introduced is changed.
- the SiC layer can be formed with a thickness of about 10 ⁇ m to form the breakdown voltage holding layer 13.
- an oxide film made of SiO 2 is formed on second main surface 13B by, for example, CVD. Then, after a resist is applied on the oxide film, exposure and development are performed, and a resist film having an opening in a region corresponding to the shape of the desired well region 14 is formed. Then, using the resist film as a mask, the oxide film is partially removed by, for example, RIE (Reactive Ion Etching), so that an opening pattern corresponding to the shape of the desired well region 14 is obtained. A mask layer made of an oxide film is formed. Thereafter, after removing the resist film, a p-type impurity is ion-implanted using the mask layer as a mask to form a well region 14.
- RIE Reactive Ion Etching
- a first activation annealing step is performed as a step (S40).
- This step (S40) is a heat treatment for activating the impurities introduced by the ion implantation by heating the breakdown voltage holding layer 13 in which the ion implantation is performed in the step (S30) with reference to FIG.
- Activation annealing is performed.
- the activation annealing can be performed, for example, by performing a heat treatment that is held at 1700 ° C. for 30 minutes in an argon gas atmosphere.
- steps (S60) and (S70) an n-type contact region forming step and a p-type contact region forming step are performed. Specifically, referring to FIGS. 5 and 6, first, in step (S60), a mask layer having an opening pattern corresponding to the shape of desired n-type contact region 15 is obtained by the same procedure as in step (S30). The n-type contact region 15 is formed by forming and ion-implanting n-type impurities. Further, in step (S70), after the mask layer is removed, a mask layer having an opening pattern corresponding to the shape of the desired p-type contact region 16 is formed by the same procedure, and p-type impurities are ion-implanted.
- a second activation annealing step is performed as a step (S80).
- step (S80) referring to FIG. 6, activation annealing is performed by heating the breakdown voltage holding layer 13 in which the ion implantation is performed in steps (S60) and (S70).
- the activation annealing can be performed, for example, in the same manner as in the step (S40).
- a gate oxide film forming step is performed as a step (S90).
- steps (S10) to (S80) are carried out to form a substrate on which breakdown voltage holding layer 13 including desired ion-implanted layer and channel region 17 are formed.
- 11 is dry oxidized by being heated to 1200 ° C. in an oxidizing atmosphere and held for 30 minutes, for example.
- thermal oxide film 18A to be gate oxide film 18 is formed to extend on channel region 17, on n-type contact region 15 and on p-type contact region 16.
- the thickness of the thermal oxide film 18A is, for example, about 40 nm.
- a high nitrogen concentration region forming step is performed as a step (S100).
- a heat treatment is performed in which heating is performed at 1200 ° C. in a nitrogen monoxide (NO) gas atmosphere and held for 120 minutes.
- NO nitrogen monoxide
- a nickel (Ni) film is deposited on the thermal oxide film 18A, the n-type contact region 15 and the p-type contact region 16 exposed from the thermal oxide film 18A, and the substrate 11 on the opposite side to the withstand voltage holding layer 13 by vapor deposition, for example.
- the resist film is formed on the main surface without removing the resist film.
- a Ni film is formed in a region where the ohmic contact electrode 19 and the drain electrode 22 are to be formed.
- a heat treatment is performed by heating to 950 ° C.
- the n-type contact region 15 and the p-type contact region 16 are formed by ion implantation, and then activation annealing is performed by holding at 1700 ° C. for 30 minutes in an Ar atmosphere. did.
- a substrate 11 (n-type, resistivity 0.02 ⁇ cm) made of 4H—SiC having a main surface 11A having an off angle of 8 ° with respect to the plane orientation (0001) was prepared.
- Another MOSFET 1 was manufactured under the same conditions (comparative example).
- the buffer layer 32 corresponding to the buffer layer 12 and the n-type layer 33 corresponding to the breakdown voltage holding layer 13 having the same impurity concentration, thickness and the like as the MOSFET it corresponds to the well region 14.
- the p-type layer 34 to be formed was similarly formed.
- ion implantation is performed to thereby correspond to the source region 35A and the drain region 35B corresponding to the n-type contact region 15 and the p-type contact region 16.
- a p-type contact region 36 and a channel region 37 corresponding to the channel region 17 are formed in the same manner, a gate oxide film 38 corresponding to the gate oxide film 18, an ohmic contact electrode 39 corresponding to the ohmic contact electrode 19, and a gate A gate electrode 40 corresponding to the electrode 20, a source electrode 41A and a drain electrode 41B corresponding to the source electrode 21 were formed (storage type MOSFET on (03-38) and storage type MOSFET on (0001)).
- the channel length L was 100 ⁇ m
- the channel width the width of the channel in the direction perpendicular to the paper surface in FIG. 9 was 150 ⁇ m.
- FIG. 10 shows the relationship between the gate voltage and channel mobility.
- the horizontal axis indicates the gate voltage
- the vertical axis indicates the channel mobility.
- a lateral inversion MOSFET 71 shown in FIG. 11 was produced as a sample. More specifically, an epitaxial layer 73 having a thickness of 10 ⁇ m was formed on an n-type silicon carbide substrate 72 having a thickness of 400 ⁇ m, and a p-type layer 74 having a thickness of 1 ⁇ m was formed on the epitaxial layer 73. Then, phosphorus (P) was implanted as an n-type impurity into the p-type layer 74 to form n + regions 75 and 76 having an n-type impurity concentration of 1 ⁇ 10 20 cm ⁇ 3 .
- the gate length (channel length L g ) which is the distance between the n + regions 75 and 76, was 100 ⁇ m.
- the gate width (channel width) was 200 ⁇ m.
- the distribution of the nitrogen concentration in the depth direction in the vicinity of the interface between the oxide film 78 and the p-type layer 74 (region within 10 nm from the interface) was measured.
- the measurement was performed by SIMS (secondary ion mass spectrometry).
- the horizontal axis indicates the peak value of nitrogen concentration (nitrogen peak concentration) measured in each sample
- the vertical axis indicates the measured channel mobility of the inverted MOSFET.
- the channel mobility increases as the nitrogen peak concentration in the region within 10 nm from the interface between oxide film 78 and p-type layer 74 increases.
- the channel mobility is preferably set to 50 cm 2 / Vs or more. Therefore, with reference to FIG. 12, in consideration of manufacturing process variations and the like, in order to set the channel mobility of the inversion MOSFET to 50 cm 2 / Vs or more, the peak concentration of nitrogen is 1 ⁇ 10 21 cm ⁇ 3 or more. It can be said that it is preferable. Then, by improving the channel mobility of the inverting MOSFET as described above, the channel mobility of the storage MOSFET under a high gate voltage can be sufficiently improved.
- the maximum value of the nitrogen concentration in the region within 10 nm from the interface between the channel region and the oxide film is set to 1 ⁇ 10 21 cm ⁇ . It can be said that it is preferably 3 or more.
- a sample was manufactured using the same manufacturing method as that of the sample having the highest channel mobility in Example 2 described above. Specifically, four types of samples as comparative examples and three types of samples as examples of the present invention were prepared using substrates having different surface orientations of the main surface.
- Comparative Example A a silicon carbide substrate (8 ° off substrate of (0001)) having a main surface with an off angle of 8 ° with respect to the plane orientation (0001), as Comparative Example B
- a substrate using a substrate whose main surface is represented by (01-15) as Comparative Example C, a substrate using a substrate whose main surface is represented by (01-14), and a comparative example As D, a substrate using a substrate having a main surface with an off angle of 70 ° with respect to the plane orientation (0001) was prepared.
- Example A a substrate in which the plane orientation of the main surface of the substrate is represented by (01-13) is used as Example A, and a plane orientation of the main surface of the substrate is (03) as Example B.
- the horizontal axis indicates the off-angle of the main surface of the substrate constituting each sample with respect to the plane orientation ⁇ 0001 ⁇
- the vertical axis indicates the inversion MOSFET channel mobility.
- the channel mobility value of the inverting MOSFET is a comparative example. It can be seen that it is greatly improved compared to.
- the channel mobility of the inverting MOSFET by improving the channel mobility of the inverting MOSFET as described above, the channel mobility of the storage MOSFET under a high gate voltage can be sufficiently improved. Therefore, in order to sufficiently improve the channel mobility of the storage MOSFET under a high gate voltage, a substrate having a main surface (main surface) having an off angle of 50 ° or more and 65 ° or less with respect to the plane orientation ⁇ 0001 ⁇ . It can be said that it is effective to adopt.
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Abstract
Description
そこで、本発明の目的は、ゲート電圧が高い場合でも、チャネル移動度を向上させることによりオン抵抗を低減することが可能なMOSFETを提供することである。
本発明者は、ゲート電圧が高い場合における蓄積型MOSFETのチャネル移動度を向上させる方策について検討を行なった。その結果、以下の知見が得られ、本発明に想到した。
以上のように、本発明のMOSFETによれば、ゲート電圧が高い場合でも、チャネル移動度を向上させることによりオン抵抗を低減することが可能なMOSFETを提供することができる。
以上の説明から明らかなように、本発明のMOSFETによれば、ゲート電圧が高い場合でも、チャネル移動度を向上させることによりオン抵抗を低減することが可能なMOSFETを提供することができる。
以上のように、本実施の形態におけるMOSFET1は、ゲート電圧が高い場合においても、チャネル移動度を向上させることによりオン抵抗を低減したMOSFETとなっている。
以下、本発明の実施例1について説明する。本発明のMOSFETにおけるチャネル移動度の向上およびオン抵抗の低減を確認する実験を行なった。実験の手順は以下の通りである。
以上の実験結果から、本発明のMOSFETによれば、ゲート電圧が高い場合でも、チャネル移動度を向上させることによりオン抵抗を低減することが可能なMOSFETを提供できることが確認された。
次に、本発明の実施例2について説明する。チャネル領域と酸化膜との界面から10nm以内の領域における窒素濃度の最大値(窒素のピーク濃度)と反転型MOSFETチャネル移動度との関係を調査する実験を行なった。実験の手順は以下の通りである。
チャネル移動度μ=gm×(L×d)/(W×ε×VDS)
(ここで、L:ゲート長、d:酸化膜厚、W:ゲート幅、ε:酸化膜の誘電率)
という式からチャネル移動度のゲート電圧に対する最大値を求めた。
次に、本発明の実施例3について説明する。基板のオフ角と反転型MOSFETチャネル移動度との関係を調査する実験を行なった。実験の手順は以下の通りである。
Claims (6)
- 炭化珪素からなり、{0001}面に対するオフ角が50°以上65°以下である主面(11A)を有する第1導電型の基板(11)と、
炭化珪素からなり、前記基板(11)の前記主面上(11A)に形成された前記第1導電型の耐圧保持層(13)と、
前記耐圧保持層(13)において、前記基板(11)側の主面である第1の主面(13A)から離れて形成された、前記第1導電型とは導電型の異なる第2導電型のウェル領域(14)と、
前記ウェル領域(14)上に形成され、酸化物からなる酸化膜(18)と、
前記ウェル領域(14)と前記酸化膜(18)との間に配置され、前記耐圧保持層(13)よりも高濃度の前記第1導電型の不純物を含む第1導電型コンタクト領域(15)と、
前記ウェル領域(14)と前記酸化膜(18)との間に、前記ウェル領域(14)および前記酸化膜(18)に接触するように配置され、前記第1導電型コンタクト領域(15)と前記耐圧保持層(13)とを接続し、前記第1導電型コンタクト領域(15)よりも低濃度の前記第1導電型の不純物を含むことにより、前記第1導電型となっているチャネル領域(17)と、
前記酸化膜(18)上に配置された電極(20)とを備え、
前記チャネル領域(17)と前記酸化膜(18)との界面を含む領域には、前記チャネル領域(17)および前記酸化膜(18)よりも窒素濃度の高い高窒素濃度領域(23)が形成されている、絶縁ゲート型電界効果トランジスタ(1)。 - 前記チャネル領域(17)と前記酸化膜(18)との界面から10nm以内の領域における窒素濃度の最大値が1×1021cm-3以上である、請求の範囲第1項に記載の絶縁ゲート型電界効果トランジスタ(1)。
- 前記基板(11)の前記主面(11A)のオフ方位が<11-20>方向±5°以下の範囲である、請求の範囲第1項に記載の絶縁ゲート型電界効果トランジスタ(1)。
- 前記基板(11)の前記主面(11A)のオフ方位が<01-10>方向±5°以下の範囲である、請求の範囲第1項に記載の絶縁ゲート型電界効果トランジスタ(1)。
- 前記基板(11)の前記主面(11A)の面方位は、面方位{03-38}に対してオフ角が-3°以上+5°以下である、請求の範囲第4項に記載の絶縁ゲート型電界効果トランジスタ(1)。
- 前記基板(11)の前記主面(11A)は、<01-10>方向における(0-33-8)面に対するオフ角が-3°以上+5°以下である、請求の範囲第4項に記載の絶縁ゲート型電界効果トランジスタ(1)。
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CN2010800028219A CN102171832A (zh) | 2009-04-10 | 2010-03-23 | 绝缘栅场效应晶体管 |
CA2739576A CA2739576A1 (en) | 2009-04-10 | 2010-03-23 | Insulated gate field effect transistor |
EP10761587.4A EP2418683A4 (en) | 2009-04-10 | 2010-03-23 | FIELD EFFECT TRANSISTOR WITH INSULATED GATE |
US13/122,377 US8502236B2 (en) | 2009-04-10 | 2010-03-23 | Insulated gate field effect transistor |
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JP2012253293A (ja) * | 2011-06-07 | 2012-12-20 | Sumitomo Electric Ind Ltd | 半導体装置 |
JP6119100B2 (ja) * | 2012-02-01 | 2017-04-26 | 住友電気工業株式会社 | 炭化珪素半導体装置 |
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JP6070155B2 (ja) | 2012-12-18 | 2017-02-01 | 住友電気工業株式会社 | 炭化珪素半導体装置 |
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US20160056283A1 (en) * | 2014-08-21 | 2016-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
CN104282766A (zh) * | 2014-11-06 | 2015-01-14 | 株洲南车时代电气股份有限公司 | 一种新型碳化硅mosfet及其制造方法 |
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