WO2009104759A1 - 半導体基板、半導体素子、発光素子及び電子素子 - Google Patents
半導体基板、半導体素子、発光素子及び電子素子 Download PDFInfo
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- WO2009104759A1 WO2009104759A1 PCT/JP2009/053078 JP2009053078W WO2009104759A1 WO 2009104759 A1 WO2009104759 A1 WO 2009104759A1 JP 2009053078 W JP2009053078 W JP 2009053078W WO 2009104759 A1 WO2009104759 A1 WO 2009104759A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 239000000758 substrate Substances 0.000 title claims abstract description 79
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910002804 graphite Inorganic materials 0.000 claims abstract description 52
- 239000010439 graphite Substances 0.000 claims abstract description 52
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 229920000642 polymer Polymers 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 23
- 238000004544 sputter deposition Methods 0.000 abstract description 13
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 37
- 229910002601 GaN Inorganic materials 0.000 description 35
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 22
- 230000017525 heat dissipation Effects 0.000 description 22
- 238000005259 measurement Methods 0.000 description 17
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 15
- 238000010438 heat treatment Methods 0.000 description 12
- 238000002441 X-ray diffraction Methods 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 239000013078 crystal Substances 0.000 description 9
- 238000005424 photoluminescence Methods 0.000 description 7
- 238000001878 scanning electron micrograph Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 150000002831 nitrogen free-radicals Chemical group 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000635 electron micrograph Methods 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001579 optical reflectometry Methods 0.000 description 1
- 238000002128 reflection high energy electron diffraction Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/0641—Nitrides
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/3485—Sputtering using pulsed power to the target
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
Definitions
- the present invention relates to a semiconductor substrate, a semiconductor element, a light emitting element, and an electronic element.
- Nitride LEDs using AlN, GaN, InN, which are Group 13 nitrides, and PN junctions of mixed crystal phases thereof have been widely put into practical use. It is known that nitride-based LEDs are inorganic and have a long life and a high internal luminous efficiency (internal quantum efficiency) of 90% due to the high binding energy of the materials. These nitride-based LEDs are often mass-produced on an expensive single crystal substrate such as sapphire or silicon carbide using a low-productivity metal organic chemical vapor deposition method (MOCVD method). For this reason, it is expensive to use as a surface light source, and has been used exclusively as a point light source.
- MOCVD method metal organic chemical vapor deposition method
- an organic EL element is known as a surface light source (see, for example, Patent Document 1).
- the organic EL element can use a cheap plastic substrate or glass substrate as a starting material, so that the price of the element can be reduced and it can be used as a surface light source.
- it is expected to be used as a light-emitting element that can be bent and illumination.
- JP 2008-21480 A JP 2008-21480 A
- the light emitting layer constituting the organic EL is an organic substance, there are problems such as low heat resistance and short lifetime. Also, the luminous efficiency was lower than that of nitride LEDs.
- an object of the present invention is to provide a semiconductor substrate, a semiconductor element, a light emitting element, and an electronic element that are inexpensive, have a long lifetime, have high light emission efficiency, and can be bent. .
- a semiconductor substrate according to the present invention includes a graphite substrate having heat resistance and flexibility against an external force, and a first semiconductor layer provided on the graphite substrate and made of a group 13 nitride. It is characterized by providing.
- the graphite substrate having heat resistance and flexibility with respect to external force and the first semiconductor layer made of a group 13 nitride provided on the graphite substrate are provided.
- the first semiconductor layer can be manufactured at low cost.
- the group 13 nitride is an inorganic substance, it has a long life and high luminous efficiency can be obtained.
- the graphite substrate has flexibility with respect to external force, it can be bent. Accordingly, a semiconductor substrate that is inexpensive, has a long life, has high light emission efficiency, and can be bent can be obtained.
- the semiconductor substrate is characterized in that the graphite substrate contains a sintered polymer.
- the graphite substrate contains the sintered polymer, it has high heat resistance and can be easily bent by an external force. Since the treatment can be performed at a high temperature, the treatment can be performed at a high temperature such as a pulse sputter deposition method, a metal organic chemical vapor deposition method, or a molecular beam epitaxy method.
- the thickness of the graphite substrate is 100 ⁇ m or less. According to the present invention, since the thickness of the graphite substrate is 100 ⁇ m or less, it has extremely excellent flexibility against external force.
- the semiconductor substrate further includes a second semiconductor layer provided between the graphite substrate and the first semiconductor layer and including at least one of HfN (halfnium nitride) and ZrN (zirconium nitride). It is characterized by. HfN and ZrN are known to have high light reflectance. According to the present invention, since the second semiconductor layer including at least one of HfN and ZrN is further provided between the graphite substrate and the first semiconductor layer, light is reflected by the second semiconductor layer. Can do. Thereby, when using a 1st semiconductor layer as a light emitting layer, the utilization efficiency of the light from the said light emitting layer can be improved.
- the semiconductor substrate further includes a third semiconductor layer provided between the graphite substrate and the first semiconductor layer and containing AlN (aluminum nitride).
- a third semiconductor layer provided between the graphite substrate and the first semiconductor layer and containing AlN (aluminum nitride).
- AlN aluminum nitride
- the grain size of the first semiconductor layer can be increased.
- the electrical characteristics of the first semiconductor layer can be enhanced.
- the optical characteristics of the first semiconductor layer can also be enhanced.
- a semiconductor element according to the present invention is characterized by including the above-described semiconductor substrate. According to the present invention, it is possible to obtain a semiconductor element that can be used in a wider range of fields than a conventional one provided with a semiconductor substrate that is inexpensive, has a long lifetime, has high luminous efficiency, and can be bent.
- a light-emitting element according to the present invention includes the above-described semiconductor element. According to the present invention, a long-life element capable of surface light emission with flexibility can be obtained at low cost.
- An electronic device includes the semiconductor device described above. According to the present invention, an element having flexibility and high electrical characteristics can be obtained at low cost.
- a semiconductor substrate, a semiconductor element, a light emitting element, and an electronic element that are inexpensive, have a long lifetime, have high luminous efficiency, and can be bent.
- FIG. 1 is a diagram showing a configuration of a semiconductor substrate 1 according to the present embodiment.
- the semiconductor substrate 1 has a configuration in which a buffer layer 3 is provided on a heat dissipation sheet 2 and a semiconductor layer 4 is laminated on the buffer layer 3.
- the semiconductor substrate 1 is mounted on a light emitting element or an electronic element.
- the heat dissipation sheet 2 is made of, for example, a graphite film prepared by sintering a polymer such as polyoxadiazole at about 3000 ° C.
- the graphite film has a thermal conductivity of about 1700 W / m ⁇ K in the in-plane direction, and the value of this thermal conductivity is about four times that of Cu. Moreover, since it has high heat resistance, it can be processed even at high temperatures. Furthermore, it has a high electrical conductivity of about 5 ⁇ 10 ⁇ 5 S / cm in the in-plane direction of the film. Since this graphite film is as thin as 25 ⁇ m to 100 ⁇ m, it has flexibility against external forces. For this reason, it can be bent.
- the graphite sheet 2 can have a large area of 50 cm 2 or more.
- the buffer layer 3 is a layer made of, for example, zirconium nitride (ZrN (111)), and is interposed between the heat dissipation sheet 2 and the semiconductor layer 4.
- FIG. 2 is a graph showing the light reflectance of zirconium nitride. The horizontal axis of the graph indicates the wavelength, and the vertical axis of the graph indicates the light reflectance.
- FIG. 3 is a table showing the correspondence between the light reflectance of zirconium nitride and the wavelength of the light.
- the light reflectance at 470 nm which is the wavelength range of blue light in zirconium nitride is 65.6%. Based on this, it can be said that the buffer layer 3 made of zirconium nitride can reflect almost 65% or more of light when irradiated with blue light.
- the semiconductor layer 4 is a semiconductor layer made of, for example, a group 13 nitride semiconductor.
- group 13 nitride include GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and the like, and have a general formula of In X Ga Y Al 1-XY N (0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1, 0 ⁇ X + Y ⁇ 1).
- FIG. 4 is a diagram showing a configuration of a sputtering apparatus which is a manufacturing apparatus for the semiconductor layer 4 and the buffer layer 3 described above.
- the sputtering apparatus 10 is mainly composed of a chamber 11, a substrate electrode 12, a target electrode 13, a DC power supply 14, a power supply control unit 15, a nitrogen supply source 16, and a heating device 17. Has been.
- the chamber 11 is provided so that it can be sealed with respect to the outside.
- the inside of the chamber 11 can be decompressed by a vacuum pump (not shown).
- the substrate electrode 12 is disposed in the chamber 11 and can hold the heat dissipation sheet 2.
- the target electrode 13 is provided in the chamber 11 so as to face the substrate electrode 12, and can hold the target 13a.
- the target 13a is made of, for example, Zr (zirconium) or an alloy thereof.
- the DC power supply 14 is a voltage source that is electrically connected to the substrate electrode 12 and the target electrode 13 and applies a DC voltage between the substrate electrode 12 and the target electrode 13.
- the control unit 15 is connected to the DC power supply 14 and performs control related to the operation timing of the DC power supply 14.
- the control unit 15 can apply a pulse voltage between the substrate electrode 12 and the target electrode 13.
- the nitrogen supply source 16 is connected to the inside of the chamber 11 by, for example, a supply pipe and supplies nitrogen gas into the chamber 11.
- an argon gas supply source for supplying argon gas into the chamber is also provided.
- the heating device 17 is fixed to the substrate electrode 12, for example, and can adjust the ambient temperature of the heat dissipation sheet 2 on the substrate electrode 12.
- a process for manufacturing the semiconductor substrate 1 according to this embodiment using the sputtering apparatus 10 will be described.
- a PSD method pulse sputter deposition method
- a pulse DC voltage is applied between a substrate and a target
- the semiconductor thin film is formed on the heat dissipation sheet 2 capable of increasing the area, it can be said that the PSD method is significant.
- argon gas is supplied into the chamber 11, and nitrogen gas is supplied into the chamber 11 from the nitrogen supply source 16. After the inside of the chamber 11 reaches a predetermined pressure by the argon gas and the nitrogen gas, the heat radiation sheet 2 is held on the substrate electrode 12 and the target 13 a is placed on the target electrode 13.
- the ambient temperature of the heat dissipation sheet 2 is adjusted by the heating device 17.
- a DC pulse voltage is applied between the substrate electrode 12 and the target electrode 13.
- a large amount of high-energy Zr atoms is supplied onto the heat dissipation sheet 2, and the surface of the heat dissipation sheet 2 is in a metal-rich state.
- Zr atoms on the heat dissipation sheet 2 migrate to stable lattice positions.
- Zr atoms migrated to a stable lattice position react with nitrogen radicals activated in the chamber 11 to form a metal nitride (ZrN) crystal.
- ZrN metal nitride
- the semiconductor layer 4 is formed on the formed buffer layer 3 by the same method. In this way, the semiconductor substrate 1 shown in FIG. 1 is completed.
- a method such as a pulse sputter deposition method can be used when forming the semiconductor layer 4 on the heat dissipation sheet 2 made of a graphite film that can be processed at a high temperature. it can.
- the group 13 nitride is an inorganic substance, it has a long life and high luminous efficiency can be obtained.
- the heat dissipation sheet 2 has flexibility with respect to external force, it can be bent. Accordingly, a semiconductor substrate that is inexpensive, has a long life, has high light emission efficiency, and can be bent can be obtained.
- the heat-dissipating sheet 2 is sintered at about 3000 ° C. as a polymer, such as polyoxadiazole, as an example of the “graphite substrate having heat resistance and flexibility against external force” of the present invention.
- a polymer such as polyoxadiazole
- the present invention is not limited to this.
- any substrate may be used as long as it has heat resistance and is flexible to external force, which is configured by laminating a graphite layer on a substrate other than graphite. Further, it can withstand a temperature environment of 600 ° C.
- the “graphite substrate having heat resistance and flexibility to external force” of the present invention is a graphite having a structure close to a single crystal made by a method of graphitizing a polymer by thermal decomposition, and has high thermal conductivity. It is particularly preferable that the graphite film is used as a heat conductive sheet and has features such as flexibility with respect to external force.
- the buffer layer 3 and the semiconductor layer 4 are formed by the pulse sputtering method, it is not restricted to this,
- PLD method pulse laser deposition method
- PED method pulse electron beam deposition
- PXD method Pulsed Excitation Deposition
- metal organic growth method molecular beam epitaxy method, or other thin film forming methods.
- the buffer layer 3 made of ZrN (111) is formed on the heat radiating sheet 2.
- the present invention is not limited to this.
- the buffer layer 3 made of HfN (111) It may be configured to form.
- the semiconductor layer 4 may be grown directly on the heat dissipation sheet 2 without forming the buffer layer 3, or the semiconductor layer 4 may be stacked (for example, GaN layer / AlN layer / graphite, etc.) ).
- Example 1 according to the present invention will be described.
- the heat-dissipating sheet 2 used in the above embodiment was observed by XRD measurement and electron microscope (SEM).
- FIG. 5 is a graph showing the results of XRD measurement for the heat dissipation sheet 2 described in the above embodiment.
- the graphite constituting the heat-dissipating sheet 2 shows a strong orientation at (002) and (004), and can be said to be a high-quality single crystal.
- FIG. 6A and 6B are electron micrographs of the surface of the heat dissipation sheet 2 described in the above embodiment.
- FIG. 6B is an enlarged photograph of one of the grains in FIG.
- the grain size of graphite is 10 ⁇ m or more, and it can be seen that the crystallinity is high.
- FIG. 6B it can be seen that the surface has no irregularities and is flat.
- an AlN layer was formed on the heat dissipation sheet 2 by the method of the above embodiment (pulse sputtering method), and a GaN layer was further formed on the AlN layer.
- heating was performed at a temperature of about 1000 ° C. to 1200 ° C., and the heating time was about 30 min to 60 min.
- heating was performed at a temperature of about 650 ° C. to 750 ° C., and the heating time was set to 60 min to 120 min.
- FIG. 7 is a graph showing measurement results by XRD for the graphite layer and the AlN layer. As shown in the figure, the graphite layer grows in the (002) direction, the AlN layer grows in the (0002) direction, and the AlN layer is recognized to exhibit c-axis orientation.
- FIG. 8 is an EBSD measurement diagram of the AlN layer. As shown in the figure, it can be seen that many crystals having a grain size of 1 ⁇ m or more are formed in the AlN layer.
- FIG. 9 is a ⁇ 10-12 ⁇ EBSD pole figure for a portion of the AlN layer. As shown in the figure, a clear pattern is recognized on the apex of the regular hexagon. This shows that the crystallinity of the AlN layer is good.
- FIG. 10 is a graph showing measurement results by XRD for the graphite layer and the GaN layer. As shown in the figure, the GaN layer grows in the (0002) direction like the AlN layer, and it is recognized that it exhibits c-axis orientation.
- FIG. 11 is an SEM image of the surface of the GaN layer. As shown in the figure, it can be seen that the surface of the GaN layer has no particularly large irregularities and is formed on a relatively flat surface.
- FIG. 12 is an EBSD measurement diagram of the GaN layer. As shown in the figure, it is understood that many crystals having a grain size of 1 ⁇ m or more are formed in the GaN layer.
- FIG. 13 is an EBSD pole figure of the GaN layer.
- FIG. 13A is a ⁇ 10-12 ⁇ EBSD pole figure for a part of the GaN layer
- FIG. 13B is a ⁇ 10-12 ⁇ EBSD pole figure for the other part of the GaN layer.
- a clear pattern is recognized on the apex of the regular hexagon. This indicates that each grain has high crystallinity.
- FIG. 14 is a graph showing the results of PL measurement of the GaN layer at room temperature.
- FIG. 15 is a graph showing the results of PL measurement at room temperature of GaN produced by conventional MOCVD.
- the vertical axis of the graph is the PL intensity
- the horizontal axis of the graph is the emission energy.
- FIG. 14 in the GaN layer obtained in this example, a strong peak is observed when the emission energy is around 3.4 eV. It was 63 meV when the half width of this peak was measured.
- FIG. 15 in the conventional GaN substrate, a strong peak is recognized in the vicinity of 3.4 eV. It was 66 meV when the half value width of this peak was measured. Comparing the results of FIGS. 14 and 15, it can be seen that the light emission characteristics of the GaN layer obtained in this example are equal to or higher than the light emission characteristics of the conventional GaN substrate.
- an HfN layer was formed on the heat dissipation sheet 2 by the method of the above embodiment (pulse sputtering method), and a GaN layer was further formed on the HfN layer.
- heating was performed at a temperature of about 1000 ° C. to 1200 ° C., and the heating time was about 30 min to 60 min.
- heating was performed at a temperature of about 650 ° C. to 750 ° C., and the heating time was set to 60 min to 120 min.
- the semiconductor substrate (GaN / HfN / graphite) thus prepared was evaluated by evaluation methods of X-ray diffraction (XRD), scanning electron microscope (SEM), and electron beam backscatter diffraction (EBSD).
- XRD X-ray diffraction
- SEM scanning electron microscope
- EBSD electron beam backscatter diffraction
- FIG. 16 is an SEM image of the surface of the HfN layer. As shown in the figure, it can be seen that the surface of the HfN layer has no particularly large irregularities and is formed on a relatively flat surface.
- FIG. 17 is a graph showing measurement results by XRD for the graphite layer and the HfN layer. As shown in the figure, it is recognized that the graphite layer grows in the (002) direction and the HfN layer grows in the (111) direction. From these results, it can be seen that the HfN layer has good crystallinity and it is possible to grow an HfN thin film having a high (111) orientation on the graphite sheet.
- FIG. 18 is an SEM image of the surface of the GaN layer. As shown in the figure, it can be seen that the surface of the GaN layer has no particularly large irregularities and is formed on a relatively flat surface.
- FIG. 19 is a ⁇ 10-12 ⁇ EBSD pole figure for the other part of the GaN layer. As shown in FIG. 19, a clear pattern is recognized on the regular hexagonal apex. This indicates that each grain has high crystallinity. It can be seen that a high-quality GaN thin film can be grown on the graphite sheet by using the HfN buffer layer.
Abstract
Description
本願は、2008年2月21日に、日本に出願された特願2008-039672号に基づき優先権を主張し、その内容をここに援用する。
本発明によれば、グラファイト基板が焼結されたポリマーを含んでいることとしたので、耐熱性が高く、外力によって容易に曲げることが可能である。高温下で処理を行うことも可能であるため、パルススパッタ堆積法や有機金属気相成長法、分子線エピタキシー法など高温下で行う処理が可能となる。
本発明によれば、グラファイト基板の厚さが100μm以下であるとしたので、外力に対して極めて優れた可撓性を有することとなる。
HfN及びZrNは高い光反射率を有することが知られている。本発明によれば、グラファイト基板と第1半導体層との間に、HfN及びZrNのうち少なくとも一方を含む第2半導体層を更に備えることとしたので、当該第2半導体層によって光を反射することができる。これにより、第1半導体層を発光層として用いる場合、当該発光層からの光の利用効率を高めることができる。
本発明によれば、グラファイト基板と第1半導体層との間に、AlNを含む第3半導体層を更に備えることとしたので、第1半導体層のグレインサイズを増大させることができる。これにより、第1半導体層の電気的特性を高めることができ、特に第1半導体層を発光層として用いる場合には当該第1半導体層の光学特性についても高めることができる。
本発明によれば、安価で、長寿命であり、発光効率が高く、しかも曲げることが可能な半導体基板を備える従来に比べて広い分野で利用可能な半導体素子を得ることができる。
本発明によれば、柔軟性を持ち面発光が可能な長寿命の素子を安価で得ることができる。
本発明によれば、柔軟性を持ち電気的特性の高い素子を安価で得ることができる。
図1は、本実施形態に係る半導体基板1の構成を示す図である。
同図に示すように、半導体基板1は、放熱シート2上にバッファ層3が設けられ、当該バッファ層3上に半導体層4が積層された構成になっている。この半導体基板1は、発光素子や電子素子などに搭載される。
このグラファイトフィルムは、厚さが25μm~100μm程度と薄いため外力に対する可撓性を有することとなる。このため、曲げることができるようになっている。グラファイトシート2は50cm2以上の大面積化が可能である。
図3は、ジルコニウムナイトライドの光反射率と当該光の波長との対応関係を示す表である。
同図に示すように、スパッタ装置10は、チャンバ11と、基板電極12と、ターゲット電極13と、直流電源14と、電源制御部15と、窒素供給源16と、加熱装置17を主体として構成されている。
基板電極12は、チャンバ11内に配置されており、上記の放熱シート2を保持可能になっている。
制御部15は、直流電源14に接続されており、直流電源14の動作のタイミングに関する制御を行う。制御部15により、基板電極12とターゲット電極13との間にパルス電圧を印加することが可能になっている。
加熱装置17は、例えば基板電極12に固定されており、基板電極12上の放熱シート2の周囲温度を調節できるようになっている。
例えば、上記実施形態では、放熱シート2は、本発明の「耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板」の一例として、ポリオキサジアゾールなどのポリマーを約3000℃程度で焼結させて作製したグラファイトフィルムからなるが、これに限られることはない。例えば、基板の片面がグラファイト構造であれば、グラファイト以外の基板上にグラファイト層を積層して構成された耐熱性を有すると共に外力に対する可撓性を有する基板であれば、構わない。また、600℃以上、好ましくは1200℃以上、さらに好ましくは2000℃以上の温度環境にも耐えることができると共に、基板の両端に外力を加える場合には120度以下、好ましくは90度以下、さらに好ましくは60度以下の角度で曲げることができるグラファイト基板であれば構わない。また、本発明の「耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板」は、ポリマーを熱分解によりグラファイト化する方法で作られた単結晶に近い構造を持つグラファイトで,高い熱伝導性と外力に対する可撓性などの特長を持った、熱伝導シートとして使われているグラファイトフィルムであることが特に好ましい。
また、上記実施形態では、バッファ層3及び半導体層4をパルススパッタ法によって形成しているが、これに限られることはなく、例えばPLD法(パルスレーザ堆積法)やPED法(パルス電子線堆積法)を含むPXD法(Pulsed Excitation Deposition:パルス励起堆積法)有機金属成長法、分子線エピタキシー法など、他の薄膜形成方法によって形成しても構わない。
図5は、上記実施形態で説明した放熱シート2についてのXRD測定の結果を示すグラフである。
同図に示すように、放熱シート2を構成するグラファイトは(002)及び(004)に強い配向を示しており、高品質な単結晶であるといえる。
図6(a)に示すように、グラファイトのグレインサイズは10μm以上となっており、結晶性が高いことが分かる。図6(b)に示すように、表面に凹凸が見られず、平坦になっていることが分かる。
同図に示すように、グラファイト層は(002)方向に成長しており、AlN層は(0002)方向に成長しており、AlN層はc軸配向性を示していると認められる。
同図に示すように、AlN層には1μm以上のグレインサイズを有する結晶が多く形成されていることが分かる。
同図に示すように、正六角形の頂点上に明確なパターンが認められる。このことからAlN層の結晶性が良好であることが分かる。
同図に示すように、GaN層はAlN層と同様に(0002)方向に成長しており、c軸配向性を示していると認められる。
同図に示すように、GaN層の表面には特段に大きな凹凸は見られず、比較的平坦な表面に形成されていることが分かる。
同図に示すように、GaN層には1μm以上のグレインサイズを有する結晶が多く形成されていることがわかる。
図13(a)及び図13(b)に示すように、正六角形の頂点上に明確なパターンが認められる。このことからそれぞれのグレインは高い結晶性を有していることが分かる。
図14に示すように、本実施例で得られたGaN層については、発光エネルギーが3.4eV付近において強いピークが認められる。このピークの半値幅を測定したら、63meVであった。また、図15に示すように、従来のGaN基板については、3.4eV付近において強いピークが認められる。このピークの半値幅を測定したら、66meVであった。図14と図15との結果とを比較すると、本実施例で得られたGaN層の発光特性は、従来のGaN基板の発光特性に比べて同等以上であることが分かる。
同図に示すように、HfN層の表面には特段に大きな凹凸は見られず、比較的平坦な表面に形成されていることが分かる。
同図に示すように、グラファイト層は(002)方向に成長しており、HfN層は(111)方向に成長しておると認められる。 これらの結果からHfN層の結晶性が良好でありグラファイトシート上に高い(111)配向性を有したHfN薄膜の成長が可能であることが分かる。
同図に示すように、GaN層の表面には特段に大きな凹凸は見られず、比較的平坦な表面に形成されていることが分かる。
図19に示すように、正六角形の頂点上に明確なパターンが認められる。このことからそれぞれのグレインは高い結晶性を有していることが分かる。
HfNバッファー層を用いることで、グラファイトシート上に良質なGaN薄膜を成長可能であることが分かる。
Claims (8)
- 耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板と、
前記グラファイト基板上に設けられ、13属窒化物からなる第1半導体層と
を備えることを特徴とする半導体基板。 - 前記グラファイト基板は、焼結されたポリマーを含んでいる
ことを特徴とする請求項1に記載の半導体基板。 - 前記グラファイト基板の厚さは100μm以下である
ことを特徴とする請求項1又は請求項2に記載の半導体基板。 - 前記グラファイト基板と前記第1半導体層との間に設けられ、HfN及びZrNのうち少なくとも一方を含む第2半導体層を更に備える
ことを特徴とする請求項1から請求項3のうちいずれか一項に記載の半導体基板。 - 前記グラファイト基板と前記第1半導体層との間に設けられ、AlNを含む第3半導体層を更に備える
ことを特徴とする請求項1から請求項4のうちいずれか一項に記載の半導体基板。 - 請求項1から請求項5のうちいずれか一項に記載の半導体基板を備えることを特長とする半導体素子。
- 請求項6に記載の半導体素子を備えることを特徴とする発光素子。
- 請求項6に記載の半導体素子を備えることを特徴とする電子素子。
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- 2009-02-20 WO PCT/JP2009/053078 patent/WO2009104759A1/ja active Application Filing
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102482797A (zh) * | 2009-09-07 | 2012-05-30 | 国立大学法人东京大学 | 半导体基板、半导体基板的制造方法、半导体生长用基板、半导体生长用基板的制造方法、半导体元件、发光元件、显示面板、电子元件、太阳能电池元件及电子设备 |
EP2476787A1 (en) * | 2009-09-07 | 2012-07-18 | The University of Tokyo | Semiconductor substrate, method for producing semiconductor substrate, substrate for semiconductor growth, method for producing substrate for semiconductor growth, semiconductor element, light-emitting element, display panel, electronic element, solar cell element, and electronic device |
EP2476787A4 (en) * | 2009-09-07 | 2014-12-31 | Univ Tokyo | SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SUBSTRATE FOR GROWING SEMICONDUCTORS, METHOD FOR MANUFACTURING SUBSTRATE FOR GROWING SEMICONDUCTORS, SEMICONDUCTOR ELEMENT, LIGHT EMITTING ELEMENT, D-PANEL DISPLAY, ELECTRONIC ELEMENT, SOLAR CELL ELEMENT, AND ELECTRONIC DEVICE |
US9000449B2 (en) | 2009-09-07 | 2015-04-07 | The University Of Tokyo | Semiconductor substrate, method for producing semiconductor substrate, substrate for semiconductor growth, method for producing substrate for semiconductor growth, semiconductor element, light-emitting element, display panel, electronic element, solar cell element, and electronic device |
CN102326266A (zh) * | 2009-10-20 | 2012-01-18 | 松下电器产业株式会社 | 发光二极管元件及其制造方法 |
Also Published As
Publication number | Publication date |
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EP2246910A4 (en) | 2014-03-19 |
EP2246910A1 (en) | 2010-11-03 |
EP2246910B1 (en) | 2019-03-27 |
US8212335B2 (en) | 2012-07-03 |
US20100320450A1 (en) | 2010-12-23 |
CN101952984B (zh) | 2012-08-08 |
JP5386747B2 (ja) | 2014-01-15 |
CN101952984A (zh) | 2011-01-19 |
KR101164107B1 (ko) | 2012-07-12 |
JP2009200207A (ja) | 2009-09-03 |
KR20100099347A (ko) | 2010-09-10 |
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