WO2009090878A1 - 多層プリント配線板およびそれを用いた実装体 - Google Patents
多層プリント配線板およびそれを用いた実装体 Download PDFInfo
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- WO2009090878A1 WO2009090878A1 PCT/JP2009/000137 JP2009000137W WO2009090878A1 WO 2009090878 A1 WO2009090878 A1 WO 2009090878A1 JP 2009000137 W JP2009000137 W JP 2009000137W WO 2009090878 A1 WO2009090878 A1 WO 2009090878A1
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- printed wiring
- wiring board
- multilayer printed
- connection layer
- relaxation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0133—Elastomeric or compliant polymer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10121—Optical component, e.g. opto-electronic component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
Definitions
- the present invention relates to a multilayer printed wiring board widely used for various electronic devices such as personal computers, mobile phones for mobile communication, video cameras and the like, and a mounting body using the same.
- Patent Document 1 proposes a component built-in module and a camera module using a multilayer circuit board. Such component built-in modules and camera modules are mounted and used on a mother board as another circuit board. However, since such component built-in modules and camera modules are expensive, it is required to use an inexpensive circuit board.
- FIG. 11 is a cross-sectional view showing a mounting body in which the camera module proposed in Patent Document 1 and manufactured using a conventional multilayer circuit board is mounted on a multilayer printed wiring board.
- FIG. 11 is a cross-sectional view showing a camera module mounting body in which the multilayer printed wiring board P2 for a camera module is mounted on the multilayer printed wiring board P1.
- the multilayer printed wiring board P1 is, for example, a mother board of a mobile phone, which is made of, for example, a laminate of glass fiber and an epoxy resin.
- the multilayer printed wiring board P2 is, for example, a multilayer printed wiring board for a camera module of several millimeters square.
- the multilayer printed wiring board P2 may be for a component-embedded module.
- the wirings 1 of a plurality of layers are stacked via the insulating layer 2.
- the wiring 1 is connected by a via 3 which is an interlayer connection.
- the large-sized multilayer printed wiring board P1 and the small-sized multilayer printed wiring board P2 are connected via solder balls (not shown).
- An imaging element 5 such as a CCD is fixed on the surface of the multilayer printed wiring board P2 to be a camera module so as to be surrounded by the holder 4.
- the imaging element 5 and the wiring 1 of the multilayer printed wiring board P2 are connected by a wire 2a or the like.
- a lens 6 having an optical axis 7 is fixed on the holder 4.
- the external light 7 a projects a predetermined image on the image sensor 5 through the lens 6 as indicated by the arrow.
- the holder 4 has a configuration capable of realizing autofocus.
- FIG. 12 is a cross-sectional view for explaining a problem when warpage occurs in the multilayer printed wiring boards P1 and P2.
- warpage 8 easily occurs due to the difference in the material used for the multilayer printed wiring boards P1 and P2 and the thermal expansion coefficient.
- the warpage 8 means that the planarity is low, and includes undulation and distortion.
- such a warp 8 peels off a connecting portion between a large multilayer printed wiring board P1 and a small multilayer printed wiring board P2, for example, a BGA (Ball Grid Array) connecting portion using solder balls 9a. Occurs.
- a gap 9 b is generated between the small-sized multilayer printed wiring board P 2 and the holder 4.
- an optical system such as the lens 6 is affected.
- the optical axis 7b the optical axis 7 of the lens 6 is shifted, and the focus (or focus or focus) of the lens 6 is shifted.
- the conventional multilayer printed wiring board and a mounting body such as a camera module using the same have the problem that the optical axis is shifted or connection failure occurs due to warping or twisting of the multilayer printed wiring board itself. It was JP 2007-165460 A
- the present invention has been made in view of the above problems, and is a multilayer printed wiring board capable of preventing the occurrence of optical deviation or wiring connection failure caused by the warp of a conventional multilayer printed wiring board. And an implementation using the same.
- the present invention is based on a plurality of printed wiring boards in which wiring is formed on the surface layer, and a relaxation connection layer connecting between the plurality of printed wiring boards and having an inorganic filler, a thermosetting resin and a relaxation material for relieving internal stress.
- Such a configuration makes it possible to prevent warpage and waviness caused by differences in material and thermal expansion coefficient. In addition, it is possible to realize high precision, low cost and light weight of a package using such a multilayer printed wiring board.
- FIG. 1 is a cross-sectional view of a mounting body using a multilayer printed wiring board according to Embodiment 1 of the present invention.
- FIG. 2A is a process cross-sectional view illustrating an example of the method of manufacturing the multilayer printed wiring board in Embodiment 1 of the present invention.
- FIG. 2: B is process sectional drawing explaining an example of the manufacturing method of the multilayer printed wiring board in Embodiment 1 of this invention.
- FIG. 3 is a view showing a melt viscosity curve of the relaxation connection layer of the multilayer printed wiring board in Embodiment 1 of the present invention.
- FIG. 4A is a cross-sectional view showing the multilayer printed wiring board shown in FIG.
- FIG. 4B is a partially enlarged cross-sectional view of FIG. 4A.
- FIG. 4C is a cross-sectional view showing another example of the multilayer printed wiring board shown in FIG.
- FIG. 5A is a cross-sectional view for describing a mechanism for suppressing the occurrence of warpage in the multilayer printed wiring board of Embodiment 1.
- FIG. 5B is a cross-sectional view describing a mechanism for suppressing the occurrence of warpage in the multilayer printed wiring board of Embodiment 1.
- FIG. 5C is a cross-sectional view describing a mechanism for suppressing the occurrence of warpage in the multilayer printed wiring board of Embodiment 1.
- FIG. 6A is a cross-sectional view for describing a mechanism for suppressing the occurrence of warpage in the multilayer printed wiring board of the first embodiment.
- FIG. 5A is a cross-sectional view for describing a mechanism for suppressing the occurrence of warpage in the multilayer printed wiring board of the first embodiment.
- FIG. 6B is a cross-sectional view for explaining a mechanism for suppressing the occurrence of warpage in the multilayer printed wiring board of the first embodiment.
- FIG. 6C is a cross-sectional view describing a mechanism for suppressing the occurrence of warpage in the multilayer printed wiring board of Embodiment 1.
- FIG. 7A is a cross-sectional view for explaining the method for manufacturing the POP which is a mounting body using a multilayer printed wiring board according to Embodiment 2 of the present invention.
- FIG. 7B is a cross-sectional view for explaining the method for manufacturing the POP which is a mounting body using a multilayer printed wiring board according to Embodiment 2 of the present invention.
- FIG. 8A is a cross sectional view for illustrating a manufacturing process of the POP in the second embodiment of the present invention.
- FIG. 8B is a cross sectional view for illustrating the manufacturing process of the POP in the second embodiment of the present invention.
- FIG. 9A is a cross-sectional view for explaining the influence of warpage in the POP.
- FIG. 9B is a cross-sectional view for explaining the influence of warpage in the POP.
- FIG. 10A is a cross-sectional view for explaining an optical module which is a mounting body using a multilayer printed wiring board according to Embodiment 3 of the present invention.
- FIG. 10B is a cross-sectional view for explaining an optical module which is a mounting body using a multilayer printed wiring board according to Embodiment 3 of the present invention.
- FIG. 11 is a cross-sectional view showing a mounting body using a conventional multilayer printed wiring board.
- FIG. 12 is a cross-sectional view for explaining a problem when warpage occurs in the conventional multilayer printed wiring board.
- Multilayer printed wiring board 12 12a, 12b Wiring 13 Via 14 Insulating layer 15 Relaxation connection layer 16, 16a, 16b, 16c Mounting body 17 Holder 18 Imaging device 19 Lens 20 Optical axis 21a, 21b Printed wiring board 22 Wire 23 Adhesive layer 24 warpage 24a, 24b, 24c internal stress 25 semiconductor element 26, 26a, 26b solder ball 27 disconnection
- Embodiment 1 The first embodiment of the present invention will be described below with reference to the drawings.
- FIG. 1 is a cross-sectional view of a mounting body using a multilayer printed wiring board according to Embodiment 1 of the present invention.
- the multilayer printed wiring board 11 is an inorganic filler and a thermosetting resin for connecting the plurality of printed wiring boards 21a and 21b having the wiring 12 formed on the surface and the printed wiring boards 21a and 21b. It is comprised from the relaxation connection layer 15 which consists of a relaxation material which relieves stress.
- the printed wiring board 21 a has the wiring 12 formed of the copper foil pattern on the surface layer of the front and back surfaces of the insulating layer 14.
- the insulating layer 14 is formed, for example, by curing a glass fiber impregnated with an epoxy resin.
- the printed wiring board 21 a is provided with a holder 17 and an imaging device 18 surrounded by the holder 17 in the surface layer of the upper surface as in the conventional case.
- a lens 19 having an optical axis 20 is held above the holder 17.
- the holder 17 is provided with an auto focus function (not shown) of the lens 17.
- the wiring 12 formed in the imaging element 18 and the wiring 12 formed in the printed wiring board 21 a are connected by a bonder with a wire 22 such as a gold wire or an aluminum wire.
- the wirings 12 formed in the surface layer of the front and back surfaces are electrically connected by vias 13 penetrating the multilayer printed wiring board 11.
- the printed wiring board 21 b is formed of a laminate in which a plurality of printed wiring boards having the wirings 12 formed on the front and back surfaces of each of the printed wiring boards 21 b have the insulating layer 14 interposed therebetween. That is, the printed wiring board 21b itself is also a multilayer printed wiring board.
- the interconnections 12 inside the printed wiring board 21 b and the interconnections 12 formed on the surface layers of the front and back surfaces are electrically connected to each other in the vertical direction by vias 13 formed in the insulating layer 14.
- the relaxation connection layer 15 is an inorganic filler and a thermal relaxation material that relieves internal stress that occurs during heating and cooling that occurs during component mounting of the multilayer printed wiring board 11 (for example, during solder reflow). It is contained in the curable resin.
- the wires 12 on the surface layer of the printed wiring boards 21 a and 21 b are buried on the relaxed connection layer 15 side.
- the thickness of the relaxed connection layer 15 is 30 to 300 ⁇ m.
- the multilayer printed wiring board 11 has the relaxed connection layer 15 in the inner layer, so that warpage hardly occurs on the surface.
- a lens 19, a holder 17 and the like are mounted on the upper surface of the multilayer printed wiring board 11 to form a mounting body 16 of the camera module.
- the camera module is, for example, a high definition module of 2 million pixels or more in a mobile phone. That is, in the present embodiment, members mounted on the printed wiring board 21a, such as the holder 17, the imaging device 18, and the lens 19, are the mounting members.
- the mounting body 16 may be, for example, a package on package (POP) or an optical module in addition to the camera module.
- POP is configured, for example, by connecting a plurality of multilayer printed wiring boards.
- the optical module is configured, for example, by forming a composite of an optical cable and a circuit component on the surface of a multilayer printed wiring board.
- the optical module is formed of a light guide formed on the surface of the multilayer printed wiring board, or an optical electronic module using an LED (light emitting diode) or a semiconductor laser.
- FIGS. 2A and 2B are cross-sectional views for explaining the method of manufacturing a multilayer printed wiring board of the present embodiment.
- the printed wiring board 21a with the wiring 12 formed on the front and back, the multilayer printed wiring board 21b consisting of the multilayer wiring 12 and the multilayer insulating layer 14, and the via Prepare the through connection with the relaxed connection layer 15.
- the predetermined wirings 12 on the front and back surfaces of the printed wiring board 21 a are connected by vias 13 in the insulating layer 14.
- the interconnections 12 inside and on the surface layer of the printed wiring board 21 b are also interlayer connected by the vias 13 in the insulating layer 14.
- the vias 13 of the relaxed connection layer 15 are provided at positions corresponding to the wirings 12 to be connected, which are formed on the surface layers of the printed wiring boards 21a and 21b.
- a printed wiring board (also referred to as a glass epoxy substrate) formed by curing glass fiber with an epoxy resin, a printed wiring board formed by curing an aramid fiber or the like with an epoxy resin, or the like is used.
- a printed wiring board 21a in addition to the single-sided double-sided printed wiring board, a multilayer printed wiring board of two or more layers can be used.
- vias 13 formed in the printed wiring boards 21a and 21b vias (filled vias or plated through holes) by plating or the like may be used in addition to the conductive paste described later.
- the relaxation connection layer 15 is an insulating layer composed of an inorganic filler, a thermosetting resin, and a relaxation material. Holes are previously formed in the relaxed connection layer 15 by laser or drill. By filling the holes with a conductive paste (for example, a via paste made of copper powder and an epoxy resin), the vias 13 can be formed as shown in FIG. 2A.
- the thickness of the relaxing connection layer 15 is set in the range of 30 to 300 ⁇ m.
- the relaxing connection layer 15 is sandwiched between a plurality of printed wiring boards 21a and 21b, and heating and pressing are performed as indicated by arrows.
- the relaxed connection layer 15 is softened by heating and pressing to enhance the adhesion to the printed wiring boards 21a and 21b.
- the wiring formed on the surface layer facing the relaxed connection layer 15 of the printed wiring boards 21a and 21b is referred to as 12a.
- the thickness of the wiring 12 a is positively bite into and embedded in the relaxed connection layer 15 side, thereby enhancing the electrical connectivity between the via 13 formed in the relaxed connection layer 15 and the wiring 12 a and reducing the electrical resistance. .
- the vias 13 are made to project by using, for example, a PET (polyethylene terephthalate) film on the surface of the relaxation connection layer 15 as described later.
- a PET polyethylene terephthalate
- FIG. 2B is a cross-sectional view of multilayer printed wiring board 11 obtained by the process shown in FIG. 2A.
- the wiring 12a formed on the surface layer of the printed wiring boards 21a and 21b is embedded in the via 13 formed in the relaxed connection layer 15 by heating and pressurizing as shown by the arrows. That is, only the thickness of the wiring 12 a is buried in the via 13 of the relaxing connection layer 15. As a result, the electrical connectivity between the wiring 12 a and the via 13 of the relaxed connection layer 15 is enhanced.
- the mounting body 16 of the mobile phone camera module shown in FIG. 1 can be obtained.
- the relaxation connection layer 15 in the present embodiment is formed of an insulating layer in which an inorganic filler and a relaxation material are dispersed in a thermosetting resin such as an epoxy resin.
- a relaxation material thermoplastic resins such as elastomers or rubbers may be mentioned.
- the thickness of the relaxed connection layer 15 is preferably 30 to 300 ⁇ m. If it is less than 30 ⁇ m, the interconnection 12 is not sufficiently embedded, and the connectivity between the via 13 and the interconnection 12 is deteriorated. If it exceeds 300 ⁇ m, miniaturization of the via 13 for maintaining the aspect ratio of the via 13 becomes difficult, or the connectivity between the via 13 and the wiring 12 is deteriorated due to the thickening.
- the relaxation connection layer 15 is an insulating layer, it generally includes a core material such as a woven fabric, a non-woven fabric, or a film. However, in the present embodiment, those having less core material such as woven fabric, non-woven fabric, film and the like are used. Even if it contains a core material, 5 wt% or less is desirable. This is because when the core material is contained in an amount of more than 5 wt%, the core material may be a hindrance to internal stress relaxation, and the effect of preventing the warpage of the relaxation connection layer 15 may be reduced.
- the relaxing connection layer 15 does not contain a core material such as a woven fabric, a non-woven fabric, or a film. That is, it is desirable that the relaxing connection layer 15 be composed only of an inorganic filler, a thermosetting resin and a relaxing material.
- the inorganic filler used for the relaxation connection layer 15 is preferably composed of at least one or more of silica, alumina, and barium titanate.
- the particle size of the inorganic filler in the relaxation connection layer 15 is preferably 0.1 to 15 ⁇ m.
- the particle size of the inorganic filler is preferably smaller than the particle size of the conductive paste in order to prevent the powder of the conductive paste from flowing.
- the particle size of the conductive paste is usually 1 to 20 ⁇ m, as described below. Therefore, the particle size of the inorganic filler is practically 0.1 to 15 ⁇ m.
- the content of the inorganic filler in the relaxation connection layer 15 is preferably 70 to 90% by weight.
- the content of the inorganic filler is less than 70%, the amount of the inorganic filler that forms the relaxation connection layer 15 is less than the amount of the thermosetting resin, and the thermosetting resin is in the press state. When flowing, the inorganic filler also flows at the same time. If it exceeds 90%, the amount of resin of the relaxation connection layer 15 is too small, and the embedding and adhesion of the wiring are impaired.
- the elastomer as the relaxation material in the present embodiment is made of either an acrylic elastomer or a thermoplastic elastomer. Specifically, for example, polybutadiene, or a butadiene-based random copolymer rubber, or a copolymer having a hard segment and a soft segment is used.
- the content of the elastomer is preferably 0.2 to 5.0% by weight based on the total amount of the epoxy resin composition. This is because if the content of the elastomer is less than 0.2% by weight, the resin flow will be large, and if it is more than 50% by weight, the elasticity of the via 13 will be increased to deteriorate the reliability of the via 13.
- the inorganic filler and the elastomer or the rubber are dispersed in the thermosetting resin constituting the relaxation connection layer 15, whereby the elastomer segregates on the surface of the inorganic filler, thereby further suppressing the flowability of the inorganic filler. can do.
- the conductive material of the conductive paste filled in the vias 13 formed in the relaxed connection layer 15 of the present embodiment is made of at least one of copper, silver, gold, palladium, bismuth, tin and their alloys,
- the diameter is preferably 1 to 20 ⁇ m.
- the particle size of the conductive paste is generally 1 to 8 ⁇ m, but may be up to 20 ⁇ m due to the dispersion of the particle size distribution. Therefore, it is usually preferable to use one having a particle size of 1 to 20 ⁇ m, which is the particle size of the available conductive paste.
- a PET film is first attached to both sides of the relaxation connection layer 15, and a through hole extending from the PET film to the relaxation connection layer 15 is formed.
- the conductive paste is filled in the through holes to form the vias 13.
- the relaxation connection layer 15 in which the via 13 is formed which has a PET film on the surface, is obtained.
- the affixing connection layer 15 having a PET film is attached to the printed wiring boards 21a and 21b as follows. First, the PET film on one side of the relaxation connection layer 15 is peeled off and brought into close contact with the first printed wiring board 21b. Thereafter, the remaining PET film is peeled off, and another printed wiring board 21a is attached. This is because when the PET films on both sides of the relaxation connection layer 15 are peeled off simultaneously, the uncured state of the relaxation connection layer 15 is easily broken, which makes handling difficult. Therefore, only the PET film on either side is peeled off and laminated. Thus, as shown in FIG. 2B, the multilayer printed wiring board 11 is formed.
- the conductive paste which is the vias 13 of the relaxation connection layer 15 is stacked while being heated and pressurized on the wiring 12 formed on the surface layer of the printed wiring boards 21a and 21b. At the time of this lamination, the wiring 12 is embedded in the relaxed connection layer 15. By so doing, the conductive paste is further compressed, so the connectivity with the wiring 12 is significantly improved.
- the glass transition point (DMA method; Dynamic Mechanical Analysis (dynamic viscoelasticity measurement method)) of the relaxation connection layer 15 is 185 ° C. or higher, or the glass transition points of the printed wiring boards 21 a and 21 b provided above and below the relaxation connection layer 15. It is desirable that the temperature is higher by 10 ° C. or more as compared with. If the glass transition temperature of the relaxation connection layer 15 is less than 185 ° C., or the difference between the glass transition temperatures of the printed wiring boards 21 a and 21 b is less than 10 ° C., warping of the substrate occurs in a process requiring high temperature such as reflow. The swell may be in a complex shape or irreversible.
- FIG. 3 is a view showing a melt viscosity curve of the relaxation connection layer 15 of the present embodiment.
- Curve a represents the upper limit value of the relaxation connection layer 15 under the above-described conditions.
- Curve b represents the lower limit value of the relaxation connection layer 15 under the above-described conditions.
- Curve c shows the upper limit value of the relaxation connection layer 15 under the conditions described above.
- Curve d represents the lower limit value of the relaxation connection layer 15 under the above-described conditions. That is, the minimum melt viscosity of the relaxation connection layer 15 is preferably 1000 to 100000 Pa ⁇ s as shown by the arrow in FIG. If the minimum melt viscosity is less than 1000 Pa ⁇ s, the resin flow will be large, and if it exceeds 100000 Pa ⁇ s, adhesion failure with the printed wiring board or embedding failure in wiring may occur, which is inappropriate.
- the relaxation connection layer 15 may contain a colorant. In this case, the mountability and the light reflectivity are improved.
- thermosetting resin used for the relaxation connection layer 15 at least one thermosetting resin selected from an epoxy resin, a polybutadiene resin, a phenol resin, a polyimide resin, a polyamide resin, and a cyanate resin can be used.
- the relaxing connection layer 15 is not formed on the outermost layer of the multilayer printed wiring board 11. This is because the internal stress relaxation effect between the plurality of printed wiring boards 21a and 21b can not be obtained when formed in the outermost layer.
- the multilayer printed wiring board 11 as a layer for bonding the plurality of laminated printed wiring boards 21a and 21b, the product yield can be greatly improved and the cost can be reduced.
- the thermal expansion coefficient of the relaxation connection layer 15 of the present embodiment is desirably at least 65 ppm / ° C. or less, preferably smaller than the thermal expansion coefficient of the printed wiring boards 21 a and 21 b.
- the thermal expansion coefficient of the relaxation connection layer 15 is larger than the thermal expansion coefficient of the printed wiring boards 21a and 21b, or larger than 65 ppm / ° C., the internal stress generated at the time of heating and cooling may not be absorbed.
- the plurality of printed wiring boards 21a and 21b are not particularly limited as long as they are resin substrates such as through-hole wiring boards or ALIVH (any layer inner via holes) wiring boards having a full-layer IVH (inner via hole) structure. Or a multilayer substrate. Also, the printed wiring board 21 and the relaxing connection layer 15 may be alternately laminated in a plurality of layers.
- the insulating material used for the plurality of printed wiring boards 21a and 21b is a composite material of a glass woven fabric and an epoxy resin.
- the insulating material may be made of a composite material of a woven fabric composed of any of organic fibers selected from aramid and wholly aromatic polyester and a thermosetting resin.
- it is composed of any of p-aramid, polyimide, poly-p-phenylene benzobis oxazole, wholly aromatic polyester, PTFE, an organic fiber selected from polyethersulfone and polyetherimide, and glass fiber.
- the insulating material may be made of a composite of a non-woven fabric and a thermosetting resin.
- the insulating material may be made of a composite material in which a thermosetting resin layer is formed on both sides of at least one of synthetic resin films of polyphenylene sulfide and polyphenylene sulfide.
- FIG. 1 shows a mounting body 16 which constitutes the camera module manufactured as described above.
- the multilayer printed wiring board 11 is provided with the relaxed connection layer 15 as an inner layer, and therefore, the occurrence of warpage on the surface thereof is suppressed.
- the mounting body 16 produced using the multilayer printed wiring board 11 is not warped by internal stress generated at the time of heating and cooling such as solder reflow. Therefore, even when this mounting body 16 is soldered by, for example, solder reflow on another printed wiring board such as a mother board of a mobile phone, for example, between the holder 17 and the multilayer printed wiring board 11
- the warpage 8 and the gap 9b due to the thermal expansion coefficient do not occur.
- warpage 8 and peeling 9a as shown in FIG. 12 do not occur between the mounting body 16 and another printed wiring board on which the mounting body 16 is mounted.
- the multilayer printed wiring board 11 in which the relaxed connection layer 15 is provided in the inner layer as described above, the occurrence of warpage that is likely to occur at the time of solder reflow is suppressed.
- FIG. 4A is a cross-sectional view of multilayer printed wiring board 11 of the present embodiment shown in FIG.
- FIG. 4B is an enlarged cross-sectional view of a portion P of FIG. 4A.
- FIG. 4A is a multilayer printed wiring board 11 in which a two-layered printed wiring board 21 a and a four-layered printed wiring board 21 b are integrated with the relaxed connection layer 15 interposed therebetween.
- the wires 12a formed on the surface layer of the printed wiring boards 21a and 21b are both embedded in the relaxing connection layer 15.
- the via 13 formed in the relaxed connection layer 15 can be compressed by the thickness of the wiring 12a. The reliability of the part can be increased and its electrical resistance can be reduced.
- FIG. 4C is a multilayer printed wiring board 11 in which four printed wiring boards 21a and 21b are integrated by laminating them with the relaxing connection layer 15 interposed therebetween.
- the non-defective four-layer printed wiring boards 21a and 21b prepared separately are bonded to each other with the relaxation connection layer interposed therebetween to create the eight-layered multilayer printed wiring board 11, thereby eight layers at a time.
- the product yield can be enhanced as compared with the production of the printed wiring board 11 of
- FIG. 1 and FIGS. 4A to 4C explain the configuration in which the vias 13 are formed in the relaxed connection layer 15, the vias 13 need not necessarily be formed. That is, the vias 13 may not be formed, and the same effect can be obtained as long as a plurality of printed wiring boards are stacked in the relaxed connection layer.
- the printed wiring boards 21 a and 21 b are generated at the time of heating and cooling by integrating the plurality of multilayer or single layer printed wiring boards 21 a and 21 b by the relaxed connection layer 15. Can be prevented.
- FIGS. 5A to 5C and 6A to 6C are cross-sectional views for explaining the mechanism of the occurrence of warpage in the multilayer printed wiring board 11 when a simple adhesive layer is used.
- a multilayer printed wiring board 11 is obtained by integrating and connecting a plurality of printed wiring boards 21a and 21b in which the wiring 12 is formed on the surface layer using an adhesive layer 23 similar to the conventional one.
- the adhesive layer 23 is made of, for example, a prepreg obtained by impregnating a commercially available glass fiber with an epoxy resin.
- FIG. 5B is a cross-sectional view of the multilayer printed wiring board 11 integrally formed so as to bury the surface wiring 12 using the conventional adhesive layer 23 shown in FIG. 5A.
- internal stress or elongation of the printed wiring boards 21a and 21b at the time of heating
- 24a and 24b is generated when the multilayer printed wiring board 11 is heated.
- the length of the arrows of the internal stresses 24a and 24b indicates the magnitude of the generated internal stress (or the amount of elongation of the substrate at the time of heating).
- the internal stress 24a is larger than the internal stress 24b (internal stress 24a> internal stress 24b).
- Such a phenomenon occurs, for example, when the thermal expansion coefficient of the printed wiring board 21a is larger than the thermal expansion coefficient of the printed wiring board 21b.
- the adhesive layer 23 is also stretched following it.
- FIG. 5C shows the generation of internal stress (or contraction of the printed wiring board 21) at the time of cooling, contrary to FIG. 5B.
- the printed wiring board with the larger thermal expansion coefficient for example, the printed wiring board 21a
- a convex (or concave upward) warpage 24 occurs downward. This is because the conventional connection layer 23 is thermally cured during the heating shown in FIG. 5B.
- the size, direction, and degree of the warpage 24 are influenced by various factors of the printed wiring boards 21a and 21b.
- the cause of the warpage 24 is generated from a slight difference between the printed wiring boards 21a and 21b.
- the difference is considered to be material variation, thickness variation, and further, the size of the copper foil pattern. This is because the thermal expansion coefficients of the wiring 12 made of copper foil and the insulating layer 14 made of glass epoxy resin or the like are different.
- the density of the wiring pattern 12 and the like complicated warpage occurs in one printed wiring board.
- warpage also occurs due to the difference in the number of layers of the printed wiring boards 21a and 21b. For example, in the case of forming a six-layer product with two layers and four layers, the internal stress shown in FIG. 5B and FIG. 5C is likely to occur.
- the difference in residual copper ratio also affects. For example, the coefficient of thermal expansion of the copper foil becomes dominant as the residual copper percentage increases.
- 5A to 5C have described the case where the warpage 24 is generated by heating and cooling during the production. However, even after production (after completion as a product), the warp 24 occurs due to heating and cooling. The mechanism of the warpage 24 that occurs is generated by the difference between the thermal expansion coefficients of the cured conventional adhesive layer 23 and the printed wiring boards 21a and 21b.
- a multilayer printed wiring board 11 is obtained by integrating and connecting the plurality of printed wiring boards 21a and 21b in which the wiring 12 is formed on the surface layer with a relaxation adhesive layer 15.
- FIG. 6B is a cross-sectional view of the multilayer printed wiring board 11 integrally formed so as to bury the surface wiring 12 using the relaxed connection layer 15 shown in FIG. 6A.
- internal stress or elongation of the printed wiring boards 21a and 21b at the time of heating
- 24a and 24b occurs at the time of heating of the multilayer printed wiring board 11 at the time of solder reflow.
- the length of the arrows of the internal stresses 24a and 24b indicates the magnitude of the generated internal stress (or the amount of elongation of the substrate at the time of heating).
- the internal stress 24a is larger than the internal stress 24b (internal stress 24a> internal stress 24b).
- Such a phenomenon occurs, for example, when the thermal expansion coefficient of the printed wiring board 21a is larger than the thermal expansion coefficient of the printed wiring board 21b.
- the relaxing connection layer 15 relieves the internal stress.
- FIG. 6C shows the generation of internal stress (or contraction of the printed wiring board 21) when the multilayer printed wiring board 11 is cooled.
- the internal stress 24c the printed wiring board with the larger thermal expansion coefficient (for example, the printed wiring board 21a) shrinks more.
- the internal stress 24 c is relieved by the relaxed connection layer 15.
- the multilayer printed wiring board 11 can prevent the occurrence of warpage by the function of the relaxation connection layer 15 absorbing the internal stress generated at the time of heating and cooling.
- the thermal expansion coefficient of the relaxation connection layer 15 is smaller than that of the printed wiring boards 21a and 21b, it is possible to alleviate the warpage generated due to the thermal expansion difference of the printed wiring boards 21a and 21b.
- the Tg (glass transition point) of the relaxed connection layer 15 is higher than that of the printed wiring boards 21a and 21b, it is always more elastic than the printed wiring boards 21a and 21b in a temperature range assuming reflow, for example, room temperature to 260 ° C. Because of this, there is an effect of suppressing the warpage of the entire substrate.
- FIGS. 7A and 7B are cross-sectional views for explaining a method of manufacturing a POP which is a mounting body using a multilayer printed wiring board according to Embodiment 2 of the present invention.
- the multilayer printed wiring board 11 is configured by laminating the printed wiring boards 21 a and 21 b on the upper and lower surfaces of the relaxing connection layer 15.
- Each of the printed wiring boards 21a and 21b is a single layer.
- the interconnections 12 formed on the front and back surfaces of the printed wiring boards 21 a and 21 b are connected to each other by vias 13.
- an influence is caused by the difference between the thermal expansion coefficients of the printed wiring boards 21a and 21b.
- the difference in the thermal expansion coefficient is caused by, for example, the magnitude of the residual copper ratio, the variation in the thermal expansion coefficient of the base material, the density of the wiring 12, etc., as described above.
- the relaxing connection layer 15 can absorb the influence of the difference between the thermal expansion coefficients of the printed wiring boards 21a and 21b. Therefore, multilayer printed wiring board 11 free from the influence of warpage caused by the heating and cooling process can be obtained.
- the semiconductor element 25 is positioned and fixed on the multilayer printed wiring board 11 as shown by the arrow.
- the wiring 12 of the semiconductor element 25 and the wiring 12 of the surface layer of the printed wiring board 21a are connected by the wire 22 or the like to form a mounting body 16 as shown in FIG. 7B.
- the semiconductor element 25, the wiring 12, the wire 22 and the like are mounting members.
- the mounting body 16 is, for example, a package for an interposer (a kind of circuit board inserted between a fine semiconductor chip and a general printed wiring board) or a POP.
- the mounting body 16 is connected to another printed wiring board such as a motherboard by solder reflow or the like by the solder balls 26 formed on the back surface of the printed wiring board 21b.
- the conventional BGA when mounted on a motherboard or the like using solder balls 26, the conventional BGA has a pitch of about 1 mm, and the diameter of the solder balls 26 is large (for example, 800 microns).
- the diameter of the solder ball 26 becomes smaller (for example, a diameter of 500 microns or less), and even slight warpage of the printed wiring board 11 on the mounted side has a great influence on the mountability. I will give.
- the warp can be reduced by using the multilayer printed wiring board 11 in which the relaxing connection layer 15 is interposed between the printed wiring boards 21a and 21b.
- FIG. 8A and 8B are cross-sectional views for explaining the manufacturing process of POP.
- FIG. 8A shows how a plurality of mounts 16a and 16b are stacked and mounted by solder balls 26.
- the mounting body 16b is a mounting body obtained by the manufacturing method shown in FIGS. 7A and 7B.
- the mounting body 16 a is a mounting body in which the semiconductor element 25 is formed on the upper surface of the insulating layer 14 having the wiring 12 on the front and back surfaces.
- the mounting body 16b is stacked on the mounting body 16a as shown by the arrows, and the mounting body 16c is as shown in FIG. 8B.
- the mounting body 16c shown in FIG. 8B is mounted on yet another circuit board (not shown) such as a mobile phone motherboard, as indicated by an arrow.
- FIG. 9A is a mounting body created by the conventional method of a POP similar to the structure obtained in FIG. 8B. That is, in the POP shown in FIG. 9A, the single-layer printed wiring board 21a is laminated on the upper surface of the multilayer printed wiring board 21b by the solder balls 26a.
- the single layer printed wiring board 21 a is configured by connecting the wiring 12 formed on the surface of the insulating layer 14 and the semiconductor element 25 a by the wire 22.
- the wirings 12 formed on the front and back surfaces of the single layer printed wiring board 21a are connected by vias 13 penetrating the single layer printed wiring board 21a.
- the multilayer printed wiring board 21 b is configured by connecting the wiring 12 formed on the surface of the three-layered insulating layer 14 and the semiconductor element 25 b by the wire 22.
- the interconnections 12 formed on the front and back surfaces of the multilayer printed wiring board 21b and the interconnections 12 formed in the inner layer are interlayer connected by vias 13 penetrating the multilayer printed wiring board 21b.
- the multilayer printed wiring board 21 b is laminated only by the insulating layer 14.
- a mounting body composed of such a single-layer printed wiring board 21a and a multilayer printed wiring board 21b is mounted on another printed wiring board such as a motherboard by the solder balls 26b.
- the single layer printed wiring board 21a is mounted on the multilayer printed wiring board 21b with the solder balls 26a, or a mounting body formed of the single layer printed wiring board 21a and the multilayer printed wiring board 21b is used as another printed wiring board.
- the multilayer printed wiring board 21b is heated and cooled in a process such as mounting with the solder balls 26b.
- the multilayer printed wiring board 21b is likely to be warped 24 depending on the residual copper ratio, the presence or absence of the pattern, the thickness of the substrate, and the like. Therefore, for example, a break 27 occurs in the solder ball 26a.
- the amount of warpage per 10 mm square can be suppressed to 150 ⁇ m or less by using the multilayer printed wiring board 11 using the relaxed connection layer 15 as shown in FIGS. 7A and 7B.
- the amount of warpage can be suppressed to 30% or less of the diameter of the solder ball 26 by adjusting the thickness, the composition, and the like of the relaxation connection layer 15.
- Third Embodiment 10A and 10B are cross-sectional views for explaining an optical module which is a mounting body using a multilayer printed wiring board according to Embodiment 3 of the present invention.
- the mounting body 16 as an optical module is such that optical components such as the lens 19 fixed to the holder 17 are installed with high accuracy on the upper surface of the multilayer printed wiring board 11 according to the present invention shown in FIG. Implemented and configured.
- the lens 19 has an optical axis 20.
- a light emitting element such as a semiconductor laser, a light receiving semiconductor element, and the like (not shown) are mounted.
- the holder 17, the lens 19, the light emitting element, the light receiving semiconductor element, and the like are mounting members.
- the multilayer printed wiring board 11 As shown in FIGS. 2A and 2B, in the multilayer printed wiring board 11, the printed wiring board 21a and the printed wiring board 21b are stacked and connected by the relaxed connection layer 15. Therefore, the multilayer printed wiring board 11 hardly warps due to the step of heating and cooling due to the relaxation connection layer 15. As a result, even if the semiconductor laser or the like is soldered after the lens 19 or the like is mounted, the optical axis 20 does not shift. Therefore, the number of adjustment steps of the optical module can be reduced, and the product cost can be reduced.
- the wirings 12 of the front and back surfaces and the inner layer are connected by vias 13.
- FIG. 10B is a mounting body formed of the multilayer printed wiring board 21c manufactured only with the insulating layer 14 without using the relaxation connection layer.
- the relaxing connection layer 15 is not provided, a warp occurs during heating and cooling such as soldering, and a shift occurs in the optical axis 20.
- the variation in quality of the optical module becomes large, and the number of adjustment steps increases.
- optical module for example, a complex of an optical cable and a circuit component, or a light guide formed on the surface of a multilayer printed wiring board, or an optoelectronic module using an LED or a semiconductor laser, etc.
- this invention is not limited to these.
- the present invention is, for example, a camera which is a module for high definition of 2,000,000 pixels or more in a cellular phone. It is applicable also to a module etc. That is, the present invention can be applied to any mounting member that can be mounted on the multilayer printed wiring board of the present invention.
- the surface wiring is embedded in the relaxation connection layer side, and the relaxation connection layer has a relaxation material for relieving internal stress generated at the time of heating and cooling, whereby the thermal expansion of the printed wiring board It is possible to prevent warpage and swell due to Therefore, a multilayer printed wiring board with little warpage and waviness can be realized.
- the present invention is useful for packaging of devices requiring high accuracy such as a camera module, an optical module, and the like, as well as a POP, because the warp is small.
Abstract
Description
12,12a,12b 配線
13 ビア
14 絶縁層
15 緩和接続層
16,16a,16b,16c 実装体
17 ホルダ
18 撮像素子
19 レンズ
20 光軸
21a,21b プリント配線板
22 ワイヤー
23 接着層
24 反り
24a,24b,24c 内部応力
25 半導体素子
26,26a,26b ハンダボール
27 断線
以下本発明の実施の形態1について、図面を参照しながら説明する。
図7A、図7Bは本発明の実施の形態2における多層プリント配線板を用いた実装体であるPOPの製造方法を説明する断面図である。
図10A、図10Bは、本発明の実施の形態3における多層プリント配線板を用いた実装体である光学モジュールを説明する断面図である。図10Aにおいて、光学モジュールとしての実装体16は、図2A、図2Bで示した本発明による多層プリント配線板11の上面に、ホルダ17に固定したレンズ19などの光学部品を高精度に設置あるいは実装して構成される。レンズ19は光軸20を有している。光学部品としてはこれ以外に、図示していない、半導体レーザーなどの発光素子や受光半導体素子などが実装される。本実施の形態では、ホルダ17、レンズ19、発光素子、受光半導体素子などが実装部材である。多層プリント配線板11は、図2A、図2Bで示したように、プリント配線板21aとプリント配線板21bとが緩和接続層15により積層されて接続されている。したがって、多層プリント配線板11は、緩和接続層15により、加熱冷却の工程により反りが発生することはほとんどない。その結果、レンズ19などを実装した後で半導体レーザーなどをハンダ付けしても、光軸20がずれない。したがって、光学モジュールの調整工数を減らすことができ、製品コストを下げることができる。なお、多層プリント配線板21bは、表裏面や内層の配線12がビア13で接続されている。
Claims (12)
- 表層に配線が形成された複数のプリント配線板と、
複数の前記プリント配線板の間を接続する、無機フィラーと熱硬化性樹脂と内部応力を緩和する緩和材とを有する緩和接続層とから
構成される多層プリント配線板。 - 前記緩和接続層の厚さが30~300μmである請求項1記載の多層プリント配線板。
- 前記緩和材は、熱可塑性樹脂である請求項1記載の多層プリント配線板。
- 前記緩和材は、エラストマーまたはゴムである請求項1記載の多層プリント配線板。
- 前記緩和材は、ポリブタジエンまたはブタジエン系ランダム共重合ゴムまたはハードセグメントと、ソフトセグメントとを有する共重合体である請求項1記載の多層プリント配線板。
- 前記無機フィラーは、シリカ、アルミナ、チタン酸バリウムのうち少なくとも1つからなる請求項1に記載の多層プリント配線板。
- 前記無機フィラーの前記緩和接続層に対する含有量は70~90重量%である請求項1に記載の多層プリント配線板。
- 前記エラストマーは、アクリル系エラストマーまたは熱可塑性エラストマーからなり、前記緩和接続層に対する含有量は0.2~5.0重量%である請求項4に記載の多層プリント配線板。
- 前記無機フィラーの粒径が0.1~15μmである請求項1に記載の多層プリント配線板。
- 前記緩和接続層は、前記無機フィラーと前記熱硬化性樹脂と前記緩和材とのみから構成される請求項1に記載の多層プリント配線板。
- 前記緩和接続層は着色剤を含む請求項1に記載の多層プリント配線板。
- 表層に配線が形成された複数のプリント配線板と、複数の前記プリント配線板の間を接続する、無機フィラーと熱硬化性樹脂と内部応力を緩和する緩和材を有する緩和接続層とからなる多層プリント配線板と、
前記多層プリント配線板の表面に形成された実装部材
とから構成される多層プリント配線板を用いた実装体。
Priority Applications (2)
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CN2009801022537A CN101911852B (zh) | 2008-01-18 | 2009-01-16 | 多层印刷布线板及利用该布线板的安装体 |
US12/811,800 US8395056B2 (en) | 2008-01-18 | 2009-01-16 | Multilayer printed wiring board and mounting body using the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2008-008859 | 2008-01-18 | ||
JP2008008859A JP2009170753A (ja) | 2008-01-18 | 2008-01-18 | 多層プリント配線板とこれを用いた実装体 |
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WO2009090878A1 true WO2009090878A1 (ja) | 2009-07-23 |
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PCT/JP2009/000137 WO2009090878A1 (ja) | 2008-01-18 | 2009-01-16 | 多層プリント配線板およびそれを用いた実装体 |
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US (1) | US8395056B2 (ja) |
JP (1) | JP2009170753A (ja) |
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TW (1) | TW200938013A (ja) |
WO (1) | WO2009090878A1 (ja) |
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CN204669479U (zh) | 2013-03-27 | 2015-09-23 | 株式会社村田制作所 | 摄像头模块 |
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Also Published As
Publication number | Publication date |
---|---|
TW200938013A (en) | 2009-09-01 |
US20100276187A1 (en) | 2010-11-04 |
CN101911852A (zh) | 2010-12-08 |
CN101911852B (zh) | 2013-01-23 |
JP2009170753A (ja) | 2009-07-30 |
US8395056B2 (en) | 2013-03-12 |
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