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  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
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  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
  • C30B29/403—AIII-nitrides
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  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02455—Group 13/15 materials
  • H01L21/02458—Nitrides
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  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/01—Manufacture or treatment
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  • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
  • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
  • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials

Definitions

• the present invention relates to a nitride semiconductor device having a group III nitride layer structure on a group IV substrate surface such as silicon, germanium, diamond, or a mixed crystal in this group IV semiconductor system.
• Recent developments also allow epitaxial growth on a Si (IOO) substrate surface, but with poorer crystal quality.
• a Si (I O0) surface as a substrate surface for a group III nitride layer structure is of interest for applications in microelectronics because, for example, the integration of GaN-based components into the silicon electronics can be facilitated.
• growth on a substrate surface - as is common in the art in the linguistic usage - it can be assumed that this growth is epitaxial or took place.
• An epitaxially deposited layer is known to take over the lattice structure of the substrate on which it grows, or is based on the symmetry prescribed by them and takes over the lattice constants depending on the lattice mismatch even on thick monolayers to micrometers.
• the term "epitaxial” is therefore not necessarily additionally mentioned below when referring to growth on a substrate surface: known non-epitaxial deposition processes such as sputtering give rise to amorphous or polycrystalline, but in the best case textured, non-monocrystalline layers useful for optoelectronic devices today's standards are not suitable.
• the quality of the Group III nitride semiconductor layers fabricated on silicon (11-1) and particularly on silicon (001) is generally not as good as that of the still widely used sapphire or SiC substrates of hexagonal crystal structure.
• One reason for the poorer quality is a poorer lattice matching of GaN crystallites, or possibly of AIN crystallites used as seed layer, in particular their twisting, also called "twist", on the silicon surface, which usually has one after 1 ⁇ m layer growth Step dislocation density of more than 10 9 cm "2 result.
• thin-film devices such as high-efficiency LEDs, FETs, or MEMS on Si (100) is due to poor crystal quality, and to Si (1 1 1) due to a difficult removal of the substrate by etching difficult, just like z.
• a nitride semiconductor device having a group III-nitride layer structure which is epitaxially deposited on a substrate having a group IV substrate surface of a group IV cubic substrate material in which the group IV substrate surface, without consideration of a surface reconstruction, has a unit cell with a C2 symmetry, but no higher rotational symmetry than the C2 symmetry, the group III nitride layer structure immediately adjacent to the group IV Substrate surface a Ankeim harsh of either GaN or AIN or from ternary or quatermärem AI 1-x . y ln x Ga y N, 0 ⁇ x, y ⁇ 1 and x + y ⁇ 1.
• the Ankeim harsh is therefore made in the last case of AlInGaN, AlInN, InGaN or Al-GaN.
• a nitride semiconductor device is here referred to a semiconductor device having a group-III nitride layer structure.
• a Group III nitride layered structure is a layered structure containing, in various embodiments, either a Group III nitride layer or a plurality of Group III nitride layers.
• the group III nitride layer structure may consist of a single group III nitride layer.
• a group III nitride layer is a material layer of a compound containing at least one group III element and nitrogen.
• other group V elements may also be present in amounts such that nitrogen has at least 50% of the group V atoms of the material.
• the ratio of atoms of group III elements to atoms of group V elements is 1: 1 in group III nitrides.
• group V elements other than nitrogen may be useful for further reducing lattice mismatch, but may be solely due to the needs of a particular application of the nitride semiconductor device.
• a group IV substrate surface is a substrate surface formed by a group IV substrate material, that is, a material forming the substrate surface from one or more group IV elements.
• a group IV substrate material thus belongs to the system Ci- x- ySi ⁇ Gey with 0 ⁇ x, y ⁇ 1 and x + y ⁇ 1.
• the group IV substrate surface forms one in the nitride semiconductor component for the purposes of the definition as ideally assumed interface between the Group IV material and the Group III nitride layer structure.
• the group IV substrate surface may be the surface of a wafer of the group IV material or the surface of a thin film, such as on a foreign substrate or on a silicon-on-insulator (SOI) type substrate.
• SOI silicon-on-insulator
• the C2 symmetry belongs to the family of finite cyclic symmetry groups in the Euclidean plane. It forms a discrete symmetry group, whose symmetry operations do not include any displacements or mirror-images, but rotations about a point by multiples of 180 °.
• the group IV substrate surface is characterized by a substrate surface formed by unit cells of group IV atoms, with an elementary cell imaged within 360 degrees of rotation divided by two - that is, 180 degrees - and multiples thereof becomes. Therefore, in the presence of the C2 symmetry, one also speaks of a twofold symmetry (English, twofold symmetry).
• a unit cell with C2 symmetry and with no higher rotational symmetry has a (trivial) monotone, ie C1 symmetry and a twofold, ie C2 symmetry, but no higher rotational symmetry, for example, no C3 or C4 symmetry.
• C1 is the symmetry group of a completely unbalanced object, with identity as the only element.
• any surface reconstruction will be disregarded for the purposes of the definition in the context of the present description and the claims.
• the group IV substrate material in a hypothetical section in a plane parallel to its substrate surface also has an elementary cell with a C2 symmetry, but with no higher rotational symmetry than the C2 symmetry.
• such a substrate surface is also referred to as a surface with (only) twofold symmetry.
• Group IV substrate surfaces having a unit cell with a C2 symmetry, but no higher rotational symmetry than the C2 symmetry, have the advantage that they have in one direction a particularly high lattice match to group III nitrides and so the single crystal epitaxial Allow deposition of a group III nitride layer structure with particularly high crystallographic quality. This reduces the defect density in the group III nitride layer structure, whereby the performance and life of the nitride semiconductor device can be improved.
• the claimed nitride semiconductor device can in this aspect
• the following description will mostly include examples using silicon as the substrate material. However, this is not to be understood as limiting the applicability of the invention.
• the invention is applicable with respect to the substrate material for the entire system Ci -x- ySi ⁇ Gey with 0 ⁇ x, y ⁇ 1 and x + y ⁇ 1.
• group IV substrate materials other than silicon other lattice parameters of the crystal lattice are known to exist in the substrate surface.
• the group III-nitride layer structure of the nitride semiconductor device immediately adjacent to the group IV substrate surface has a seed layer AI 1 -x .yln x Ga y N.
• some binary or ternary or quaternary material for a seed layer is most suitably selectable for some twofold group IV substrate surfaces due to the ratios of the lattice parameters.
• a low lattice mismatch between the Group IV substrate surface and the seed layer is of great importance for the crystalline quality of the Group III nitride layer structure in a large group of different nitride semiconductor devices.
• the crystalline quality in turn influences the performance parameters and the lifetime of (opto) electronic components.
• AlN is a suitable material for a seed layer.
• lattice matching of the Si (110) surface to GaN is also good. Therefore, a GaN seed layer is also suitable.
• the lattice mismatch here is about 2% in the direction that has a small mismatch also in the AIN and about 16.9% in the other direction.
• meltback etching is the reaction of the gallium of a growing Group III nitride layer with the silicon of the substrate material.
• the Al content of the seed layer on the group III elements in particular when MOVPE is used to avoid the meltback etching, in some embodiments 90% or greater, in relation to the total number of group Ill contained. Atoms, and the proportion of Ga accordingly not more than 10%.
• an alloy of Si with Ge is present as a Group IV substrate material. This substrate material allows deposition with less likelihood of the occurrence of meltback etching.
• An appropriately selected SiGe alloy can, moreover, enable a particularly good lattice matching of a GaN seed layer.
• the group IV substrate surface is a Si (HO) surface. This has a very low lattice mismatch in one direction to the c-axis oriented and m-plane AIN and thus allows better orientation of the layers of the group III nitride layer structure on the substrate. With similarly favorable lattice mismatch properties to AIN, Group IV substrate materials can be used with other Group IV ⁇ 1 10 ⁇ substrate surfaces.
• Substrates having a Si (H O) substrate surface also have the advantage that they are commercially available in large quantities and therefore can be procured easily and at low cost.
• the ⁇ 120 ⁇ group IV substrate surfaces are useful for forming other embodiments, and also other higher indexed surfaces of the type ⁇ nmO ⁇ , where n, m are non-zero integers, are also of interest for the growth of a high-value group illusory.
• Nitride layer structure but also, for example, a high-grade Group III nitride single layer such as a GaN layer.
• a method of fabricating a nitride semiconductor device comprises epitaxially depositing a group of semiconductor devices.
• pel III-nitride layer structure on a group IV substrate surface of a group IV substrate substrate material having a cubic crystal structure wherein the group III nitride layer structure is deposited on a group IV substrate surface, for the purpose of the conceptual definition without regard to surface reconstruction, has a unit cell with a C2 symmetry but no higher rotational symmetry than the C2 symmetry, and where immediately adjacent to the group IV substrate surface a seed layer of either AIN, GaN or ternary or quaternary AI 1-x .
• y ln x Ga y N, 0 ⁇ x, y ⁇ 1 and x + y ⁇ 1 is deposited epitaxially.
• the method includes partially or completely dry or wet-chemical removal of the substrate after deposition of the Group III nitride layer structure.
• Figure 2 is a cross-sectional view of an embodiment of a
• Nitride semiconductor device having a Group III nitride layer structure
• FIG. 1 shows a plan view of a group IV substrate surface in the form of a) silicon (IOO), b) silicon (1 10) for explaining an exemplary embodiment of a nitride semiconductor component and for comparison with solutions from the prior art.
• - and c) silicon (11 1) surface each with Al 1-x . y ln x Ga y N coverage, 0 ⁇ x, y ⁇ 1 and x + y ⁇ 1.
• FIG. 1 b) is relevant, the two other FIGS. 1 a) and 1 c) make comparison conditions on already used in the prior art substrate surfaces.
• the best lattice matching in one direction is obtained by using ternary materials for Al 0 97In 0 03N and Al O 7sGao 22 N. It is even a slight addition of Ga and in helpful the material parameters to improve. When using a quaternary material, the ideal In and Ga concentrations are correspondingly lower. However, higher concentrations are possible and advantageous depending on the process, since then also the lattice mismatch in the [1-10] direction, but at the expense of perpendicular thereto, is reduced.
• the AI 1-x .yln x Ga y N land cover the silicon substrate surface forms, in the present embodiment of Fig. 1 b) a germination layer at the start of growing a Group III nitride layer structure on the substrate surface, as commonly used for the Growth of GaN finds use.
• the following considerations are to be understood as examples.
• other combinations of Group IV substrate surface materials and the Group III nitride layer structure growing thereon could also be used for illustration.
• the Al atoms are arranged at vertices of hexagonal unit cells.
• y In x Ga y N is extend in (l ⁇ TOO -directions.
• the distances are 5.41 ⁇ in the non-ideal use of AIN, and may, for example, with Al or Al O 97ln O o3N 78Ga 0 022 N to 5:43 ⁇ is reduced to a mismatch of 0%, thus providing improved layer characteristics over use of an AIN seed layer
• the shorter distance of the Si unit cell extends in (l ⁇ ) directions and is 5.43 ⁇ , so the mismatch is in the direction AI (GaJn) N (lT ⁇ )
• AIN On most highly indexed surfaces with a twofold symmetry, AIN also grows preferentially with c-axis orientation.
• the ⁇ 410 ⁇ surfaces are advantageous for silicon, since every 10.86 ⁇ repeats the structure, with a mismatch of approximately 7.5% for in two Al 097 0 O O 78 sn or AI Gao 22 N unit cells in the c direction (8.6% AIN) at 0% in the vertical plane for m-AI (GaJn) N (0.37% for AIN) are very low mismatch values.
• an area of the type ⁇ 411 ⁇ with I ⁇ 2 and ⁇ 1 14 ⁇ can be used, since this results in a better lattice matching.
• the resulting nitride semiconductor layer has a tensile stress that may be slightly anisotropic due to the thermal mismatch of the materials after cooling unless countermeasures are taken during growth by pre-stressing. This is due to the low symmetry of the crystal orientation, which is not isotropic, in contrast to the tridentate Si (11) (Fig. 1 c) or fivefold Si (100) orientation. H. in which Si ⁇ 100> and Si ⁇ 1 10> directions are different. Therefore, detached layers can be recognized by an anisotropic strain, which can be detected, for example, with curvature or better X-ray measurements.
• Si (11 1) substrate can be removed only wet-chemically in a reasonable time by working with the latter etching solution.
• this dissolves many metals and thus makes it more difficult to detach nitride semiconductor component layers bonded to substrates, which are to be further processed as a thin film.
• the use of surfaces with twofold symmetry of Ci -xy Si ⁇ Ge y (0 ⁇ x, y ⁇ 1, x + y ⁇ 1) has the additional advantage that the wet chemical cal etching can be facilitated.
• the (11) surface is typically chemically more stable for comparison and therefore less likely to be removed in a wet chemical etch step.
• the use of surfaces with only twofold symmetry therefore eliminates the expense of laboriously protecting the novel carrier with acid-resistant substances, the adhesion-promoting layer, frequently metal layers such as Au / Sn, for the new carrier.
• the invention is applicable to any nitride semiconductor device having a Group III nitride layer structure.
• Optical, optoelectronic and electronic components such as light-emitting diodes, laser diodes, transistors and MEMS components are to be understood as application examples which, however, do not exhaust the applicability of the invention.
• Their advantage lies in a high achievable crystal quality, the growth of c-, a- and m-plane GaN and in the easy way to remove the substrate in whole or in part, as this wet-chemically lighter than otherwise used (1 11) -oriented Substrates is possible.
• FIG. 2 shows a schematic view of the layer structure of a nitride semiconductor device 100.
• the nitride semiconductor device 100 may form an intermediate in the production of a thin-film nitride semiconductor device.
• Fig. 2 The illustration in Fig. 2 is not to scale. In particular, the exact ratio of the layer thicknesses of the individual layers shown to one another can not be determined from the FIG. The layer thickness ratios shown in the figure only provide a very rough indication. In the following description, the shortage of representing half process aspects in parallel to device aspects will be explained.
• the nitride semiconductor product 100 includes a group III nitride layer structure 102 on a silicon wafer 104.
• the growth surface of the wafer used which is perpendicular to the paper plane of FIG. 1, is a (HO) silicon surface.
• a silicon wafer may also be an SOI substrate or any another substrate, preferably with a (HO) silicon surface, may be used.
• A is a ternary or quaternary Nitridankeim harsh in combination with a
• Buffer layer, B a masking layer
• C nitride semiconductor layers in particular n-type GaN layers
• E a p-doped nitride semiconductor cap layer, in particular p-GaN and
• the growth surface of the wafer 104 Prior to depositing layers, the growth surface of the wafer 104 is passivated. This means that they lung either by wet chemical treatment or is deoxidized by heating in vacuum or in hydrogen at temperatures above 1000 0 C and a hydrogen-terminated surface is generated.
• the seed layer 106 has a thickness of between 10 and 50 nm.
• a layer thickness of at most 400 nm is formed.
• Suitable is an Al 1-xy In x Ga y N seed layer, O ⁇ x, y ⁇ 1 and x + y ⁇ 1, (also referred to as Ankeim harsh), either at low temperature, ie below 1000 0 C, for example 600 to 800 0 C or at high temperature, ie ordinary growth temperatures of Al 1-x . y ln x Ga y N above 1000 0 C, is grown.
• the optional buffer layer is preferably also made of Al 1-x . y ln x Ga y N or AIN and is applied at high growth temperatures.
• the buffer layer can also consist of AIGaN. When using AIGaN, the seed layer may also have a greater thickness, for example about 600 nm.
• Nitriding of the substrate can lead to unwanted polycrystalline growth, ie non-epitaxial growth.
• a masking layer 108 of silicon nitride is deposited on the graft and buffer layer 106 composite. This is done by simultaneously passing a silicon precursor such as silane or disilane or an organic silicon compound, and a nitrogen precursor such as ammonia or dimethylhydrazine. On the growth surface, the two precursors react to form silicon nitride.
• a silicon precursor such as silane or disilane or an organic silicon compound
• a nitrogen precursor such as ammonia or dimethylhydrazine
• the layer thickness of a GaN layer 110 deposited thereon is between 800 and 1600 nm.
• An aluminum-containing nitride semiconductor intermediate layer in the form of an (optional) low-temperature AlN intermediate layer 12 is then deposited for the strain engineering.
• the low temperature AlN interlayer has a thickness of 8 to 15 nm here.
• the insertion of the low-temperature AlN intermediate layer 112 makes it possible to achieve a higher overall layer thickness of the GaN layer by growing a succession of further GaN layers and low-temperature AlN interlayers.
• the low temperature AlN interlayer 1 12 follows accordingly second GaN layer 114 again from about 800 to 1600 nm thickness, again followed by another low-temperature AlN interlayer 1 15.
• a third GaN layer 116 is deposited.
• a second masking layer 1 17 is deposited from SiN.
• the second SiN masking layer 117 brings about a reduction in the dislocation density in the subsequent fourth GaN layer 1 18.
• the four GaN layers 110, 114, 116 and 118 are n-doped. The doping takes place during growth by adding a suitable dopant precursor.
• this multi-quantum well structure 120 is deposited on the fourth GaN layer 1 18 .
• the material choice and precise layer structure of this multi-quantum well structure 120 is set according to the desired wavelength of the light emission.
• the parameters to be set for this such as layer stoichiometry and layer thickness, are known to the person skilled in the art.
• the addition of indium reduces the band gap of a nitride semiconductor, for example starting from pure GaN, in the direction of the band gap of indium nitride.
• the band gap is increased in the direction of the value of AIN. In this way, a light emission with a desired wavelength can be set, which lies between the red and the ultraviolet spectral range.
• multi-quantum well structure 120 may optionally be provided an injection barrier of about 10 to 30 nm thickness, which is not shown in Fig. 1.
• 3a) to 3f) show different process stages in the production of a light-emitting diode from the nitride semiconductor component of FIG. 1.
• the method procedure described here follows the production of the nitride semiconductor component of FIG.
• a top-side metallization is first provided on the nitride semiconductor component 100. This serves on the one hand for subsequent bonding to a carrier 126 and on the other hand to improve the light extraction from the resulting device.
• the carrier 126 is made of copper or AISi and has a metallization 130 on a side 128 which is used for bonding.
• FIG. 3b) shows a process stage after bonding. The bonding is carried out at a temperature of 280 0 C. The use of such a low temperature has the advantage that no additional strains caused by the thermal cycle during bonding.
• the Si wafer 104 is removed. This is shown schematically in Fig. 3c).
• the Si wafer 104 is removed by grinding and etching.
• the etching can be wet or dry chemical. Compared with the use of substrates with (11) growth surface, the removal is significantly facilitated.
• the top is patterned by etching.
• the etching for example with KOH or H 3 PO 4, produces pyramidal structures which improve the light extraction from the component (FIG. 3 e).
• contact structures are created.
• a negative contact 136 is provided on the surface and a contact to be poled positively on the carrier (FIG. 3f).
• the layer growth according to the invention is possible on large substrates and thus allows either the production of large components or a cost-efficient production of a large number of smaller components.
• the described process management does not require the usual laser stripping with the use of sapphire substrates and is therefore simpler and cheaper. Only for the production of backside contact and a structuring before the separation of the components photolithography steps are required.

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